1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s 3 4;; This used to cause a backend crash about not being able to 5;; select ROTL. Make sure if generates the basic ushr/shl. 6define <2 x i64> @testcase(ptr %in) { 7; CHECK-LABEL: testcase: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ldr q1, [x0] 10; CHECK-NEXT: shl v0.2d, v1.2d, #56 11; CHECK-NEXT: usra v0.2d, v1.2d, #8 12; CHECK-NEXT: ret 13 %1 = load <2 x i64>, ptr %in 14 %2 = lshr <2 x i64> %1, <i64 8, i64 8> 15 %3 = shl <2 x i64> %1, <i64 56, i64 56> 16 %4 = or <2 x i64> %2, %3 17 ret <2 x i64> %4 18} 19 20;; This used to cause a miscompile because rot combine 21;; doesn't handle negative shift well. 22define i5 @pr59898(i5 %x) { 23; CHECK-LABEL: pr59898: 24; CHECK: // %bb.0: 25; CHECK-NEXT: ubfx w8, w0, #1, #4 26; CHECK-NEXT: orr w0, w8, w0, lsl #4 27; CHECK-NEXT: ret 28 %r1 = call i5 @llvm.fshr.i5(i5 %x, i5 %x, i5 3) 29 %r2 = call i5 @llvm.fshl.i5(i5 %r1, i5 %r1, i5 2) 30 ret i5 %r2 31} 32 33declare i5 @llvm.fshl.i5(i5, i5, i5) 34declare i5 @llvm.fshr.i5(i5, i5, i5) 35