xref: /llvm-project/llvm/test/CodeGen/AArch64/replace-load-with-shrink-store-indexed-crash.ll (revision f79b0333fc368d8dc7a780a100370a29415bdf91)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
4target triple = "arm64-apple-macosx13.0.0"
5
6define void @_Z1hP1f(ptr %j) {
7; CHECK-LABEL: _Z1hP1f:
8; CHECK:       // %bb.0: // %entry
9; CHECK-NEXT:    mov x8, x0
10; CHECK-NEXT:  .LBB0_1: // %for.body
11; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
12; CHECK-NEXT:    ldr w9, [x8]
13; CHECK-NEXT:    mov w10, w9
14; CHECK-NEXT:    bfi w10, w9, #16, #16
15; CHECK-NEXT:    str w10, [x8], #4
16; CHECK-NEXT:    str w9, [x0]
17; CHECK-NEXT:    b .LBB0_1
18entry:
19  br label %for.body
20
21for.body:                                         ; preds = %for.body, %entry
22  %indvars.iv1 = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
23  %arrayidx3 = getelementptr i32, ptr %j, i64 %indvars.iv1
24  %0 = load i32, ptr %arrayidx3, align 4
25  %and = and i32 %0, 65535
26  %or = mul i32 %and, 65537
27  store i32 %or, ptr %arrayidx3, align 4
28  store i32 %0, ptr %j, align 4
29  %indvars.iv.next = add i64 %indvars.iv1, 1
30  br label %for.body
31}
32