1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -frame-pointer=all -o - %s | FileCheck %s 3 4; When generating DAG selection tables, TableGen used to only flag an 5; instruction as needing a chain on its own account if it had a built-in pattern 6; which used the chain. This meant that the AArch64 load/stores weren't 7; recognised and so both loads from %locvar below were coalesced into a single 8; LS8_LDR instruction (same operands other than the non-existent chain) and the 9; increment was lost at return. 10 11; This was obviously a Bad Thing. 12 13declare void @bar(ptr) 14 15define i64 @test_chains() { 16; CHECK-LABEL: test_chains: 17; CHECK: ; %bb.0: 18; CHECK-NEXT: sub sp, sp, #32 19; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill 20; CHECK-NEXT: add x29, sp, #16 21; CHECK-NEXT: .cfi_def_cfa w29, 16 22; CHECK-NEXT: .cfi_offset w30, -8 23; CHECK-NEXT: .cfi_offset w29, -16 24; CHECK-NEXT: sub x0, x29, #1 25; CHECK-NEXT: bl _bar 26; CHECK-NEXT: ldurb w8, [x29, #-1] 27; CHECK-NEXT: add x8, x8, #1 28; CHECK-NEXT: sturb w8, [x29, #-1] 29; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload 30; CHECK-NEXT: and x0, x8, #0xff 31; CHECK-NEXT: add sp, sp, #32 32; CHECK-NEXT: ret 33 34 %locvar = alloca i8 35 36 call void @bar(ptr %locvar) 37 38 %inc.1 = load i8, ptr %locvar 39 %inc.2 = zext i8 %inc.1 to i64 40 %inc.3 = add i64 %inc.2, 1 41 %inc.4 = trunc i64 %inc.3 to i8 42 store i8 %inc.4, ptr %locvar 43 44 45 %ret.1 = load i8, ptr %locvar 46 %ret.2 = zext i8 %ret.1 to i64 47 ret i64 %ret.2 48} 49