1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O3 -mtriple=aarch64-linux-gnu < %s | FileCheck %s 3 4define i32 @test(i32 %input, i32 %n, i32 %a) { 5; CHECK-LABEL: test: 6; CHECK: // %bb.0: // %entry 7; CHECK-NEXT: cbz w1, .LBB0_2 8; CHECK-NEXT: // %bb.1: 9; CHECK-NEXT: mov w0, wzr 10; CHECK-NEXT: ret 11; CHECK-NEXT: .LBB0_2: // %bb.0 12; CHECK-NEXT: add w8, w0, w1 13; CHECK-NEXT: mov w0, #100 // =0x64 14; CHECK-NEXT: cmp w8, #1 15; CHECK-NEXT: b.le .LBB0_7 16; CHECK-NEXT: // %bb.3: // %bb.0 17; CHECK-NEXT: cmp w8, #2 18; CHECK-NEXT: b.eq .LBB0_10 19; CHECK-NEXT: // %bb.4: // %bb.0 20; CHECK-NEXT: cmp w8, #4 21; CHECK-NEXT: b.eq .LBB0_11 22; CHECK-NEXT: // %bb.5: // %bb.0 23; CHECK-NEXT: cmp w8, #200 24; CHECK-NEXT: b.ne .LBB0_12 25; CHECK-NEXT: // %bb.6: // %sw.bb7 26; CHECK-NEXT: add w0, w2, #7 27; CHECK-NEXT: ret 28; CHECK-NEXT: .LBB0_7: // %bb.0 29; CHECK-NEXT: cbz w8, .LBB0_13 30; CHECK-NEXT: // %bb.8: // %bb.0 31; CHECK-NEXT: cmp w8, #1 32; CHECK-NEXT: b.ne .LBB0_12 33; CHECK-NEXT: // %bb.9: // %sw.bb1 34; CHECK-NEXT: add w0, w2, #3 35; CHECK-NEXT: ret 36; CHECK-NEXT: .LBB0_10: // %sw.bb3 37; CHECK-NEXT: add w0, w2, #4 38; CHECK-NEXT: ret 39; CHECK-NEXT: .LBB0_11: // %sw.bb5 40; CHECK-NEXT: add w0, w2, #5 41; CHECK-NEXT: .LBB0_12: // %return 42; CHECK-NEXT: ret 43; CHECK-NEXT: .LBB0_13: // %sw.bb 44; CHECK-NEXT: add w0, w2, #1 45; CHECK-NEXT: ret 46entry: 47 %b = add nsw i32 %input, %n 48 %cmp = icmp eq i32 %n, 0 49 br i1 %cmp, label %bb.0, label %return 50 51bb.0: 52 switch i32 %b, label %return [ 53 i32 0, label %sw.bb 54 i32 1, label %sw.bb1 55 i32 2, label %sw.bb3 56 i32 4, label %sw.bb5 57 i32 200, label %sw.bb7 58 ] 59 60sw.bb: 61 %add = add nsw i32 %a, 1 62 br label %return 63 64sw.bb1: 65 %add2 = add nsw i32 %a, 3 66 br label %return 67 68sw.bb3: 69 %add4 = add nsw i32 %a, 4 70 br label %return 71 72sw.bb5: 73 %add6 = add nsw i32 %a, 5 74 br label %return 75 76sw.bb7: 77 %add8 = add nsw i32 %a, 7 78 br label %return 79 80return: 81 %retval.0 = phi i32 [ %add8, %sw.bb7 ], [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 100, %bb.0 ], [ 0, %entry ] 82 ret i32 %retval.0 83} 84 85