1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64 -mattr=+v8.9a -mattr=+sve -mattr=+rcpc3 < %s | FileCheck %s 3; RUN: llc -mtriple=aarch64 -mattr=+v8.9a -mattr=+sve < %s | FileCheck %s 4 5; Show what happens with RCPC3 for extract/insert into SVE vectors. 6; Currently there is no RCPC3 codegen expected for this. 7 8define hidden <vscale x 2 x i64> @test_load_sve_lane0(ptr nocapture noundef readonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr { 9; CHECK-LABEL: test_load_sve_lane0: 10; CHECK: // %bb.0: 11; CHECK-NEXT: ldapr x8, [x0] 12; CHECK-NEXT: ptrue p0.d, vl1 13; CHECK-NEXT: mov z0.d, p0/m, x8 14; CHECK-NEXT: ret 15 %1 = load atomic i64, ptr %a acquire, align 8 16 %vldap1_lane = insertelement <vscale x 2 x i64> %b, i64 %1, i64 0 17 ret <vscale x 2 x i64> %vldap1_lane 18} 19 20define hidden <vscale x 2 x i64> @test_load_sve_lane1(ptr nocapture noundef readonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr { 21; CHECK-LABEL: test_load_sve_lane1: 22; CHECK: // %bb.0: 23; CHECK-NEXT: mov w8, #1 // =0x1 24; CHECK-NEXT: index z1.d, #0, #1 25; CHECK-NEXT: ptrue p0.d 26; CHECK-NEXT: mov z2.d, x8 27; CHECK-NEXT: ldapr x8, [x0] 28; CHECK-NEXT: cmpeq p0.d, p0/z, z1.d, z2.d 29; CHECK-NEXT: mov z0.d, p0/m, x8 30; CHECK-NEXT: ret 31 %1 = load atomic i64, ptr %a acquire, align 8 32 %vldap1_lane = insertelement <vscale x 2 x i64> %b, i64 %1, i64 1 33 ret <vscale x 2 x i64> %vldap1_lane 34} 35 36define hidden void @test_store_sve_lane0(ptr nocapture noundef writeonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr { 37; CHECK-LABEL: test_store_sve_lane0: 38; CHECK: // %bb.0: 39; CHECK-NEXT: fmov x8, d0 40; CHECK-NEXT: stlr x8, [x0] 41; CHECK-NEXT: ret 42 %1 = extractelement <vscale x 2 x i64> %b, i64 0 43 store atomic i64 %1, ptr %a release, align 8 44 ret void 45} 46 47define hidden void @test_store_sve_lane1(ptr nocapture noundef writeonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr { 48; CHECK-LABEL: test_store_sve_lane1: 49; CHECK: // %bb.0: 50; CHECK-NEXT: mov x8, v0.d[1] 51; CHECK-NEXT: stlr x8, [x0] 52; CHECK-NEXT: ret 53 %1 = extractelement <vscale x 2 x i64> %b, i64 1 54 store atomic i64 %1, ptr %a release, align 8 55 ret void 56} 57