1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand -aarch64-enable-sink-fold=true %s -o - | FileCheck %s 3 4define i32 @rndr(ptr %__addr) { 5; CHECK-LABEL: rndr: 6; CHECK: // %bb.0: 7; CHECK-NEXT: mrs x9, RNDR 8; CHECK-NEXT: mov x8, x0 9; CHECK-NEXT: cset w10, eq 10; CHECK-NEXT: str x9, [x8] 11; CHECK-NEXT: and w0, w10, #0x1 12; CHECK-NEXT: ret 13 %1 = tail call { i64, i1 } @llvm.aarch64.rndr() 14 %2 = extractvalue { i64, i1 } %1, 0 15 %3 = extractvalue { i64, i1 } %1, 1 16 store i64 %2, ptr %__addr, align 8 17 %4 = zext i1 %3 to i32 18 ret i32 %4 19} 20 21 22define i32 @rndrrs(ptr %__addr) { 23; CHECK-LABEL: rndrrs: 24; CHECK: // %bb.0: 25; CHECK-NEXT: mrs x9, RNDRRS 26; CHECK-NEXT: mov x8, x0 27; CHECK-NEXT: cset w10, eq 28; CHECK-NEXT: str x9, [x8] 29; CHECK-NEXT: and w0, w10, #0x1 30; CHECK-NEXT: ret 31 %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs() 32 %2 = extractvalue { i64, i1 } %1, 0 33 %3 = extractvalue { i64, i1 } %1, 1 34 store i64 %2, ptr %__addr, align 8 35 %4 = zext i1 %3 to i32 36 ret i32 %4 37} 38 39declare { i64, i1 } @llvm.aarch64.rndr() 40declare { i64, i1 } @llvm.aarch64.rndrrs() 41