xref: /llvm-project/llvm/test/CodeGen/AArch64/predicated-add-sub.ll (revision cc82f1290a1e2157a6c0530d78d8cc84d2b8553d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux"
5
6define <vscale x 8 x i8> @zext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
7; CHECK-LABEL: zext.add.8xi8:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    mov z1.h, #1 // =0x1
10; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
11; CHECK-NEXT:    ret
12  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
13  %result = add <vscale x 8 x i8> %a, %extend
14  ret <vscale x 8 x i8> %result
15}
16
17define <vscale x 4 x i16> @zext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
18; CHECK-LABEL: zext.add.4xi16:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    mov z1.s, #1 // =0x1
21; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
22; CHECK-NEXT:    ret
23  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
24  %result = add <vscale x 4 x i16> %a, %extend
25  ret <vscale x 4 x i16> %result
26}
27
28define <vscale x 2 x i32> @zext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
29; CHECK-LABEL: zext.add.2xi32:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    mov z1.d, #1 // =0x1
32; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
33; CHECK-NEXT:    ret
34  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
35  %result = add <vscale x 2 x i32> %a, %extend
36  ret <vscale x 2 x i32> %result
37}
38
39define <vscale x 16 x i8> @zext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
40; CHECK-LABEL: zext.add.16xi8:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    mov z1.b, #1 // =0x1
43; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
44; CHECK-NEXT:    ret
45  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
46  %result = add <vscale x 16 x i8> %a, %extend
47  ret <vscale x 16 x i8> %result
48}
49
50define <vscale x 8 x i16> @zext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
51; CHECK-LABEL: zext.add.8xi16:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    mov z1.h, #1 // =0x1
54; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
55; CHECK-NEXT:    ret
56  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
57  %result = add <vscale x 8 x i16> %a, %extend
58  ret <vscale x 8 x i16> %result
59}
60
61define <vscale x 4 x i32> @zext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
62; CHECK-LABEL: zext.add.4xi32:
63; CHECK:       // %bb.0:
64; CHECK-NEXT:    mov z1.s, #1 // =0x1
65; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
66; CHECK-NEXT:    ret
67  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
68  %result = add <vscale x 4 x i32> %a, %extend
69  ret <vscale x 4 x i32> %result
70}
71
72define <vscale x 2 x i64> @zext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
73; CHECK-LABEL: zext.add.2xi64:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    mov z1.d, #1 // =0x1
76; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
77; CHECK-NEXT:    ret
78  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
79  %result = add <vscale x 2 x i64> %a, %extend
80  ret <vscale x 2 x i64> %result
81}
82
83define <vscale x 8 x i32> @zext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
84; CHECK-LABEL: zext.add.8xi32:
85; CHECK:       // %bb.0:
86; CHECK-NEXT:    mov z2.s, #1 // =0x1
87; CHECK-NEXT:    punpkhi p1.h, p0.b
88; CHECK-NEXT:    punpklo p0.h, p0.b
89; CHECK-NEXT:    add z0.s, p0/m, z0.s, z2.s
90; CHECK-NEXT:    add z1.s, p1/m, z1.s, z2.s
91; CHECK-NEXT:    ret
92  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
93  %result = add <vscale x 8 x i32> %a, %extend
94  ret <vscale x 8 x i32> %result
95}
96
97define <vscale x 16 x i32> @zext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
98; CHECK-LABEL: zext.add.16xi32:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    punpkhi p1.h, p0.b
101; CHECK-NEXT:    mov z4.s, #1 // =0x1
102; CHECK-NEXT:    punpklo p0.h, p0.b
103; CHECK-NEXT:    punpkhi p2.h, p1.b
104; CHECK-NEXT:    punpklo p1.h, p1.b
105; CHECK-NEXT:    punpklo p3.h, p0.b
106; CHECK-NEXT:    add z3.s, p2/m, z3.s, z4.s
107; CHECK-NEXT:    punpkhi p0.h, p0.b
108; CHECK-NEXT:    add z2.s, p1/m, z2.s, z4.s
109; CHECK-NEXT:    add z0.s, p3/m, z0.s, z4.s
110; CHECK-NEXT:    add z1.s, p0/m, z1.s, z4.s
111; CHECK-NEXT:    ret
112  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
113  %result = add <vscale x 16 x i32> %a, %extend
114  ret <vscale x 16 x i32> %result
115}
116
117define <vscale x 8 x i8> @zext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
118; CHECK-LABEL: zext.sub.8xi8:
119; CHECK:       // %bb.0:
120; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
121; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
122; CHECK-NEXT:    ret
123  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
124  %result = sub <vscale x 8 x i8> %a, %extend
125  ret <vscale x 8 x i8> %result
126}
127
128define <vscale x 4 x i16> @zext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
129; CHECK-LABEL: zext.sub.4xi16:
130; CHECK:       // %bb.0:
131; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
132; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
133; CHECK-NEXT:    ret
134  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
135  %result = sub <vscale x 4 x i16> %a, %extend
136  ret <vscale x 4 x i16> %result
137}
138
139define <vscale x 2 x i32> @zext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
140; CHECK-LABEL: zext.sub.2xi32:
141; CHECK:       // %bb.0:
142; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
143; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
144; CHECK-NEXT:    ret
145  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
146  %result = sub <vscale x 2 x i32> %a, %extend
147  ret <vscale x 2 x i32> %result
148}
149
150define <vscale x 16 x i8> @zext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
151; CHECK-LABEL: zext.sub.16xi8:
152; CHECK:       // %bb.0:
153; CHECK-NEXT:    mov z1.b, #-1 // =0xffffffffffffffff
154; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
155; CHECK-NEXT:    ret
156  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
157  %result = sub <vscale x 16 x i8> %a, %extend
158  ret <vscale x 16 x i8> %result
159}
160
161define <vscale x 8 x i16> @zext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
162; CHECK-LABEL: zext.sub.8xi16:
163; CHECK:       // %bb.0:
164; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
165; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
166; CHECK-NEXT:    ret
167  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
168  %result = sub <vscale x 8 x i16> %a, %extend
169  ret <vscale x 8 x i16> %result
170}
171
172define <vscale x 4 x i32> @zext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
173; CHECK-LABEL: zext.sub.4xi32:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
176; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
177; CHECK-NEXT:    ret
178  %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
179  %result = sub <vscale x 4 x i32> %a, %extend
180  ret <vscale x 4 x i32> %result
181}
182
183define <vscale x 2 x i64> @zext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
184; CHECK-LABEL: zext.sub.2xi64:
185; CHECK:       // %bb.0:
186; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
187; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
188; CHECK-NEXT:    ret
189  %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
190  %result = sub <vscale x 2 x i64> %a, %extend
191  ret <vscale x 2 x i64> %result
192}
193
194define <vscale x 8 x i32> @zext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
195; CHECK-LABEL: zext.sub.8xi32:
196; CHECK:       // %bb.0:
197; CHECK-NEXT:    mov z2.s, #-1 // =0xffffffffffffffff
198; CHECK-NEXT:    punpklo p1.h, p0.b
199; CHECK-NEXT:    punpkhi p0.h, p0.b
200; CHECK-NEXT:    add z0.s, p1/m, z0.s, z2.s
201; CHECK-NEXT:    add z1.s, p0/m, z1.s, z2.s
202; CHECK-NEXT:    ret
203  %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
204  %result = sub <vscale x 8 x i32> %a, %extend
205  ret <vscale x 8 x i32> %result
206}
207
208define <vscale x 16 x i32> @zext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
209; CHECK-LABEL: zext.sub.16xi32:
210; CHECK:       // %bb.0:
211; CHECK-NEXT:    punpklo p1.h, p0.b
212; CHECK-NEXT:    mov z4.s, #-1 // =0xffffffffffffffff
213; CHECK-NEXT:    punpkhi p0.h, p0.b
214; CHECK-NEXT:    punpklo p2.h, p1.b
215; CHECK-NEXT:    punpkhi p1.h, p1.b
216; CHECK-NEXT:    punpklo p3.h, p0.b
217; CHECK-NEXT:    add z0.s, p2/m, z0.s, z4.s
218; CHECK-NEXT:    punpkhi p0.h, p0.b
219; CHECK-NEXT:    add z1.s, p1/m, z1.s, z4.s
220; CHECK-NEXT:    add z2.s, p3/m, z2.s, z4.s
221; CHECK-NEXT:    add z3.s, p0/m, z3.s, z4.s
222; CHECK-NEXT:    ret
223  %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
224  %result = sub <vscale x 16 x i32> %a, %extend
225  ret <vscale x 16 x i32> %result
226}
227
228define <vscale x 8 x i8> @sext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
229; CHECK-LABEL: sext.add.8xi8:
230; CHECK:       // %bb.0:
231; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
232; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
233; CHECK-NEXT:    ret
234  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
235  %result = add <vscale x 8 x i8> %a, %extend
236  ret <vscale x 8 x i8> %result
237}
238
239define <vscale x 4 x i16> @sext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
240; CHECK-LABEL: sext.add.4xi16:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
243; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
244; CHECK-NEXT:    ret
245  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
246  %result = add <vscale x 4 x i16> %a, %extend
247  ret <vscale x 4 x i16> %result
248}
249
250define <vscale x 2 x i32> @sext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
251; CHECK-LABEL: sext.add.2xi32:
252; CHECK:       // %bb.0:
253; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
254; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
255; CHECK-NEXT:    ret
256  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
257  %result = add <vscale x 2 x i32> %a, %extend
258  ret <vscale x 2 x i32> %result
259}
260
261define <vscale x 16 x i8> @sext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
262; CHECK-LABEL: sext.add.16xi8:
263; CHECK:       // %bb.0:
264; CHECK-NEXT:    mov z1.b, #-1 // =0xffffffffffffffff
265; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
266; CHECK-NEXT:    ret
267  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
268  %result = add <vscale x 16 x i8> %a, %extend
269  ret <vscale x 16 x i8> %result
270}
271
272define <vscale x 8 x i16> @sext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
273; CHECK-LABEL: sext.add.8xi16:
274; CHECK:       // %bb.0:
275; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
276; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
277; CHECK-NEXT:    ret
278  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
279  %result = add <vscale x 8 x i16> %a, %extend
280  ret <vscale x 8 x i16> %result
281}
282
283define <vscale x 4 x i32> @sext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
284; CHECK-LABEL: sext.add.4xi32:
285; CHECK:       // %bb.0:
286; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
287; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
288; CHECK-NEXT:    ret
289  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
290  %result = add <vscale x 4 x i32> %a, %extend
291  ret <vscale x 4 x i32> %result
292}
293
294define <vscale x 2 x i64> @sext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
295; CHECK-LABEL: sext.add.2xi64:
296; CHECK:       // %bb.0:
297; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
298; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
299; CHECK-NEXT:    ret
300  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
301  %result = add <vscale x 2 x i64> %a, %extend
302  ret <vscale x 2 x i64> %result
303}
304
305define <vscale x 8 x i32> @sext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
306; CHECK-LABEL: sext.add.8xi32:
307; CHECK:       // %bb.0:
308; CHECK-NEXT:    mov z2.s, #-1 // =0xffffffffffffffff
309; CHECK-NEXT:    punpkhi p1.h, p0.b
310; CHECK-NEXT:    punpklo p0.h, p0.b
311; CHECK-NEXT:    add z0.s, p0/m, z0.s, z2.s
312; CHECK-NEXT:    add z1.s, p1/m, z1.s, z2.s
313; CHECK-NEXT:    ret
314  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
315  %result = add <vscale x 8 x i32> %a, %extend
316  ret <vscale x 8 x i32> %result
317}
318
319define <vscale x 16 x i32> @sext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
320; CHECK-LABEL: sext.add.16xi32:
321; CHECK:       // %bb.0:
322; CHECK-NEXT:    punpkhi p1.h, p0.b
323; CHECK-NEXT:    mov z4.s, #-1 // =0xffffffffffffffff
324; CHECK-NEXT:    punpklo p0.h, p0.b
325; CHECK-NEXT:    punpkhi p2.h, p1.b
326; CHECK-NEXT:    punpklo p1.h, p1.b
327; CHECK-NEXT:    punpklo p3.h, p0.b
328; CHECK-NEXT:    add z3.s, p2/m, z3.s, z4.s
329; CHECK-NEXT:    punpkhi p0.h, p0.b
330; CHECK-NEXT:    add z2.s, p1/m, z2.s, z4.s
331; CHECK-NEXT:    add z0.s, p3/m, z0.s, z4.s
332; CHECK-NEXT:    add z1.s, p0/m, z1.s, z4.s
333; CHECK-NEXT:    ret
334  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
335  %result = add <vscale x 16 x i32> %a, %extend
336  ret <vscale x 16 x i32> %result
337}
338
339define <vscale x 8 x i8> @sext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {
340; CHECK-LABEL: sext.sub.8xi8:
341; CHECK:       // %bb.0:
342; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
343; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
344; CHECK-NEXT:    ret
345  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
346  %result = sub <vscale x 8 x i8> %a, %extend
347  ret <vscale x 8 x i8> %result
348}
349
350define <vscale x 4 x i16> @sext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {
351; CHECK-LABEL: sext.sub.4xi16:
352; CHECK:       // %bb.0:
353; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
354; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
355; CHECK-NEXT:    ret
356  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
357  %result = sub <vscale x 4 x i16> %a, %extend
358  ret <vscale x 4 x i16> %result
359}
360
361define <vscale x 2 x i32> @sext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {
362; CHECK-LABEL: sext.sub.2xi32:
363; CHECK:       // %bb.0:
364; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
365; CHECK-NEXT:    sub z0.d, p0/m, z0.d, z1.d
366; CHECK-NEXT:    ret
367  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
368  %result = sub <vscale x 2 x i32> %a, %extend
369  ret <vscale x 2 x i32> %result
370}
371
372define <vscale x 16 x i8> @sext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {
373; CHECK-LABEL: sext.sub.16xi8:
374; CHECK:       // %bb.0:
375; CHECK-NEXT:    mov z1.b, #-1 // =0xffffffffffffffff
376; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
377; CHECK-NEXT:    ret
378  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
379  %result = sub <vscale x 16 x i8> %a, %extend
380  ret <vscale x 16 x i8> %result
381}
382
383define <vscale x 8 x i16> @sext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {
384; CHECK-LABEL: sext.sub.8xi16:
385; CHECK:       // %bb.0:
386; CHECK-NEXT:    mov z1.h, #-1 // =0xffffffffffffffff
387; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
388; CHECK-NEXT:    ret
389  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
390  %result = sub <vscale x 8 x i16> %a, %extend
391  ret <vscale x 8 x i16> %result
392}
393
394define <vscale x 4 x i32> @sext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {
395; CHECK-LABEL: sext.sub.4xi32:
396; CHECK:       // %bb.0:
397; CHECK-NEXT:    mov z1.s, #-1 // =0xffffffffffffffff
398; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
399; CHECK-NEXT:    ret
400  %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
401  %result = sub <vscale x 4 x i32> %a, %extend
402  ret <vscale x 4 x i32> %result
403}
404
405define <vscale x 2 x i64> @sext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {
406; CHECK-LABEL: sext.sub.2xi64:
407; CHECK:       // %bb.0:
408; CHECK-NEXT:    mov z1.d, #-1 // =0xffffffffffffffff
409; CHECK-NEXT:    sub z0.d, p0/m, z0.d, z1.d
410; CHECK-NEXT:    ret
411  %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
412  %result = sub <vscale x 2 x i64> %a, %extend
413  ret <vscale x 2 x i64> %result
414}
415
416define <vscale x 8 x i32> @sext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {
417; CHECK-LABEL: sext.sub.8xi32:
418; CHECK:       // %bb.0:
419; CHECK-NEXT:    mov z2.s, #-1 // =0xffffffffffffffff
420; CHECK-NEXT:    punpkhi p1.h, p0.b
421; CHECK-NEXT:    punpklo p0.h, p0.b
422; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z2.s
423; CHECK-NEXT:    sub z1.s, p1/m, z1.s, z2.s
424; CHECK-NEXT:    ret
425  %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
426  %result = sub <vscale x 8 x i32> %a, %extend
427  ret <vscale x 8 x i32> %result
428}
429
430define <vscale x 16 x i32> @sext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {
431; CHECK-LABEL: sext.sub.16xi32:
432; CHECK:       // %bb.0:
433; CHECK-NEXT:    punpkhi p1.h, p0.b
434; CHECK-NEXT:    mov z4.s, #-1 // =0xffffffffffffffff
435; CHECK-NEXT:    punpklo p0.h, p0.b
436; CHECK-NEXT:    punpkhi p2.h, p1.b
437; CHECK-NEXT:    punpklo p1.h, p1.b
438; CHECK-NEXT:    punpklo p3.h, p0.b
439; CHECK-NEXT:    sub z3.s, p2/m, z3.s, z4.s
440; CHECK-NEXT:    punpkhi p0.h, p0.b
441; CHECK-NEXT:    sub z2.s, p1/m, z2.s, z4.s
442; CHECK-NEXT:    sub z0.s, p3/m, z0.s, z4.s
443; CHECK-NEXT:    sub z1.s, p0/m, z1.s, z4.s
444; CHECK-NEXT:    ret
445  %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
446  %result = sub <vscale x 16 x i32> %a, %extend
447  ret <vscale x 16 x i32> %result
448}
449
450attributes #0 = { "target-features"="+sve" }
451