xref: /llvm-project/llvm/test/CodeGen/AArch64/pr72777.ll (revision a8450619358c3de23b72aef7c1fd932bca112257)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3
4define i64 @f(i64 %0, i64 %1) {
5; CHECK-LABEL: f:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    orr x9, x1, #0x1
8; CHECK-NEXT:    add x10, x0, x0
9; CHECK-NEXT:    mov x8, #-9223372036854775808 // =0x8000000000000000
10; CHECK-NEXT:    add x9, x9, x10
11; CHECK-NEXT:    lsl x10, x9, #1
12; CHECK-NEXT:    cmp x9, #0
13; CHECK-NEXT:    cinv x8, x8, ge
14; CHECK-NEXT:    cmp x9, x10, asr #1
15; CHECK-NEXT:    csel x0, x8, x10, ne
16; CHECK-NEXT:    ret
17  %3 = or i64 1, %1
18  %4 = add i64 %3, %0
19  %5 = add nsw i64 %4, %0
20  %6 = call i64 @llvm.sshl.sat.i64(i64 %5, i64 1)
21  ret i64 %6
22}
23
24declare i64 @llvm.sshl.sat.i64(i64, i64)
25