1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4;; This used to crash mid-legalization because we'd no longer have BUILD_VECTOR, 5;; but an CONCAT_VECTOR, and we didn't anticipate that. 6 7target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 8 9define linkonce_odr void @_ZN1y2beEPiRK1vPmPS1_(<8 x i8> %0, ptr %agg.tmp.i) { 10; CHECK-LABEL: _ZN1y2beEPiRK1vPmPS1_: 11; CHECK: // %bb.0: // %entry 12; CHECK-NEXT: sub sp, sp, #16 13; CHECK-NEXT: .cfi_def_cfa_offset 16 14; CHECK-NEXT: mov x8, sp 15; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 16; CHECK-NEXT: movi v1.2d, #0000000000000000 17; CHECK-NEXT: orr x9, x8, #0xf 18; CHECK-NEXT: orr x10, x8, #0xe 19; CHECK-NEXT: st1 { v0.b }[0], [x8] 20; CHECK-NEXT: st1 { v0.b }[15], [x9] 21; CHECK-NEXT: orr x9, x8, #0xc 22; CHECK-NEXT: st1 { v0.b }[12], [x9] 23; CHECK-NEXT: orr x9, x8, #0x8 24; CHECK-NEXT: st1 { v0.b }[8], [x9] 25; CHECK-NEXT: orr x9, x8, #0x7 26; CHECK-NEXT: st1 { v0.b }[7], [x9] 27; CHECK-NEXT: orr x9, x8, #0x6 28; CHECK-NEXT: st1 { v0.b }[6], [x9] 29; CHECK-NEXT: orr x9, x8, #0x4 30; CHECK-NEXT: st1 { v0.b }[4], [x9] 31; CHECK-NEXT: orr x9, x8, #0x3 32; CHECK-NEXT: st1 { v0.b }[3], [x9] 33; CHECK-NEXT: orr x9, x8, #0x2 34; CHECK-NEXT: st1 { v0.b }[14], [x10] 35; CHECK-NEXT: mov w10, #13 // =0xd 36; CHECK-NEXT: st1 { v0.b }[2], [x9] 37; CHECK-NEXT: orr x9, x8, #0x1 38; CHECK-NEXT: st1 { v0.b }[1], [x9] 39; CHECK-NEXT: orr x9, x8, x10 40; CHECK-NEXT: mov w10, #11 // =0xb 41; CHECK-NEXT: st1 { v0.b }[13], [x9] 42; CHECK-NEXT: orr x9, x8, x10 43; CHECK-NEXT: mov w10, #10 // =0xa 44; CHECK-NEXT: st1 { v0.b }[11], [x9] 45; CHECK-NEXT: orr x9, x8, x10 46; CHECK-NEXT: mov w10, #9 // =0x9 47; CHECK-NEXT: st1 { v0.b }[10], [x9] 48; CHECK-NEXT: orr x9, x8, x10 49; CHECK-NEXT: st1 { v0.b }[9], [x9] 50; CHECK-NEXT: mov w9, #5 // =0x5 51; CHECK-NEXT: orr x8, x8, x9 52; CHECK-NEXT: st1 { v0.b }[5], [x8] 53; CHECK-NEXT: ldr q0, [sp] 54; CHECK-NEXT: stp q0, q1, [x0] 55; CHECK-NEXT: add sp, sp, #16 56; CHECK-NEXT: ret 57entry: 58 %ref.tmp6.sroa.0.0.vecblend.i = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <24 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 59 %ref.tmp6.sroa.0.20.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.0.vecblend.i, <24 x i8> zeroinitializer, <24 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 45, i32 46, i32 47> 60 %ref.tmp.sroa.0.0.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.20.vecblend.i, <24 x i8> zeroinitializer, <28 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef> 61 %n.sroa.0.0.vecblend.i.i = shufflevector <28 x i8> %ref.tmp.sroa.0.0.vecblend.i, <28 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 undef, i32 undef, i32 undef, i32 undef> 62 store <32 x i8> %n.sroa.0.0.vecblend.i.i, ptr %agg.tmp.i, align 4 63 ret void 64} 65