1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-- -aarch64-enable-sink-fold=true | FileCheck %s 3 4declare float @llvm.pow.f32(float, float) 5declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) 6 7declare double @llvm.pow.f64(double, double) 8declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) 9 10define float @pow_f32_one_fourth_fmf(float %x) nounwind { 11; CHECK-LABEL: pow_f32_one_fourth_fmf: 12; CHECK: // %bb.0: 13; CHECK-NEXT: fsqrt s0, s0 14; CHECK-NEXT: fsqrt s0, s0 15; CHECK-NEXT: ret 16 %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01) 17 ret float %r 18} 19 20define double @pow_f64_one_fourth_fmf(double %x) nounwind { 21; CHECK-LABEL: pow_f64_one_fourth_fmf: 22; CHECK: // %bb.0: 23; CHECK-NEXT: fsqrt d0, d0 24; CHECK-NEXT: fsqrt d0, d0 25; CHECK-NEXT: ret 26 %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01) 27 ret double %r 28} 29 30define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind { 31; CHECK-LABEL: pow_v4f32_one_fourth_fmf: 32; CHECK: // %bb.0: 33; CHECK-NEXT: fsqrt v0.4s, v0.4s 34; CHECK-NEXT: fsqrt v0.4s, v0.4s 35; CHECK-NEXT: ret 36 %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>) 37 ret <4 x float> %r 38} 39 40define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind { 41; CHECK-LABEL: pow_v2f64_one_fourth_fmf: 42; CHECK: // %bb.0: 43; CHECK-NEXT: fsqrt v0.2d, v0.2d 44; CHECK-NEXT: fsqrt v0.2d, v0.2d 45; CHECK-NEXT: ret 46 %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>) 47 ret <2 x double> %r 48} 49 50define float @pow_f32_one_fourth_not_enough_fmf(float %x) nounwind { 51; CHECK-LABEL: pow_f32_one_fourth_not_enough_fmf: 52; CHECK: // %bb.0: 53; CHECK-NEXT: fmov s1, #0.25000000 54; CHECK-NEXT: b powf 55 %r = call afn ninf float @llvm.pow.f32(float %x, float 2.5e-01) 56 ret float %r 57} 58 59define double @pow_f64_one_fourth_not_enough_fmf(double %x) nounwind { 60; CHECK-LABEL: pow_f64_one_fourth_not_enough_fmf: 61; CHECK: // %bb.0: 62; CHECK-NEXT: fmov d1, #0.25000000 63; CHECK-NEXT: b pow 64 %r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01) 65 ret double %r 66} 67 68define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind { 69; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf: 70; CHECK: // %bb.0: 71; CHECK-NEXT: sub sp, sp, #48 72; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill 73; CHECK-NEXT: mov s0, v0.s[1] 74; CHECK-NEXT: fmov s1, #0.25000000 75; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill 76; CHECK-NEXT: bl powf 77; CHECK-NEXT: fmov s1, #0.25000000 78; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 79; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 80; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload 81; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 82; CHECK-NEXT: bl powf 83; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 84; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 85; CHECK-NEXT: mov v0.s[1], v1.s[0] 86; CHECK-NEXT: fmov s1, #0.25000000 87; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 88; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload 89; CHECK-NEXT: mov s0, v0.s[2] 90; CHECK-NEXT: bl powf 91; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 92; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 93; CHECK-NEXT: mov v1.s[2], v0.s[0] 94; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload 95; CHECK-NEXT: mov s0, v0.s[3] 96; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill 97; CHECK-NEXT: fmov s1, #0.25000000 98; CHECK-NEXT: bl powf 99; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 100; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 101; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload 102; CHECK-NEXT: mov v1.s[3], v0.s[0] 103; CHECK-NEXT: mov v0.16b, v1.16b 104; CHECK-NEXT: add sp, sp, #48 105; CHECK-NEXT: ret 106 %r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>) 107 ret <4 x float> %r 108} 109 110define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind { 111; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf: 112; CHECK: // %bb.0: 113; CHECK-NEXT: sub sp, sp, #48 114; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill 115; CHECK-NEXT: mov d0, v0.d[1] 116; CHECK-NEXT: fmov d1, #0.25000000 117; CHECK-NEXT: str x30, [sp, #32] // 8-byte Folded Spill 118; CHECK-NEXT: bl pow 119; CHECK-NEXT: fmov d1, #0.25000000 120; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 121; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill 122; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload 123; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 124; CHECK-NEXT: bl pow 125; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload 126; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 127; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload 128; CHECK-NEXT: mov v0.d[1], v1.d[0] 129; CHECK-NEXT: add sp, sp, #48 130; CHECK-NEXT: ret 131 %r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>) 132 ret <2 x double> %r 133} 134 135