1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -run-pass=aarch64-mi-peephole-opt -mtriple=aarch64-unknown-linux -verify-machineinstrs -o - %s | FileCheck %s 3--- | 4 define void @insert_vec_v6i64_uaddlv_from_v4i32(ptr %0) { 5 entry: 6 ret void 7 } 8 9 define void @insert_vec_v2i32_uaddlv_from_v8i16(ptr %0) { 10 entry: 11 ret void 12 } 13 14 define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) { 15 entry: 16 ret void 17 } 18 19 define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) { 20 entry: 21 ret void 22 } 23 24 define void @insert_vec_v2i32_uaddlv_from_v8i16_nz_index(ptr %0) { 25 entry: 26 ret void 27 } 28 29 define void @insert_vec_from_gpr(i32 %v, ptr %p) { 30 entry: 31 ret void 32 } 33 34 define void @fadd(double %v, double %p) { 35 entry: 36 ret void 37 } 38 39 define void @asm(ptr %hist) { 40 entry: 41 ret void 42 } 43 44 attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) } 45 46... 47--- 48name: insert_vec_v6i64_uaddlv_from_v4i32 49registers: 50 - { id: 0, class: gpr64common, preferred-register: '' } 51 - { id: 1, class: fpr128, preferred-register: '' } 52 - { id: 2, class: fpr64, preferred-register: '' } 53 - { id: 3, class: fpr128, preferred-register: '' } 54 - { id: 4, class: fpr128, preferred-register: '' } 55 - { id: 5, class: gpr64, preferred-register: '' } 56 - { id: 6, class: fpr128, preferred-register: '' } 57 - { id: 7, class: fpr128, preferred-register: '' } 58 - { id: 8, class: fpr64, preferred-register: '' } 59 - { id: 9, class: fpr128, preferred-register: '' } 60 - { id: 10, class: fpr128, preferred-register: '' } 61 - { id: 11, class: fpr128, preferred-register: '' } 62 - { id: 12, class: fpr64, preferred-register: '' } 63 - { id: 13, class: fpr128, preferred-register: '' } 64 - { id: 14, class: fpr128, preferred-register: '' } 65 - { id: 15, class: fpr128, preferred-register: '' } 66 - { id: 16, class: gpr64all, preferred-register: '' } 67 - { id: 17, class: fpr64, preferred-register: '' } 68liveins: 69 - { reg: '$x0', virtual-reg: '%0' } 70body: | 71 bb.0.entry: 72 liveins: $x0 73 74 ; CHECK-LABEL: name: insert_vec_v6i64_uaddlv_from_v4i32 75 ; CHECK: liveins: $x0 76 ; CHECK-NEXT: {{ $}} 77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 78 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 79 ; CHECK-NEXT: [[UADDLVv4i32v:%[0-9]+]]:fpr64 = UADDLVv4i32v [[MOVIv2d_ns]] 80 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 81 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv4i32v]], %subreg.dsub 82 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[INSERT_SUBREG]].dsub 83 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[MOVIv2d_ns]], 0, [[INSERT_SUBREG]], 0 84 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0 85 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 86 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub 87 ; CHECK-NEXT: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 killed [[INSvi64lane]], implicit $fpcr 88 ; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 killed [[UCVTFv2f64_]], implicit $fpcr 89 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF 90 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], killed [[FCVTNv2i32_]], %subreg.dsub 91 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub 92 ; CHECK-NEXT: STRDui killed [[COPY2]], [[COPY]], 2 :: (store (s64) into %ir.0 + 16) 93 ; CHECK-NEXT: STRQui killed [[INSERT_SUBREG2]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8) 94 ; CHECK-NEXT: RET_ReallyLR 95 %0:gpr64common = COPY $x0 96 %1:fpr128 = MOVIv2d_ns 0 97 %2:fpr64 = UADDLVv4i32v %1 98 %4:fpr128 = IMPLICIT_DEF 99 %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.dsub 100 %5:gpr64 = COPY %3.dsub 101 %7:fpr128 = INSvi64gpr %1, 0, killed %5 102 %8:fpr64 = MOVID 0 103 %10:fpr128 = IMPLICIT_DEF 104 %9:fpr128 = INSERT_SUBREG %10, killed %8, %subreg.dsub 105 %11:fpr128 = nofpexcept UCVTFv2f64 killed %7, implicit $fpcr 106 %12:fpr64 = nofpexcept FCVTNv2i32 killed %11, implicit $fpcr 107 %14:fpr128 = IMPLICIT_DEF 108 %13:fpr128 = INSERT_SUBREG %14, killed %12, %subreg.dsub 109 %15:fpr128 = INSvi64lane %13, 1, killed %9, 0 110 %17:fpr64 = COPY %1.dsub 111 STRDui killed %17, %0, 2 :: (store (s64) into %ir.0 + 16) 112 STRQui killed %15, %0, 0 :: (store (s128) into %ir.0, align 8) 113 RET_ReallyLR 114 115... 116--- 117name: insert_vec_v2i32_uaddlv_from_v8i16 118registers: 119 - { id: 0, class: gpr64common, preferred-register: '' } 120 - { id: 1, class: fpr128, preferred-register: '' } 121 - { id: 2, class: fpr32, preferred-register: '' } 122 - { id: 3, class: fpr128, preferred-register: '' } 123 - { id: 4, class: fpr128, preferred-register: '' } 124 - { id: 5, class: gpr32, preferred-register: '' } 125 - { id: 6, class: fpr64, preferred-register: '' } 126 - { id: 7, class: fpr128, preferred-register: '' } 127 - { id: 8, class: fpr128, preferred-register: '' } 128 - { id: 9, class: fpr128, preferred-register: '' } 129 - { id: 10, class: fpr64, preferred-register: '' } 130 - { id: 11, class: fpr64, preferred-register: '' } 131liveins: 132 - { reg: '$x0', virtual-reg: '%0' } 133body: | 134 bb.0.entry: 135 liveins: $x0 136 137 ; CHECK-LABEL: name: insert_vec_v2i32_uaddlv_from_v8i16 138 ; CHECK: liveins: $x0 139 ; CHECK-NEXT: {{ $}} 140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 141 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 142 ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v killed [[MOVIv2d_ns]] 143 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 144 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub 145 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub 146 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0 147 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 148 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub 149 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0 150 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub 151 ; CHECK-NEXT: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 killed [[COPY2]], implicit $fpcr 152 ; CHECK-NEXT: STRDui killed [[UCVTFv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.0) 153 ; CHECK-NEXT: RET_ReallyLR 154 %0:gpr64common = COPY $x0 155 %1:fpr128 = MOVIv2d_ns 0 156 %2:fpr32 = UADDLVv8i16v killed %1 157 %4:fpr128 = IMPLICIT_DEF 158 %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub 159 %5:gpr32 = COPY %3.ssub 160 %6:fpr64 = MOVID 0 161 %8:fpr128 = IMPLICIT_DEF 162 %7:fpr128 = INSERT_SUBREG %8, killed %6, %subreg.dsub 163 %9:fpr128 = INSvi32gpr %7, 0, killed %5 164 %10:fpr64 = COPY %9.dsub 165 %11:fpr64 = nofpexcept UCVTFv2f32 killed %10, implicit $fpcr 166 STRDui killed %11, %0, 0 :: (store (s64) into %ir.0) 167 RET_ReallyLR 168 169... 170--- 171name: insert_vec_v8i16_uaddlv_from_v8i16 172registers: 173 - { id: 0, class: gpr64common, preferred-register: '' } 174 - { id: 1, class: fpr128, preferred-register: '' } 175 - { id: 2, class: fpr32, preferred-register: '' } 176 - { id: 3, class: fpr128, preferred-register: '' } 177 - { id: 4, class: fpr128, preferred-register: '' } 178 - { id: 5, class: gpr32, preferred-register: '' } 179 - { id: 6, class: fpr64, preferred-register: '' } 180 - { id: 7, class: fpr128, preferred-register: '' } 181 - { id: 8, class: fpr128, preferred-register: '' } 182 - { id: 9, class: fpr128, preferred-register: '' } 183 - { id: 10, class: fpr64, preferred-register: '' } 184 - { id: 11, class: fpr128, preferred-register: '' } 185 - { id: 12, class: fpr128, preferred-register: '' } 186 - { id: 13, class: gpr32, preferred-register: '' } 187liveins: 188 - { reg: '$x0', virtual-reg: '%0' } 189body: | 190 bb.0.entry: 191 liveins: $x0 192 193 ; CHECK-LABEL: name: insert_vec_v8i16_uaddlv_from_v8i16 194 ; CHECK: liveins: $x0 195 ; CHECK-NEXT: {{ $}} 196 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 197 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 198 ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v killed [[MOVIv2d_ns]] 199 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 200 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub 201 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub 202 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0 203 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 204 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub 205 ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0 206 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane]].dsub 207 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift killed [[COPY2]], 0 208 ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[USHLLv4i16_shift]], implicit $fpcr 209 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr 210 ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 7 :: (store (s32) into %ir.0 + 28) 211 ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 6 :: (store (s32) into %ir.0 + 24, align 8) 212 ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 5 :: (store (s32) into %ir.0 + 20) 213 ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 4 :: (store (s32) into %ir.0 + 16, align 8) 214 ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8) 215 ; CHECK-NEXT: RET_ReallyLR 216 %0:gpr64common = COPY $x0 217 %1:fpr128 = MOVIv2d_ns 0 218 %2:fpr32 = UADDLVv8i16v killed %1 219 %4:fpr128 = IMPLICIT_DEF 220 %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub 221 %5:gpr32 = COPY %3.ssub 222 %6:fpr64 = MOVID 0 223 %8:fpr128 = IMPLICIT_DEF 224 %7:fpr128 = INSERT_SUBREG %8, killed %6, %subreg.dsub 225 %9:fpr128 = INSvi16gpr %7, 0, killed %5 226 %10:fpr64 = COPY %9.dsub 227 %11:fpr128 = USHLLv4i16_shift killed %10, 0 228 %12:fpr128 = nofpexcept UCVTFv4f32 killed %11, implicit $fpcr 229 %13:gpr32 = COPY $wzr 230 STRWui %13, %0, 7 :: (store (s32) into %ir.0 + 28) 231 STRWui %13, %0, 6 :: (store (s32) into %ir.0 + 24, align 8) 232 STRWui %13, %0, 5 :: (store (s32) into %ir.0 + 20) 233 STRWui %13, %0, 4 :: (store (s32) into %ir.0 + 16, align 8) 234 STRQui killed %12, %0, 0 :: (store (s128) into %ir.0, align 8) 235 RET_ReallyLR 236 237... 238--- 239name: insert_vec_v16i8_uaddlv_from_v4i32 240registers: 241 - { id: 0, class: gpr64common, preferred-register: '' } 242 - { id: 1, class: fpr128, preferred-register: '' } 243 - { id: 2, class: fpr64, preferred-register: '' } 244 - { id: 3, class: fpr128, preferred-register: '' } 245 - { id: 4, class: fpr128, preferred-register: '' } 246 - { id: 5, class: gpr64all, preferred-register: '' } 247 - { id: 6, class: gpr32, preferred-register: '' } 248 - { id: 7, class: fpr64, preferred-register: '' } 249 - { id: 8, class: fpr128, preferred-register: '' } 250 - { id: 9, class: fpr128, preferred-register: '' } 251 - { id: 10, class: fpr128, preferred-register: '' } 252 - { id: 11, class: fpr64, preferred-register: '' } 253 - { id: 12, class: fpr64, preferred-register: '' } 254 - { id: 13, class: fpr64, preferred-register: '' } 255 - { id: 14, class: fpr64, preferred-register: '' } 256 - { id: 15, class: fpr128, preferred-register: '' } 257 - { id: 16, class: fpr128, preferred-register: '' } 258 - { id: 17, class: fpr128, preferred-register: '' } 259liveins: 260 - { reg: '$x0', virtual-reg: '%0' } 261body: | 262 bb.0.entry: 263 liveins: $x0 264 265 ; CHECK-LABEL: name: insert_vec_v16i8_uaddlv_from_v4i32 266 ; CHECK: liveins: $x0 267 ; CHECK-NEXT: {{ $}} 268 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 269 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 270 ; CHECK-NEXT: [[UADDLVv4i32v:%[0-9]+]]:fpr64 = UADDLVv4i32v [[MOVIv2d_ns]] 271 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 272 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv4i32v]], %subreg.dsub 273 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY [[INSERT_SUBREG]].dsub 274 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32 275 ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0 276 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 277 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub 278 ; CHECK-NEXT: [[INSvi8lane:%[0-9]+]]:fpr128 = INSvi8lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0 279 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi8lane]].dsub 280 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr64 = IMPLICIT_DEF 281 ; CHECK-NEXT: [[ZIP1v8i8_:%[0-9]+]]:fpr64 = ZIP1v8i8 killed [[COPY3]], killed [[DEF2]] 282 ; CHECK-NEXT: [[BICv4i16_:%[0-9]+]]:fpr64 = BICv4i16 [[ZIP1v8i8_]], 255, 8 283 ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift killed [[BICv4i16_]], 0 284 ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[USHLLv4i16_shift]], implicit $fpcr 285 ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 3 :: (store (s128) into %ir.0 + 48, align 8) 286 ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 2 :: (store (s128) into %ir.0 + 32, align 8) 287 ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 1 :: (store (s128) into %ir.0 + 16, align 8) 288 ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8) 289 ; CHECK-NEXT: RET_ReallyLR 290 %0:gpr64common = COPY $x0 291 %1:fpr128 = MOVIv2d_ns 0 292 %2:fpr64 = UADDLVv4i32v %1 293 %4:fpr128 = IMPLICIT_DEF 294 %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.dsub 295 %5:gpr64all = COPY %3.dsub 296 %6:gpr32 = COPY %5.sub_32 297 %7:fpr64 = MOVID 0 298 %9:fpr128 = IMPLICIT_DEF 299 %8:fpr128 = INSERT_SUBREG %9, killed %7, %subreg.dsub 300 %10:fpr128 = INSvi8gpr %8, 0, killed %6 301 %11:fpr64 = COPY %10.dsub 302 %13:fpr64 = IMPLICIT_DEF 303 %12:fpr64 = ZIP1v8i8 killed %11, killed %13 304 %14:fpr64 = BICv4i16 %12, 255, 8 305 %15:fpr128 = USHLLv4i16_shift killed %14, 0 306 %16:fpr128 = nofpexcept UCVTFv4f32 killed %15, implicit $fpcr 307 STRQui %1, %0, 3 :: (store (s128) into %ir.0 + 48, align 8) 308 STRQui %1, %0, 2 :: (store (s128) into %ir.0 + 32, align 8) 309 STRQui %1, %0, 1 :: (store (s128) into %ir.0 + 16, align 8) 310 STRQui killed %16, %0, 0 :: (store (s128) into %ir.0, align 8) 311 RET_ReallyLR 312 313... 314--- 315name: insert_vec_v2i32_uaddlv_from_v8i16_nz_index 316registers: 317 - { id: 0, class: gpr64common, preferred-register: '' } 318 - { id: 1, class: fpr128, preferred-register: '' } 319 - { id: 2, class: fpr32, preferred-register: '' } 320 - { id: 3, class: fpr128, preferred-register: '' } 321 - { id: 4, class: fpr128, preferred-register: '' } 322 - { id: 5, class: gpr32, preferred-register: '' } 323 - { id: 6, class: fpr128, preferred-register: '' } 324 - { id: 7, class: fpr128, preferred-register: '' } 325 - { id: 8, class: fpr128, preferred-register: '' } 326liveins: 327 - { reg: '$x0', virtual-reg: '%0' } 328body: | 329 bb.0.entry: 330 liveins: $x0 331 332 ; CHECK-LABEL: name: insert_vec_v2i32_uaddlv_from_v8i16_nz_index 333 ; CHECK: liveins: $x0 334 ; CHECK-NEXT: {{ $}} 335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 336 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 337 ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v [[MOVIv2d_ns]] 338 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 339 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub 340 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub 341 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[MOVIv2d_ns]], 2, [[INSERT_SUBREG]], 0 342 ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[INSvi32lane]], implicit $fpcr 343 ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8) 344 ; CHECK-NEXT: RET_ReallyLR 345 %0:gpr64common = COPY $x0 346 %1:fpr128 = MOVIv2d_ns 0 347 %2:fpr32 = UADDLVv8i16v %1 348 %4:fpr128 = IMPLICIT_DEF 349 %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub 350 %5:gpr32 = COPY %3.ssub 351 %7:fpr128 = INSvi32gpr %1, 2, killed %5 352 %8:fpr128 = nofpexcept UCVTFv4f32 killed %7, implicit $fpcr 353 STRQui killed %8, %0, 0 :: (store (s128) into %ir.0, align 8) 354 RET_ReallyLR 355 356... 357--- 358name: insert_vec_from_gpr 359registers: 360 - { id: 0, class: gpr32, preferred-register: '' } 361 - { id: 1, class: gpr64common, preferred-register: '' } 362 - { id: 2, class: gpr64, preferred-register: '' } 363 - { id: 3, class: gpr64all, preferred-register: '' } 364 - { id: 4, class: gpr64common, preferred-register: '' } 365 - { id: 5, class: gpr64common, preferred-register: '' } 366 - { id: 6, class: fpr128, preferred-register: '' } 367 - { id: 7, class: fpr128, preferred-register: '' } 368liveins: 369 - { reg: '$w0', virtual-reg: '%0' } 370 - { reg: '$x1', virtual-reg: '%1' } 371stack: 372 - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16, 373 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 374 local-offset: -16, debug-info-variable: '', debug-info-expression: '', 375 debug-info-location: '' } 376body: | 377 bb.0.entry: 378 liveins: $w0, $x1 379 380 ; CHECK-LABEL: name: insert_vec_from_gpr 381 ; CHECK: liveins: $w0, $x1 382 ; CHECK-NEXT: {{ $}} 383 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1 384 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0 385 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 386 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32 387 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0, 0 388 ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64common = BFMXri [[ADDXri]], killed [[INSERT_SUBREG]], 62, 1 389 ; CHECK-NEXT: STRWui [[COPY1]], killed [[BFMXri]], 0 :: (store (s32)) 390 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0) 391 ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[LDRQui]], 1, [[COPY1]] 392 ; CHECK-NEXT: STRQui killed [[INSvi32gpr]], [[COPY]], 0 :: (store (s128) into %ir.p, align 4) 393 ; CHECK-NEXT: RET_ReallyLR 394 %1:gpr64common = COPY $x1 395 %0:gpr32 = COPY $w0 396 %3:gpr64all = IMPLICIT_DEF 397 %2:gpr64 = INSERT_SUBREG %3, %0, %subreg.sub_32 398 %4:gpr64common = ADDXri %stack.0, 0, 0 399 %5:gpr64common = BFMXri %4, killed %2, 62, 1 400 STRWui %0, killed %5, 0 :: (store (s32)) 401 %6:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0) 402 %7:fpr128 = INSvi32gpr %6, 1, %0 403 STRQui killed %7, %1, 0 :: (store (s128) into %ir.p, align 4) 404 RET_ReallyLR 405 406... 407--- 408name: fadd 409alignment: 4 410tracksRegLiveness: true 411registers: 412 - { id: 0, class: fpr64, preferred-register: '' } 413 - { id: 1, class: fpr64, preferred-register: '' } 414 - { id: 2, class: fpr64, preferred-register: '' } 415 - { id: 3, class: fpr128, preferred-register: '' } 416 - { id: 4, class: fpr64, preferred-register: '' } 417 - { id: 5, class: fpr128, preferred-register: '' } 418 - { id: 6, class: fpr128, preferred-register: '' } 419 - { id: 7, class: fpr128, preferred-register: '' } 420 - { id: 8, class: fpr128, preferred-register: '' } 421 - { id: 9, class: fpr128, preferred-register: '' } 422liveins: 423 - { reg: '$d0', virtual-reg: '%0' } 424 - { reg: '$d1', virtual-reg: '%1' } 425body: | 426 bb.0.entry: 427 liveins: $d0, $d1 428 429 ; CHECK-LABEL: name: fadd 430 ; CHECK: liveins: $d0, $d1 431 ; CHECK-NEXT: {{ $}} 432 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 433 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 434 ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY1]], [[COPY]], implicit $fpcr 435 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 436 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub 437 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 438 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub 439 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 440 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[FADDDrr]], %subreg.dsub 441 ; CHECK-NEXT: $q0 = COPY [[INSERT_SUBREG1]] 442 ; CHECK-NEXT: RET_ReallyLR implicit $q0 443 %1:fpr64 = COPY $d1 444 %0:fpr64 = COPY $d0 445 %2:fpr64 = nofpexcept FADDDrr %0, %1, implicit $fpcr 446 %3:fpr128 = MOVIv2d_ns 0 447 %4:fpr64 = COPY %3.dsub 448 %6:fpr128 = IMPLICIT_DEF 449 %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub 450 %8:fpr128 = IMPLICIT_DEF 451 %7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub 452 %9:fpr128 = INSvi64lane %7, 1, killed %5, 0 453 $q0 = COPY %9 454 RET_ReallyLR implicit $q0 455 456... 457--- 458name: asm 459tracksRegLiveness: true 460registers: 461 - { id: 0, class: gpr64common, preferred-register: '' } 462 - { id: 1, class: fpr64, preferred-register: '' } 463 - { id: 2, class: gpr64all, preferred-register: '' } 464 - { id: 3, class: gpr64sp, preferred-register: '' } 465 - { id: 4, class: fpr128, preferred-register: '' } 466 - { id: 5, class: fpr64, preferred-register: '' } 467 - { id: 6, class: fpr128, preferred-register: '' } 468 - { id: 7, class: fpr128, preferred-register: '' } 469 - { id: 8, class: fpr128, preferred-register: '' } 470 - { id: 9, class: fpr128, preferred-register: '' } 471 - { id: 10, class: fpr128, preferred-register: '' } 472 - { id: 11, class: fpr64, preferred-register: '' } 473 - { id: 12, class: fpr64, preferred-register: '' } 474 - { id: 13, class: fpr128, preferred-register: '' } 475 - { id: 14, class: fpr128, preferred-register: '' } 476 - { id: 15, class: gpr32all, preferred-register: '' } 477 - { id: 16, class: fpr32, preferred-register: '' } 478liveins: 479 - { reg: '$x0', virtual-reg: '%0' } 480body: | 481 bb.0.entry: 482 liveins: $x0 483 484 ; CHECK-LABEL: name: asm 485 ; CHECK: liveins: $x0 486 ; CHECK-NEXT: {{ $}} 487 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 488 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 489 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]] 490 ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3735562 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]] 491 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 492 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub 493 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 494 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[COPY2]], %subreg.dsub 495 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF 496 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %1, %subreg.dsub 497 ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0 498 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr64 = IMPLICIT_DEF 499 ; CHECK-NEXT: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One killed [[INSvi64lane]], killed [[DEF3]] 500 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF 501 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], killed [[TBLv8i8One]], %subreg.dsub 502 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[INSERT_SUBREG2]].ssub 503 ; CHECK-NEXT: STRSui killed [[COPY3]], [[COPY]], 0 :: (store (s32) into %ir.hist) 504 ; CHECK-NEXT: RET_ReallyLR 505 %0:gpr64common = COPY $x0 506 %2:gpr64all = IMPLICIT_DEF 507 %3:gpr64sp = COPY %2 508 INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3735562 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3 509 %4:fpr128 = MOVIv2d_ns 0 510 %5:fpr64 = COPY %4.dsub 511 %7:fpr128 = IMPLICIT_DEF 512 %6:fpr128 = INSERT_SUBREG %7, killed %5, %subreg.dsub 513 %9:fpr128 = IMPLICIT_DEF 514 %8:fpr128 = INSERT_SUBREG %9, %1, %subreg.dsub 515 %10:fpr128 = INSvi64lane %8, 1, killed %6, 0 516 %12:fpr64 = IMPLICIT_DEF 517 %11:fpr64 = TBLv8i8One killed %10, killed %12 518 %14:fpr128 = IMPLICIT_DEF 519 %13:fpr128 = INSERT_SUBREG %14, killed %11, %subreg.dsub 520 %16:fpr32 = COPY %13.ssub 521 STRSui killed %16, %0, 0 :: (store (s32) into %ir.hist) 522 RET_ReallyLR 523 524... 525