1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -force-vector-interleave=1 -o - %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5target triple = "aarch64-none-unknown-elf" 6 7define <4 x i32> @partial_reduce_add_fixed(<4 x i32> %accumulator, <4 x i32> %0) #0 { 8; CHECK-LABEL: partial_reduce_add_fixed: 9; CHECK: // %bb.0: // %entry 10; CHECK-NEXT: add v0.4s, v0.4s, v1.4s 11; CHECK-NEXT: ret 12entry: 13 %partial.reduce = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v4i32.v4i32(<4 x i32> %accumulator, <4 x i32> %0) 14 ret <4 x i32> %partial.reduce 15} 16 17define <4 x i32> @partial_reduce_add_fixed_half(<4 x i32> %accumulator, <8 x i32> %0) #0 { 18; CHECK-LABEL: partial_reduce_add_fixed_half: 19; CHECK: // %bb.0: // %entry 20; CHECK-NEXT: add v0.4s, v0.4s, v1.4s 21; CHECK-NEXT: add v0.4s, v2.4s, v0.4s 22; CHECK-NEXT: ret 23entry: 24 %partial.reduce = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v4i32.v8i32(<4 x i32> %accumulator, <8 x i32> %0) 25 ret <4 x i32> %partial.reduce 26} 27 28define <vscale x 4 x i32> @partial_reduce_add(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) #0 { 29; CHECK-LABEL: partial_reduce_add: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: add z0.s, z0.s, z1.s 32; CHECK-NEXT: ret 33entry: 34 %partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) 35 ret <vscale x 4 x i32> %partial.reduce 36} 37 38define <vscale x 4 x i32> @partial_reduce_add_half(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) #0 { 39; CHECK-LABEL: partial_reduce_add_half: 40; CHECK: // %bb.0: // %entry 41; CHECK-NEXT: add z0.s, z0.s, z1.s 42; CHECK-NEXT: add z0.s, z2.s, z0.s 43; CHECK-NEXT: ret 44entry: 45 %partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) 46 ret <vscale x 4 x i32> %partial.reduce 47} 48 49define <vscale x 4 x i32> @partial_reduce_add_quart(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) #0 { 50; CHECK-LABEL: partial_reduce_add_quart: 51; CHECK: // %bb.0: // %entry 52; CHECK-NEXT: add z0.s, z0.s, z1.s 53; CHECK-NEXT: add z2.s, z2.s, z3.s 54; CHECK-NEXT: add z0.s, z4.s, z0.s 55; CHECK-NEXT: add z0.s, z2.s, z0.s 56; CHECK-NEXT: ret 57entry: 58 %partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) 59 ret <vscale x 4 x i32> %partial.reduce 60} 61 62define <vscale x 8 x i32> @partial_reduce_add_half_8(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) #0 { 63; CHECK-LABEL: partial_reduce_add_half_8: 64; CHECK: // %bb.0: // %entry 65; CHECK-NEXT: add z0.s, z0.s, z2.s 66; CHECK-NEXT: add z1.s, z1.s, z3.s 67; CHECK-NEXT: add z0.s, z4.s, z0.s 68; CHECK-NEXT: add z1.s, z5.s, z1.s 69; CHECK-NEXT: ret 70entry: 71 %partial.reduce = call <vscale x 8 x i32> @llvm.experimental.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) 72 ret <vscale x 8 x i32> %partial.reduce 73} 74 75declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 76declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32>, <vscale x 8 x i32>) 77declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32>, <vscale x 16 x i32>) 78declare <vscale x 8 x i32> @llvm.experimental.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32>, <vscale x 16 x i32>) 79 80declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>) 81declare i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32>) 82 83attributes #0 = { "target-features"="+sve2" } 84