1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -o - %s -mtriple=aarch64-- -aarch64-enable-sink-fold=true | FileCheck %s 3 4define void @and1(i32 %a, ptr nocapture %p) { 5; CHECK-LABEL: and1: 6; CHECK: // %bb.0: // %entry 7; CHECK-NEXT: and w8, w0, #0xfffffffd 8; CHECK-NEXT: strb w8, [x1] 9; CHECK-NEXT: ret 10entry: 11 %and = and i32 %a, 253 12 %conv = trunc i32 %and to i8 13 store i8 %conv, ptr %p, align 1 14 ret void 15} 16 17; (a & 0x3dfd) | 0xffffc000 18define i32 @and2(i32 %a) { 19; CHECK-LABEL: and2: 20; CHECK: // %bb.0: // %entry 21; CHECK-NEXT: and w8, w0, #0xfdfdfdfd 22; CHECK-NEXT: orr w0, w8, #0xffffc000 23; CHECK-NEXT: ret 24entry: 25 %and = and i32 %a, 15869 26 %or = or i32 %and, -16384 27 ret i32 %or 28} 29 30; (a & 0x19) | 0xffffffc0 31define i32 @and3(i32 %a) { 32; CHECK-LABEL: and3: 33; CHECK: // %bb.0: // %entry 34; CHECK-NEXT: and w8, w0, #0x99999999 35; CHECK-NEXT: orr w0, w8, #0xffffffc0 36; CHECK-NEXT: ret 37entry: 38 %and = and i32 %a, 25 39 %or = or i32 %and, -64 40 ret i32 %or 41} 42 43; (a & 0xc5600) | 0xfff1f1ff 44define i32 @and4(i32 %a) { 45; CHECK-LABEL: and4: 46; CHECK: // %bb.0: // %entry 47; CHECK-NEXT: mov w8, #61951 // =0xf1ff 48; CHECK-NEXT: and w9, w0, #0xfffc07ff 49; CHECK-NEXT: movk w8, #65521, lsl #16 50; CHECK-NEXT: orr w0, w9, w8 51; CHECK-NEXT: ret 52entry: 53 %and = and i32 %a, 787968 54 %or = or i32 %and, -921089 55 ret i32 %or 56} 57 58; Make sure we don't shrink or optimize an XOR's immediate operand if the 59; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into 60; a BIC. 61define i32 @xor1(i32 %a) { 62; CHECK-LABEL: xor1: 63; CHECK: // %bb.0: // %entry 64; CHECK-NEXT: mov w8, #56 // =0x38 65; CHECK-NEXT: bic w0, w8, w0, lsl #3 66; CHECK-NEXT: ret 67entry: 68 %shl = shl i32 %a, 3 69 %xor = and i32 %shl, 56 70 %and = xor i32 %xor, 56 71 ret i32 %and 72} 73 74; Check that, when (and %t1, 129) is transformed to (and %t0, 0), 75; (xor %arg, 129) doesn't get transformed to (xor %arg, 0). 76define i64 @PR33100(i64 %arg) { 77; CHECK-LABEL: PR33100: 78; CHECK: // %bb.0: // %entry 79; CHECK-NEXT: sub sp, sp, #16 80; CHECK-NEXT: .cfi_def_cfa_offset 16 81; CHECK-NEXT: mov w8, #129 // =0x81 82; CHECK-NEXT: mov w9, #8 // =0x8 83; CHECK-NEXT: eor x0, x0, x8 84; CHECK-NEXT: str x9, [sp, #8] 85; CHECK-NEXT: add sp, sp, #16 86; CHECK-NEXT: ret 87entry: 88 %alloca0 = alloca i64 89 store i64 8, ptr %alloca0, align 4 90 %t0 = load i64, ptr %alloca0, align 4 91 %t1 = shl i64 %arg, %t0 92 %and0 = and i64 %t1, 129 93 %xor0 = xor i64 %arg, 129 94 %t2 = add i64 %and0, %xor0 95 ret i64 %t2 96} 97