xref: /llvm-project/llvm/test/CodeGen/AArch64/nzcv-save.ll (revision 3d18c8cd265c0c0bf1d85226c4770a2dd0f86e8f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64 | FileCheck %s
3
4; DAG ends up with two uses for the flags from an ADCS node, which means they
5; must be saved for later.
6define void @f(ptr nocapture %a, ptr nocapture %b, ptr nocapture %cc, ptr nocapture %dd) nounwind uwtable noinline ssp {
7; CHECK-LABEL: f:
8; CHECK:       // %bb.0: // %entry
9; CHECK-NEXT:    ldp x8, x10, [x2]
10; CHECK-NEXT:    ldp x9, x11, [x3]
11; CHECK-NEXT:    ldp x13, x12, [x2, #16]
12; CHECK-NEXT:    adds x8, x8, x9
13; CHECK-NEXT:    ldp x14, x9, [x3, #16]
14; CHECK-NEXT:    adcs x10, x10, x11
15; CHECK-NEXT:    stp x8, x10, [x0]
16; CHECK-NEXT:    adcs x11, x13, x14
17; CHECK-NEXT:    adc x13, x12, x9
18; CHECK-NEXT:    orr x12, x12, #0x100
19; CHECK-NEXT:    adc x9, x12, x9
20; CHECK-NEXT:    stp x11, x13, [x0, #16]
21; CHECK-NEXT:    stp x11, x9, [x1, #16]
22; CHECK-NEXT:    stp x8, x10, [x1]
23; CHECK-NEXT:    ret
24entry:
25  %c = load i256, ptr %cc
26  %d = load i256, ptr %dd
27  %add = add nsw i256 %c, %d
28  store i256 %add, ptr %a, align 8
29  %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
30  %add6 = add nsw i256 %or, %d
31  store i256 %add6, ptr %b, align 8
32  ret void
33}
34