xref: /llvm-project/llvm/test/CodeGen/AArch64/neon_rbit.ll (revision 3d18c8cd265c0c0bf1d85226c4770a2dd0f86e8f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 %s -o - | FileCheck %s
3
4; The llvm.aarch64_neon_rbit intrinsic should be auto-upgraded to the
5; target-independent bitreverse intrinsic.
6
7declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
8
9define <8 x i8> @rbit_8x8(<8 x i8> %A) nounwind {
10; CHECK-LABEL: rbit_8x8:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    rbit v0.8b, v0.8b
13; CHECK-NEXT:    ret
14    %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %A)
15	ret <8 x i8> %tmp3
16}
17
18declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
19
20define <16 x i8> @rbit_16x8(<16 x i8> %A) nounwind {
21; CHECK-LABEL: rbit_16x8:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    rbit v0.16b, v0.16b
24; CHECK-NEXT:    ret
25    %tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %A)
26	ret <16 x i8> %tmp3
27}
28
29declare <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16>) nounwind readnone
30
31define <4 x i16> @rbit_4x16(<4 x i16> %A) nounwind {
32; CHECK-LABEL: rbit_4x16:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    rev16 v0.8b, v0.8b
35; CHECK-NEXT:    rbit v0.8b, v0.8b
36; CHECK-NEXT:    ret
37    %tmp3 = call <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16> %A)
38	ret <4 x i16> %tmp3
39}
40
41declare <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16>) nounwind readnone
42
43define <8 x i16> @rbit_8x16(<8 x i16> %A) {
44; CHECK-LABEL: rbit_8x16:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    rev16 v0.16b, v0.16b
47; CHECK-NEXT:    rbit v0.16b, v0.16b
48; CHECK-NEXT:    ret
49  %tmp3 = call <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16> %A)
50  ret <8 x i16> %tmp3
51}
52
53declare <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32>) nounwind readnone
54
55define <2 x i32> @rbit_2x32(<2 x i32> %A) {
56; CHECK-LABEL: rbit_2x32:
57; CHECK:       // %bb.0:
58; CHECK-NEXT:    rev32 v0.8b, v0.8b
59; CHECK-NEXT:    rbit v0.8b, v0.8b
60; CHECK-NEXT:    ret
61  %tmp3 = call <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32> %A)
62  ret <2 x i32> %tmp3
63}
64
65declare <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32>) nounwind readnone
66
67define <4 x i32> @rbit_4x32(<4 x i32> %A) {
68; CHECK-LABEL: rbit_4x32:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    rev32 v0.16b, v0.16b
71; CHECK-NEXT:    rbit v0.16b, v0.16b
72; CHECK-NEXT:    ret
73  %tmp3 = call <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32> %A)
74  ret <4 x i32> %tmp3
75}
76
77declare <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64>) readnone
78
79define <1 x i64> @rbit_1x64(<1 x i64> %A) {
80; CHECK-LABEL: rbit_1x64:
81; CHECK:       // %bb.0:
82; CHECK-NEXT:    rev64 v0.8b, v0.8b
83; CHECK-NEXT:    rbit v0.8b, v0.8b
84; CHECK-NEXT:    ret
85  %tmp3 = call <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64> %A)
86  ret <1 x i64> %tmp3
87}
88
89declare <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64>) readnone
90
91define <2 x i64> @rbit_2x64(<2 x i64> %A) {
92; CHECK-LABEL: rbit_2x64:
93; CHECK:       // %bb.0:
94; CHECK-NEXT:    rev64 v0.16b, v0.16b
95; CHECK-NEXT:    rbit v0.16b, v0.16b
96; CHECK-NEXT:    ret
97  %tmp3 = call <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64> %A)
98  ret <2 x i64> %tmp3
99}
100