xref: /llvm-project/llvm/test/CodeGen/AArch64/neon-wide-splat.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3
4define <4 x i16> @shuffle1(<4 x i16> %v) {
5; CHECK-LABEL: shuffle1:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
8; CHECK-NEXT:    dup v0.2s, v0.s[0]
9; CHECK-NEXT:    ret
10entry:
11  %res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 1>
12  ret <4 x i16> %res
13}
14
15define <4 x i16> @shuffle2(<4 x i16> %v) {
16; CHECK-LABEL: shuffle2:
17; CHECK:       // %bb.0: // %entry
18; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
19; CHECK-NEXT:    dup v0.2s, v0.s[1]
20; CHECK-NEXT:    ret
21entry:
22  %res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 3>
23  ret <4 x i16> %res
24}
25
26define <8 x i16> @shuffle3(<8 x i16> %v) {
27; CHECK-LABEL: shuffle3:
28; CHECK:       // %bb.0: // %entry
29; CHECK-NEXT:    dup v0.2d, v0.d[0]
30; CHECK-NEXT:    ret
31entry:
32  %res = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3,
33                                                                 i32 undef, i32 1, i32 undef, i32 3>
34  ret <8 x i16> %res
35}
36
37define <4 x i32> @shuffle4(<4 x i32> %v) {
38; CHECK-LABEL: shuffle4:
39; CHECK:       // %bb.0: // %entry
40; CHECK-NEXT:    dup v0.2d, v0.d[0]
41; CHECK-NEXT:    ret
42entry:
43  %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
44  ret <4 x i32> %res
45}
46
47define <16 x i8> @shuffle5(<16 x i8> %v) {
48; CHECK-LABEL: shuffle5:
49; CHECK:       // %bb.0: // %entry
50; CHECK-NEXT:    dup v0.4s, v0.s[2]
51; CHECK-NEXT:    ret
52entry:
53  %res = shufflevector <16 x i8> %v, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11,
54                                                                  i32 8, i32 9, i32 10, i32 11,
55                                                                  i32 8, i32 9, i32 10, i32 11,
56                                                                  i32 8, i32 9, i32 10, i32 11>
57  ret <16 x i8> %res
58}
59
60define <16 x i8> @shuffle6(<16 x i8> %v) {
61; CHECK-LABEL: shuffle6:
62; CHECK:       // %bb.0: // %entry
63; CHECK-NEXT:    dup v0.2d, v0.d[1]
64; CHECK-NEXT:    ret
65entry:
66  %res = shufflevector <16 x i8> %v, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11,
67                                                                  i32 12, i32 13, i32 14, i32 15,
68                                                                  i32 8, i32 9, i32 10, i32 11,
69                                                                  i32 12, i32 13, i32 14, i32 15>
70  ret <16 x i8> %res
71}
72
73define <8 x i8> @shuffle7(<8 x i8> %v) {
74; CHECK-LABEL: shuffle7:
75; CHECK:       // %bb.0: // %entry
76; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
77; CHECK-NEXT:    dup v0.2s, v0.s[1]
78; CHECK-NEXT:    ret
79entry:
80  %res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef,
81                                                               i32 undef, i32 5, i32 6, i32 undef>
82  ret <8 x i8> %res
83}
84
85define <8 x i8> @shuffle8(<8 x i8> %v) {
86; CHECK-LABEL: shuffle8:
87; CHECK:       // %bb.0: // %entry
88; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
89; CHECK-NEXT:    dup v0.4h, v0.h[3]
90; CHECK-NEXT:    ret
91entry:
92  %res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 6, i32 7, i32 6, i32 undef,
93                                                               i32 undef, i32 7, i32 6, i32 undef>
94  ret <8 x i8> %res
95}
96
97; No blocks
98define <8 x i8> @shuffle_not1(<16 x i8> %v) {
99; CHECK-LABEL: shuffle_not1:
100; CHECK:       // %bb.0:
101; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #2
102; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
103; CHECK-NEXT:    ret
104  %res = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
105  ret <8 x i8> %res
106}
107
108; Block is not a proper lane
109define <4 x i32> @shuffle_not2(<4 x i32> %v) {
110; CHECK-LABEL: shuffle_not2:
111; CHECK:       // %bb.0: // %entry
112; CHECK-NEXT:    mov v0.s[3], v0.s[2]
113; CHECK-NEXT:    uzp2 v0.4s, v0.4s, v0.4s
114; CHECK-NEXT:    ret
115entry:
116  %res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 2>
117  ret <4 x i32> %res
118}
119
120; Block size is equal to vector size
121define <4 x i16> @shuffle_not3(<4 x i16> %v) {
122; CHECK-LABEL: shuffle_not3:
123; CHECK:       // %bb.0: // %entry
124; CHECK-NEXT:    ret
125entry:
126  %res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
127  ret <4 x i16> %res
128}
129
130; Blocks mismatch
131define <8 x i8> @shuffle_not4(<8 x i8> %v) {
132; CHECK-LABEL: shuffle_not4:
133; CHECK:       // %bb.0: // %entry
134; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
135; CHECK-NEXT:    adrp x8, .LCPI11_0
136; CHECK-NEXT:    mov v0.d[1], v0.d[0]
137; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI11_0]
138; CHECK-NEXT:    tbl v0.8b, { v0.16b }, v1.8b
139; CHECK-NEXT:    ret
140entry:
141  %res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef,
142                                                               i32 undef, i32 5, i32 5, i32 undef>
143  ret <8 x i8> %res
144}
145