1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s 3 4declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1 immarg) 5declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>) 6 7define i32 @test_sad_v16i8_zext(ptr nocapture readonly %a, ptr nocapture readonly %b) { 8; CHECK-LABEL: test_sad_v16i8_zext: 9; CHECK: // %bb.0: // %entry 10; CHECK-NEXT: ldr q0, [x0] 11; CHECK-NEXT: ldr q1, [x1] 12; CHECK-NEXT: uabdl v2.8h, v1.8b, v0.8b 13; CHECK-NEXT: uabal2 v2.8h, v1.16b, v0.16b 14; CHECK-NEXT: uaddlv s0, v2.8h 15; CHECK-NEXT: fmov w0, s0 16; CHECK-NEXT: ret 17entry: 18 %0 = load <16 x i8>, ptr %a 19 %1 = zext <16 x i8> %0 to <16 x i32> 20 %2 = load <16 x i8>, ptr %b 21 %3 = zext <16 x i8> %2 to <16 x i32> 22 %4 = sub nsw <16 x i32> %3, %1 23 %5 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true) 24 %6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5) 25 ret i32 %6 26} 27 28define i32 @test_sad_v16i8_sext(ptr nocapture readonly %a, ptr nocapture readonly %b) { 29; CHECK-LABEL: test_sad_v16i8_sext: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: ldr q0, [x0] 32; CHECK-NEXT: ldr q1, [x1] 33; CHECK-NEXT: sabdl v2.8h, v1.8b, v0.8b 34; CHECK-NEXT: sabal2 v2.8h, v1.16b, v0.16b 35; CHECK-NEXT: uaddlv s0, v2.8h 36; CHECK-NEXT: fmov w0, s0 37; CHECK-NEXT: ret 38entry: 39 %0 = load <16 x i8>, ptr %a 40 %1 = sext <16 x i8> %0 to <16 x i32> 41 %2 = load <16 x i8>, ptr %b 42 %3 = sext <16 x i8> %2 to <16 x i32> 43 %4 = sub nsw <16 x i32> %3, %1 44 %5 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true) 45 %6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5) 46 ret i32 %6 47} 48