xref: /llvm-project/llvm/test/CodeGen/AArch64/neon-dotpattern.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod    < %s | FileCheck %s
3
4define fastcc void @test_sdot_v4i8(ptr noalias nocapture %0, ptr noalias nocapture readonly %1, ptr noalias nocapture readonly %2) {
5; CHECK-LABEL: test_sdot_v4i8:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    ldr w8, [x2]
8; CHECK-NEXT:    ldr w9, [x1]
9; CHECK-NEXT:    dup v0.2s, wzr
10; CHECK-NEXT:    fmov s1, w8
11; CHECK-NEXT:    fmov s2, w9
12; CHECK-NEXT:    sdot v0.2s, v1.8b, v2.8b
13; CHECK-NEXT:    fmov x8, d0
14; CHECK-NEXT:    str w8, [x0]
15; CHECK-NEXT:    ret
16entry:
17  %3 = load i8, ptr %1, align 1
18  %4 = sext i8 %3 to i32
19  %5 = load i8, ptr %2, align 1
20  %6 = sext i8 %5 to i32
21  %7 = mul nsw i32 %6, %4
22  %8 = getelementptr inbounds i8, ptr %1, i64 1
23  %9 = load i8, ptr %8, align 1
24  %10 = sext i8 %9 to i32
25  %11 = getelementptr inbounds i8, ptr %2, i64 1
26  %12 = load i8, ptr %11, align 1
27  %13 = sext i8 %12 to i32
28  %14 = mul nsw i32 %13, %10
29  %15 = add nsw i32 %14, %7
30  %16 = getelementptr inbounds i8, ptr %1, i64 2
31  %17 = load i8, ptr %16, align 1
32  %18 = sext i8 %17 to i32
33  %19 = getelementptr inbounds i8, ptr %2, i64 2
34  %20 = load i8, ptr %19, align 1
35  %21 = sext i8 %20 to i32
36  %22 = mul nsw i32 %21, %18
37  %23 = add nsw i32 %22, %15
38  %24 = getelementptr inbounds i8, ptr %1, i64 3
39  %25 = load i8, ptr %24, align 1
40  %26 = sext i8 %25 to i32
41  %27 = getelementptr inbounds i8, ptr %2, i64 3
42  %28 = load i8, ptr %27, align 1
43  %29 = sext i8 %28 to i32
44  %30 = mul nsw i32 %29, %26
45  %31 = add nsw i32 %30, %23
46  store i32 %31, ptr %0, align 64
47  ret void
48}
49
50define fastcc void @test_udot_v4i8(ptr noalias nocapture %0, ptr noalias nocapture readonly %1, ptr noalias nocapture readonly %2) {
51; CHECK-LABEL: test_udot_v4i8:
52; CHECK:       // %bb.0: // %entry
53; CHECK-NEXT:    ldr w8, [x2]
54; CHECK-NEXT:    ldr w9, [x1]
55; CHECK-NEXT:    dup v0.2s, wzr
56; CHECK-NEXT:    fmov s1, w8
57; CHECK-NEXT:    fmov s2, w9
58; CHECK-NEXT:    udot v0.2s, v1.8b, v2.8b
59; CHECK-NEXT:    fmov x8, d0
60; CHECK-NEXT:    str w8, [x0]
61; CHECK-NEXT:    ret
62entry:
63  %3 = load i8, ptr %1, align 1
64  %4 = zext i8 %3 to i32
65  %5 = load i8, ptr %2, align 1
66  %6 = zext i8 %5 to i32
67  %7 = mul nsw i32 %6, %4
68  %8 = getelementptr inbounds i8, ptr %1, i64 1
69  %9 = load i8, ptr %8, align 1
70  %10 = zext i8 %9 to i32
71  %11 = getelementptr inbounds i8, ptr %2, i64 1
72  %12 = load i8, ptr %11, align 1
73  %13 = zext i8 %12 to i32
74  %14 = mul nsw i32 %13, %10
75  %15 = add nsw i32 %14, %7
76  %16 = getelementptr inbounds i8, ptr %1, i64 2
77  %17 = load i8, ptr %16, align 1
78  %18 = zext i8 %17 to i32
79  %19 = getelementptr inbounds i8, ptr %2, i64 2
80  %20 = load i8, ptr %19, align 1
81  %21 = zext i8 %20 to i32
82  %22 = mul nsw i32 %21, %18
83  %23 = add nsw i32 %22, %15
84  %24 = getelementptr inbounds i8, ptr %1, i64 3
85  %25 = load i8, ptr %24, align 1
86  %26 = zext i8 %25 to i32
87  %27 = getelementptr inbounds i8, ptr %2, i64 3
88  %28 = load i8, ptr %27, align 1
89  %29 = zext i8 %28 to i32
90  %30 = mul nsw i32 %29, %26
91  %31 = add nsw i32 %30, %23
92  store i32 %31, ptr %0, align 64
93  ret void
94}
95