1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD 3; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI 4 5define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) { 6; CHECK-LABEL: cmeq8xi8: 7; CHECK: // %bb.0: 8; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 9; CHECK-NEXT: ret 10 %tmp3 = icmp eq <8 x i8> %A, %B 11 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 12 ret <8 x i8> %tmp4 13} 14 15define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) { 16; CHECK-LABEL: cmeq16xi8: 17; CHECK: // %bb.0: 18; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b 19; CHECK-NEXT: ret 20 %tmp3 = icmp eq <16 x i8> %A, %B 21 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 22 ret <16 x i8> %tmp4 23} 24 25define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) { 26; CHECK-LABEL: cmeq4xi16: 27; CHECK: // %bb.0: 28; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h 29; CHECK-NEXT: ret 30 %tmp3 = icmp eq <4 x i16> %A, %B 31 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 32 ret <4 x i16> %tmp4 33} 34 35define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) { 36; CHECK-LABEL: cmeq8xi16: 37; CHECK: // %bb.0: 38; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h 39; CHECK-NEXT: ret 40 %tmp3 = icmp eq <8 x i16> %A, %B 41 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 42 ret <8 x i16> %tmp4 43} 44 45define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) { 46; CHECK-LABEL: cmeq2xi32: 47; CHECK: // %bb.0: 48; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s 49; CHECK-NEXT: ret 50 %tmp3 = icmp eq <2 x i32> %A, %B 51 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 52 ret <2 x i32> %tmp4 53} 54 55define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) { 56; CHECK-LABEL: cmeq4xi32: 57; CHECK: // %bb.0: 58; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s 59; CHECK-NEXT: ret 60 %tmp3 = icmp eq <4 x i32> %A, %B 61 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 62 ret <4 x i32> %tmp4 63} 64 65define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) { 66; CHECK-LABEL: cmeq2xi64: 67; CHECK: // %bb.0: 68; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d 69; CHECK-NEXT: ret 70 %tmp3 = icmp eq <2 x i64> %A, %B 71 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 72 ret <2 x i64> %tmp4 73} 74 75define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { 76; CHECK-LABEL: cmne8xi8: 77; CHECK: // %bb.0: 78; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b 79; CHECK-NEXT: mvn v0.8b, v0.8b 80; CHECK-NEXT: ret 81 %tmp3 = icmp ne <8 x i8> %A, %B 82 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 83 ret <8 x i8> %tmp4 84} 85 86define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { 87; CHECK-LABEL: cmne16xi8: 88; CHECK: // %bb.0: 89; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b 90; CHECK-NEXT: mvn v0.16b, v0.16b 91; CHECK-NEXT: ret 92 %tmp3 = icmp ne <16 x i8> %A, %B 93 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 94 ret <16 x i8> %tmp4 95} 96 97define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { 98; CHECK-LABEL: cmne4xi16: 99; CHECK: // %bb.0: 100; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h 101; CHECK-NEXT: mvn v0.8b, v0.8b 102; CHECK-NEXT: ret 103 %tmp3 = icmp ne <4 x i16> %A, %B 104 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 105 ret <4 x i16> %tmp4 106} 107 108define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { 109; CHECK-LABEL: cmne8xi16: 110; CHECK: // %bb.0: 111; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h 112; CHECK-NEXT: mvn v0.16b, v0.16b 113; CHECK-NEXT: ret 114 %tmp3 = icmp ne <8 x i16> %A, %B 115 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 116 ret <8 x i16> %tmp4 117} 118 119define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { 120; CHECK-LABEL: cmne2xi32: 121; CHECK: // %bb.0: 122; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s 123; CHECK-NEXT: mvn v0.8b, v0.8b 124; CHECK-NEXT: ret 125 %tmp3 = icmp ne <2 x i32> %A, %B 126 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 127 ret <2 x i32> %tmp4 128} 129 130define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { 131; CHECK-LABEL: cmne4xi32: 132; CHECK: // %bb.0: 133; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s 134; CHECK-NEXT: mvn v0.16b, v0.16b 135; CHECK-NEXT: ret 136 %tmp3 = icmp ne <4 x i32> %A, %B 137 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 138 ret <4 x i32> %tmp4 139} 140 141define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) { 142; CHECK-LABEL: cmne2xi64: 143; CHECK: // %bb.0: 144; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d 145; CHECK-NEXT: mvn v0.16b, v0.16b 146; CHECK-NEXT: ret 147 %tmp3 = icmp ne <2 x i64> %A, %B 148 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 149 ret <2 x i64> %tmp4 150} 151 152define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) { 153; CHECK-LABEL: cmgt8xi8: 154; CHECK: // %bb.0: 155; CHECK-NEXT: cmgt v0.8b, v0.8b, v1.8b 156; CHECK-NEXT: ret 157 %tmp3 = icmp sgt <8 x i8> %A, %B 158 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 159 ret <8 x i8> %tmp4 160} 161 162define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) { 163; CHECK-LABEL: cmgt16xi8: 164; CHECK: // %bb.0: 165; CHECK-NEXT: cmgt v0.16b, v0.16b, v1.16b 166; CHECK-NEXT: ret 167 %tmp3 = icmp sgt <16 x i8> %A, %B 168 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 169 ret <16 x i8> %tmp4 170} 171 172define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) { 173; CHECK-LABEL: cmgt4xi16: 174; CHECK: // %bb.0: 175; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h 176; CHECK-NEXT: ret 177 %tmp3 = icmp sgt <4 x i16> %A, %B 178 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 179 ret <4 x i16> %tmp4 180} 181 182define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) { 183; CHECK-LABEL: cmgt8xi16: 184; CHECK: // %bb.0: 185; CHECK-NEXT: cmgt v0.8h, v0.8h, v1.8h 186; CHECK-NEXT: ret 187 %tmp3 = icmp sgt <8 x i16> %A, %B 188 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 189 ret <8 x i16> %tmp4 190} 191 192define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) { 193; CHECK-LABEL: cmgt2xi32: 194; CHECK: // %bb.0: 195; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s 196; CHECK-NEXT: ret 197 %tmp3 = icmp sgt <2 x i32> %A, %B 198 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 199 ret <2 x i32> %tmp4 200} 201 202define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) { 203; CHECK-LABEL: cmgt4xi32: 204; CHECK: // %bb.0: 205; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s 206; CHECK-NEXT: ret 207 %tmp3 = icmp sgt <4 x i32> %A, %B 208 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 209 ret <4 x i32> %tmp4 210} 211 212define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) { 213; CHECK-LABEL: cmgt2xi64: 214; CHECK: // %bb.0: 215; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d 216; CHECK-NEXT: ret 217 %tmp3 = icmp sgt <2 x i64> %A, %B 218 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 219 ret <2 x i64> %tmp4 220} 221 222; LT implemented as GT, so check reversed operands. 223define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) { 224; CHECK-LABEL: cmlt8xi8: 225; CHECK: // %bb.0: 226; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b 227; CHECK-NEXT: ret 228 %tmp3 = icmp slt <8 x i8> %A, %B 229 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 230 ret <8 x i8> %tmp4 231} 232 233; LT implemented as GT, so check reversed operands. 234define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) { 235; CHECK-LABEL: cmlt16xi8: 236; CHECK: // %bb.0: 237; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b 238; CHECK-NEXT: ret 239 %tmp3 = icmp slt <16 x i8> %A, %B 240 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 241 ret <16 x i8> %tmp4 242} 243 244; LT implemented as GT, so check reversed operands. 245define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) { 246; CHECK-LABEL: cmlt4xi16: 247; CHECK: // %bb.0: 248; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h 249; CHECK-NEXT: ret 250 %tmp3 = icmp slt <4 x i16> %A, %B 251 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 252 ret <4 x i16> %tmp4 253} 254 255; LT implemented as GT, so check reversed operands. 256define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) { 257; CHECK-LABEL: cmlt8xi16: 258; CHECK: // %bb.0: 259; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h 260; CHECK-NEXT: ret 261 %tmp3 = icmp slt <8 x i16> %A, %B 262 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 263 ret <8 x i16> %tmp4 264} 265 266; LT implemented as GT, so check reversed operands. 267define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) { 268; CHECK-LABEL: cmlt2xi32: 269; CHECK: // %bb.0: 270; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s 271; CHECK-NEXT: ret 272 %tmp3 = icmp slt <2 x i32> %A, %B 273 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 274 ret <2 x i32> %tmp4 275} 276 277; LT implemented as GT, so check reversed operands. 278define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) { 279; CHECK-LABEL: cmlt4xi32: 280; CHECK: // %bb.0: 281; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s 282; CHECK-NEXT: ret 283 %tmp3 = icmp slt <4 x i32> %A, %B 284 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 285 ret <4 x i32> %tmp4 286} 287 288; LT implemented as GT, so check reversed operands. 289define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) { 290; CHECK-LABEL: cmlt2xi64: 291; CHECK: // %bb.0: 292; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d 293; CHECK-NEXT: ret 294 %tmp3 = icmp slt <2 x i64> %A, %B 295 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 296 ret <2 x i64> %tmp4 297} 298 299define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) { 300; CHECK-LABEL: cmge8xi8: 301; CHECK: // %bb.0: 302; CHECK-NEXT: cmge v0.8b, v0.8b, v1.8b 303; CHECK-NEXT: ret 304 %tmp3 = icmp sge <8 x i8> %A, %B 305 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 306 ret <8 x i8> %tmp4 307} 308 309define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) { 310; CHECK-LABEL: cmge16xi8: 311; CHECK: // %bb.0: 312; CHECK-NEXT: cmge v0.16b, v0.16b, v1.16b 313; CHECK-NEXT: ret 314 %tmp3 = icmp sge <16 x i8> %A, %B 315 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 316 ret <16 x i8> %tmp4 317} 318 319define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) { 320; CHECK-LABEL: cmge4xi16: 321; CHECK: // %bb.0: 322; CHECK-NEXT: cmge v0.4h, v0.4h, v1.4h 323; CHECK-NEXT: ret 324 %tmp3 = icmp sge <4 x i16> %A, %B 325 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 326 ret <4 x i16> %tmp4 327} 328 329define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) { 330; CHECK-LABEL: cmge8xi16: 331; CHECK: // %bb.0: 332; CHECK-NEXT: cmge v0.8h, v0.8h, v1.8h 333; CHECK-NEXT: ret 334 %tmp3 = icmp sge <8 x i16> %A, %B 335 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 336 ret <8 x i16> %tmp4 337} 338 339define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) { 340; CHECK-LABEL: cmge2xi32: 341; CHECK: // %bb.0: 342; CHECK-NEXT: cmge v0.2s, v0.2s, v1.2s 343; CHECK-NEXT: ret 344 %tmp3 = icmp sge <2 x i32> %A, %B 345 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 346 ret <2 x i32> %tmp4 347} 348 349define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) { 350; CHECK-LABEL: cmge4xi32: 351; CHECK: // %bb.0: 352; CHECK-NEXT: cmge v0.4s, v0.4s, v1.4s 353; CHECK-NEXT: ret 354 %tmp3 = icmp sge <4 x i32> %A, %B 355 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 356 ret <4 x i32> %tmp4 357} 358 359define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) { 360; CHECK-LABEL: cmge2xi64: 361; CHECK: // %bb.0: 362; CHECK-NEXT: cmge v0.2d, v0.2d, v1.2d 363; CHECK-NEXT: ret 364 %tmp3 = icmp sge <2 x i64> %A, %B 365 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 366 ret <2 x i64> %tmp4 367} 368 369; LE implemented as GE, so check reversed operands. 370define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) { 371; CHECK-LABEL: cmle8xi8: 372; CHECK: // %bb.0: 373; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b 374; CHECK-NEXT: ret 375 %tmp3 = icmp sle <8 x i8> %A, %B 376 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 377 ret <8 x i8> %tmp4 378} 379 380; LE implemented as GE, so check reversed operands. 381define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) { 382; CHECK-LABEL: cmle16xi8: 383; CHECK: // %bb.0: 384; CHECK-NEXT: cmge v0.16b, v1.16b, v0.16b 385; CHECK-NEXT: ret 386 %tmp3 = icmp sle <16 x i8> %A, %B 387 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 388 ret <16 x i8> %tmp4 389} 390 391; LE implemented as GE, so check reversed operands. 392define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) { 393; CHECK-LABEL: cmle4xi16: 394; CHECK: // %bb.0: 395; CHECK-NEXT: cmge v0.4h, v1.4h, v0.4h 396; CHECK-NEXT: ret 397 %tmp3 = icmp sle <4 x i16> %A, %B 398 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 399 ret <4 x i16> %tmp4 400} 401 402; LE implemented as GE, so check reversed operands. 403define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) { 404; CHECK-LABEL: cmle8xi16: 405; CHECK: // %bb.0: 406; CHECK-NEXT: cmge v0.8h, v1.8h, v0.8h 407; CHECK-NEXT: ret 408 %tmp3 = icmp sle <8 x i16> %A, %B 409 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 410 ret <8 x i16> %tmp4 411} 412 413; LE implemented as GE, so check reversed operands. 414define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) { 415; CHECK-LABEL: cmle2xi32: 416; CHECK: // %bb.0: 417; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s 418; CHECK-NEXT: ret 419 %tmp3 = icmp sle <2 x i32> %A, %B 420 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 421 ret <2 x i32> %tmp4 422} 423 424; LE implemented as GE, so check reversed operands. 425define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) { 426; CHECK-LABEL: cmle4xi32: 427; CHECK: // %bb.0: 428; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s 429; CHECK-NEXT: ret 430 %tmp3 = icmp sle <4 x i32> %A, %B 431 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 432 ret <4 x i32> %tmp4 433} 434 435; LE implemented as GE, so check reversed operands. 436define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) { 437; CHECK-LABEL: cmle2xi64: 438; CHECK: // %bb.0: 439; CHECK-NEXT: cmge v0.2d, v1.2d, v0.2d 440; CHECK-NEXT: ret 441 %tmp3 = icmp sle <2 x i64> %A, %B 442 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 443 ret <2 x i64> %tmp4 444} 445 446define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) { 447; CHECK-LABEL: cmhi8xi8: 448; CHECK: // %bb.0: 449; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b 450; CHECK-NEXT: ret 451 %tmp3 = icmp ugt <8 x i8> %A, %B 452 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 453 ret <8 x i8> %tmp4 454} 455 456define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) { 457; CHECK-LABEL: cmhi16xi8: 458; CHECK: // %bb.0: 459; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b 460; CHECK-NEXT: ret 461 %tmp3 = icmp ugt <16 x i8> %A, %B 462 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 463 ret <16 x i8> %tmp4 464} 465 466define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) { 467; CHECK-LABEL: cmhi4xi16: 468; CHECK: // %bb.0: 469; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h 470; CHECK-NEXT: ret 471 %tmp3 = icmp ugt <4 x i16> %A, %B 472 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 473 ret <4 x i16> %tmp4 474} 475 476define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) { 477; CHECK-LABEL: cmhi8xi16: 478; CHECK: // %bb.0: 479; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h 480; CHECK-NEXT: ret 481 %tmp3 = icmp ugt <8 x i16> %A, %B 482 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 483 ret <8 x i16> %tmp4 484} 485 486define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) { 487; CHECK-LABEL: cmhi2xi32: 488; CHECK: // %bb.0: 489; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s 490; CHECK-NEXT: ret 491 %tmp3 = icmp ugt <2 x i32> %A, %B 492 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 493 ret <2 x i32> %tmp4 494} 495 496define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) { 497; CHECK-LABEL: cmhi4xi32: 498; CHECK: // %bb.0: 499; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s 500; CHECK-NEXT: ret 501 %tmp3 = icmp ugt <4 x i32> %A, %B 502 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 503 ret <4 x i32> %tmp4 504} 505 506define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) { 507; CHECK-LABEL: cmhi2xi64: 508; CHECK: // %bb.0: 509; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d 510; CHECK-NEXT: ret 511 %tmp3 = icmp ugt <2 x i64> %A, %B 512 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 513 ret <2 x i64> %tmp4 514} 515 516; LO implemented as HI, so check reversed operands. 517define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) { 518; CHECK-LABEL: cmlo8xi8: 519; CHECK: // %bb.0: 520; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b 521; CHECK-NEXT: ret 522 %tmp3 = icmp ult <8 x i8> %A, %B 523 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 524 ret <8 x i8> %tmp4 525} 526 527; LO implemented as HI, so check reversed operands. 528define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) { 529; CHECK-LABEL: cmlo16xi8: 530; CHECK: // %bb.0: 531; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b 532; CHECK-NEXT: ret 533 %tmp3 = icmp ult <16 x i8> %A, %B 534 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 535 ret <16 x i8> %tmp4 536} 537 538; LO implemented as HI, so check reversed operands. 539define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) { 540; CHECK-LABEL: cmlo4xi16: 541; CHECK: // %bb.0: 542; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h 543; CHECK-NEXT: ret 544 %tmp3 = icmp ult <4 x i16> %A, %B 545 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 546 ret <4 x i16> %tmp4 547} 548 549; LO implemented as HI, so check reversed operands. 550define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) { 551; CHECK-LABEL: cmlo8xi16: 552; CHECK: // %bb.0: 553; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h 554; CHECK-NEXT: ret 555 %tmp3 = icmp ult <8 x i16> %A, %B 556 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 557 ret <8 x i16> %tmp4 558} 559 560; LO implemented as HI, so check reversed operands. 561define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) { 562; CHECK-LABEL: cmlo2xi32: 563; CHECK: // %bb.0: 564; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s 565; CHECK-NEXT: ret 566 %tmp3 = icmp ult <2 x i32> %A, %B 567 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 568 ret <2 x i32> %tmp4 569} 570 571; LO implemented as HI, so check reversed operands. 572define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) { 573; CHECK-LABEL: cmlo4xi32: 574; CHECK: // %bb.0: 575; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s 576; CHECK-NEXT: ret 577 %tmp3 = icmp ult <4 x i32> %A, %B 578 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 579 ret <4 x i32> %tmp4 580} 581 582; LO implemented as HI, so check reversed operands. 583define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) { 584; CHECK-LABEL: cmlo2xi64: 585; CHECK: // %bb.0: 586; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d 587; CHECK-NEXT: ret 588 %tmp3 = icmp ult <2 x i64> %A, %B 589 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 590 ret <2 x i64> %tmp4 591} 592 593define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) { 594; CHECK-LABEL: cmhs8xi8: 595; CHECK: // %bb.0: 596; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b 597; CHECK-NEXT: ret 598 %tmp3 = icmp uge <8 x i8> %A, %B 599 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 600 ret <8 x i8> %tmp4 601} 602 603define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) { 604; CHECK-LABEL: cmhs16xi8: 605; CHECK: // %bb.0: 606; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b 607; CHECK-NEXT: ret 608 %tmp3 = icmp uge <16 x i8> %A, %B 609 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 610 ret <16 x i8> %tmp4 611} 612 613define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) { 614; CHECK-LABEL: cmhs4xi16: 615; CHECK: // %bb.0: 616; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h 617; CHECK-NEXT: ret 618 %tmp3 = icmp uge <4 x i16> %A, %B 619 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 620 ret <4 x i16> %tmp4 621} 622 623define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) { 624; CHECK-LABEL: cmhs8xi16: 625; CHECK: // %bb.0: 626; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h 627; CHECK-NEXT: ret 628 %tmp3 = icmp uge <8 x i16> %A, %B 629 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 630 ret <8 x i16> %tmp4 631} 632 633define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) { 634; CHECK-LABEL: cmhs2xi32: 635; CHECK: // %bb.0: 636; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s 637; CHECK-NEXT: ret 638 %tmp3 = icmp uge <2 x i32> %A, %B 639 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 640 ret <2 x i32> %tmp4 641} 642 643define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) { 644; CHECK-LABEL: cmhs4xi32: 645; CHECK: // %bb.0: 646; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s 647; CHECK-NEXT: ret 648 %tmp3 = icmp uge <4 x i32> %A, %B 649 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 650 ret <4 x i32> %tmp4 651} 652 653define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) { 654; CHECK-LABEL: cmhs2xi64: 655; CHECK: // %bb.0: 656; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d 657; CHECK-NEXT: ret 658 %tmp3 = icmp uge <2 x i64> %A, %B 659 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 660 ret <2 x i64> %tmp4 661} 662 663; LS implemented as HS, so check reversed operands. 664define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) { 665; CHECK-LABEL: cmls8xi8: 666; CHECK: // %bb.0: 667; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b 668; CHECK-NEXT: ret 669 %tmp3 = icmp ule <8 x i8> %A, %B 670 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 671 ret <8 x i8> %tmp4 672} 673 674; LS implemented as HS, so check reversed operands. 675define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) { 676; CHECK-LABEL: cmls16xi8: 677; CHECK: // %bb.0: 678; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b 679; CHECK-NEXT: ret 680 %tmp3 = icmp ule <16 x i8> %A, %B 681 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 682 ret <16 x i8> %tmp4 683} 684 685; LS implemented as HS, so check reversed operands. 686define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) { 687; CHECK-LABEL: cmls4xi16: 688; CHECK: // %bb.0: 689; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h 690; CHECK-NEXT: ret 691 %tmp3 = icmp ule <4 x i16> %A, %B 692 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 693 ret <4 x i16> %tmp4 694} 695 696; LS implemented as HS, so check reversed operands. 697define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) { 698; CHECK-LABEL: cmls8xi16: 699; CHECK: // %bb.0: 700; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h 701; CHECK-NEXT: ret 702 %tmp3 = icmp ule <8 x i16> %A, %B 703 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 704 ret <8 x i16> %tmp4 705} 706 707; LS implemented as HS, so check reversed operands. 708define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) { 709; CHECK-LABEL: cmls2xi32: 710; CHECK: // %bb.0: 711; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s 712; CHECK-NEXT: ret 713 %tmp3 = icmp ule <2 x i32> %A, %B 714 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 715 ret <2 x i32> %tmp4 716} 717 718; LS implemented as HS, so check reversed operands. 719define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) { 720; CHECK-LABEL: cmls4xi32: 721; CHECK: // %bb.0: 722; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 723; CHECK-NEXT: ret 724 %tmp3 = icmp ule <4 x i32> %A, %B 725 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 726 ret <4 x i32> %tmp4 727} 728 729; LS implemented as HS, so check reversed operands. 730define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) { 731; CHECK-LABEL: cmls2xi64: 732; CHECK: // %bb.0: 733; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d 734; CHECK-NEXT: ret 735 %tmp3 = icmp ule <2 x i64> %A, %B 736 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 737 ret <2 x i64> %tmp4 738} 739 740define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) { 741; CHECK-SD-LABEL: cmtst8xi8: 742; CHECK-SD: // %bb.0: 743; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b 744; CHECK-SD-NEXT: ret 745; 746; CHECK-GI-LABEL: cmtst8xi8: 747; CHECK-GI: // %bb.0: 748; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 749; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0 750; CHECK-GI-NEXT: mvn v0.8b, v0.8b 751; CHECK-GI-NEXT: ret 752 %tmp3 = and <8 x i8> %A, %B 753 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer 754 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8> 755 ret <8 x i8> %tmp5 756} 757 758define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) { 759; CHECK-SD-LABEL: cmtst16xi8: 760; CHECK-SD: // %bb.0: 761; CHECK-SD-NEXT: cmtst v0.16b, v0.16b, v1.16b 762; CHECK-SD-NEXT: ret 763; 764; CHECK-GI-LABEL: cmtst16xi8: 765; CHECK-GI: // %bb.0: 766; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 767; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, #0 768; CHECK-GI-NEXT: mvn v0.16b, v0.16b 769; CHECK-GI-NEXT: ret 770 %tmp3 = and <16 x i8> %A, %B 771 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer 772 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8> 773 ret <16 x i8> %tmp5 774} 775 776define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) { 777; CHECK-SD-LABEL: cmtst4xi16: 778; CHECK-SD: // %bb.0: 779; CHECK-SD-NEXT: cmtst v0.4h, v0.4h, v1.4h 780; CHECK-SD-NEXT: ret 781; 782; CHECK-GI-LABEL: cmtst4xi16: 783; CHECK-GI: // %bb.0: 784; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 785; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, #0 786; CHECK-GI-NEXT: mvn v0.8b, v0.8b 787; CHECK-GI-NEXT: ret 788 %tmp3 = and <4 x i16> %A, %B 789 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer 790 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16> 791 ret <4 x i16> %tmp5 792} 793 794define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) { 795; CHECK-SD-LABEL: cmtst8xi16: 796; CHECK-SD: // %bb.0: 797; CHECK-SD-NEXT: cmtst v0.8h, v0.8h, v1.8h 798; CHECK-SD-NEXT: ret 799; 800; CHECK-GI-LABEL: cmtst8xi16: 801; CHECK-GI: // %bb.0: 802; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 803; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0 804; CHECK-GI-NEXT: mvn v0.16b, v0.16b 805; CHECK-GI-NEXT: ret 806 %tmp3 = and <8 x i16> %A, %B 807 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer 808 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16> 809 ret <8 x i16> %tmp5 810} 811 812define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) { 813; CHECK-SD-LABEL: cmtst2xi32: 814; CHECK-SD: // %bb.0: 815; CHECK-SD-NEXT: cmtst v0.2s, v0.2s, v1.2s 816; CHECK-SD-NEXT: ret 817; 818; CHECK-GI-LABEL: cmtst2xi32: 819; CHECK-GI: // %bb.0: 820; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b 821; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, #0 822; CHECK-GI-NEXT: mvn v0.8b, v0.8b 823; CHECK-GI-NEXT: ret 824 %tmp3 = and <2 x i32> %A, %B 825 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer 826 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32> 827 ret <2 x i32> %tmp5 828} 829 830define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) { 831; CHECK-SD-LABEL: cmtst4xi32: 832; CHECK-SD: // %bb.0: 833; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v1.4s 834; CHECK-SD-NEXT: ret 835; 836; CHECK-GI-LABEL: cmtst4xi32: 837; CHECK-GI: // %bb.0: 838; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 839; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0 840; CHECK-GI-NEXT: mvn v0.16b, v0.16b 841; CHECK-GI-NEXT: ret 842 %tmp3 = and <4 x i32> %A, %B 843 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer 844 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> 845 ret <4 x i32> %tmp5 846} 847 848define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) { 849; CHECK-SD-LABEL: cmtst2xi64: 850; CHECK-SD: // %bb.0: 851; CHECK-SD-NEXT: cmtst v0.2d, v0.2d, v1.2d 852; CHECK-SD-NEXT: ret 853; 854; CHECK-GI-LABEL: cmtst2xi64: 855; CHECK-GI: // %bb.0: 856; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b 857; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, #0 858; CHECK-GI-NEXT: mvn v0.16b, v0.16b 859; CHECK-GI-NEXT: ret 860 %tmp3 = and <2 x i64> %A, %B 861 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer 862 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64> 863 ret <2 x i64> %tmp5 864} 865 866 867 868define <8 x i8> @cmeqz8xi8(<8 x i8> %A) { 869; CHECK-LABEL: cmeqz8xi8: 870; CHECK: // %bb.0: 871; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 872; CHECK-NEXT: ret 873 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer 874 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 875 ret <8 x i8> %tmp4 876} 877 878define <16 x i8> @cmeqz16xi8(<16 x i8> %A) { 879; CHECK-LABEL: cmeqz16xi8: 880; CHECK: // %bb.0: 881; CHECK-NEXT: cmeq v0.16b, v0.16b, #0 882; CHECK-NEXT: ret 883 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer 884 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 885 ret <16 x i8> %tmp4 886} 887 888define <4 x i16> @cmeqz4xi16(<4 x i16> %A) { 889; CHECK-LABEL: cmeqz4xi16: 890; CHECK: // %bb.0: 891; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 892; CHECK-NEXT: ret 893 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer 894 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 895 ret <4 x i16> %tmp4 896} 897 898define <8 x i16> @cmeqz8xi16(<8 x i16> %A) { 899; CHECK-LABEL: cmeqz8xi16: 900; CHECK: // %bb.0: 901; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 902; CHECK-NEXT: ret 903 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer 904 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 905 ret <8 x i16> %tmp4 906} 907 908define <2 x i32> @cmeqz2xi32(<2 x i32> %A) { 909; CHECK-LABEL: cmeqz2xi32: 910; CHECK: // %bb.0: 911; CHECK-NEXT: cmeq v0.2s, v0.2s, #0 912; CHECK-NEXT: ret 913 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer 914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 915 ret <2 x i32> %tmp4 916} 917 918define <4 x i32> @cmeqz4xi32(<4 x i32> %A) { 919; CHECK-LABEL: cmeqz4xi32: 920; CHECK: // %bb.0: 921; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 922; CHECK-NEXT: ret 923 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer 924 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 925 ret <4 x i32> %tmp4 926} 927 928define <2 x i64> @cmeqz2xi64(<2 x i64> %A) { 929; CHECK-LABEL: cmeqz2xi64: 930; CHECK: // %bb.0: 931; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 932; CHECK-NEXT: ret 933 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer 934 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 935 ret <2 x i64> %tmp4 936} 937 938 939define <8 x i8> @cmgez8xi8(<8 x i8> %A) { 940; CHECK-LABEL: cmgez8xi8: 941; CHECK: // %bb.0: 942; CHECK-NEXT: cmge v0.8b, v0.8b, #0 943; CHECK-NEXT: ret 944 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer 945 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 946 ret <8 x i8> %tmp4 947} 948 949define <16 x i8> @cmgez16xi8(<16 x i8> %A) { 950; CHECK-LABEL: cmgez16xi8: 951; CHECK: // %bb.0: 952; CHECK-NEXT: cmge v0.16b, v0.16b, #0 953; CHECK-NEXT: ret 954 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer 955 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 956 ret <16 x i8> %tmp4 957} 958 959define <4 x i16> @cmgez4xi16(<4 x i16> %A) { 960; CHECK-LABEL: cmgez4xi16: 961; CHECK: // %bb.0: 962; CHECK-NEXT: cmge v0.4h, v0.4h, #0 963; CHECK-NEXT: ret 964 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer 965 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 966 ret <4 x i16> %tmp4 967} 968 969define <8 x i16> @cmgez8xi16(<8 x i16> %A) { 970; CHECK-LABEL: cmgez8xi16: 971; CHECK: // %bb.0: 972; CHECK-NEXT: cmge v0.8h, v0.8h, #0 973; CHECK-NEXT: ret 974 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer 975 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 976 ret <8 x i16> %tmp4 977} 978 979define <2 x i32> @cmgez2xi32(<2 x i32> %A) { 980; CHECK-LABEL: cmgez2xi32: 981; CHECK: // %bb.0: 982; CHECK-NEXT: cmge v0.2s, v0.2s, #0 983; CHECK-NEXT: ret 984 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer 985 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 986 ret <2 x i32> %tmp4 987} 988 989define <4 x i32> @cmgez4xi32(<4 x i32> %A) { 990; CHECK-LABEL: cmgez4xi32: 991; CHECK: // %bb.0: 992; CHECK-NEXT: cmge v0.4s, v0.4s, #0 993; CHECK-NEXT: ret 994 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer 995 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 996 ret <4 x i32> %tmp4 997} 998 999define <2 x i64> @cmgez2xi64(<2 x i64> %A) { 1000; CHECK-LABEL: cmgez2xi64: 1001; CHECK: // %bb.0: 1002; CHECK-NEXT: cmge v0.2d, v0.2d, #0 1003; CHECK-NEXT: ret 1004 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer 1005 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1006 ret <2 x i64> %tmp4 1007} 1008 1009 1010define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) { 1011; CHECK-SD-LABEL: cmgez8xi8_alt: 1012; CHECK-SD: // %bb.0: 1013; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0 1014; CHECK-SD-NEXT: ret 1015; 1016; CHECK-GI-LABEL: cmgez8xi8_alt: 1017; CHECK-GI: // %bb.0: 1018; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7 1019; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1020; CHECK-GI-NEXT: ret 1021 %sign = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 1022 %not = xor <8 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 1023 ret <8 x i8> %not 1024} 1025 1026define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) { 1027; CHECK-SD-LABEL: cmgez16xi8_alt: 1028; CHECK-SD: // %bb.0: 1029; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0 1030; CHECK-SD-NEXT: ret 1031; 1032; CHECK-GI-LABEL: cmgez16xi8_alt: 1033; CHECK-GI: // %bb.0: 1034; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7 1035; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1036; CHECK-GI-NEXT: ret 1037 %sign = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 1038 %not = xor <16 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 1039 ret <16 x i8> %not 1040} 1041 1042define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) { 1043; CHECK-SD-LABEL: cmgez4xi16_alt: 1044; CHECK-SD: // %bb.0: 1045; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0 1046; CHECK-SD-NEXT: ret 1047; 1048; CHECK-GI-LABEL: cmgez4xi16_alt: 1049; CHECK-GI: // %bb.0: 1050; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15 1051; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1052; CHECK-GI-NEXT: ret 1053 %sign = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15> 1054 %not = xor <4 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1> 1055 ret <4 x i16> %not 1056} 1057 1058define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) { 1059; CHECK-SD-LABEL: cmgez8xi16_alt: 1060; CHECK-SD: // %bb.0: 1061; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0 1062; CHECK-SD-NEXT: ret 1063; 1064; CHECK-GI-LABEL: cmgez8xi16_alt: 1065; CHECK-GI: // %bb.0: 1066; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15 1067; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1068; CHECK-GI-NEXT: ret 1069 %sign = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 1070 %not = xor <8 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 1071 ret <8 x i16> %not 1072} 1073 1074define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) { 1075; CHECK-SD-LABEL: cmgez2xi32_alt: 1076; CHECK-SD: // %bb.0: 1077; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0 1078; CHECK-SD-NEXT: ret 1079; 1080; CHECK-GI-LABEL: cmgez2xi32_alt: 1081; CHECK-GI: // %bb.0: 1082; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31 1083; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1084; CHECK-GI-NEXT: ret 1085 %sign = ashr <2 x i32> %A, <i32 31, i32 31> 1086 %not = xor <2 x i32> %sign, <i32 -1, i32 -1> 1087 ret <2 x i32> %not 1088} 1089 1090define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) { 1091; CHECK-SD-LABEL: cmgez4xi32_alt: 1092; CHECK-SD: // %bb.0: 1093; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0 1094; CHECK-SD-NEXT: ret 1095; 1096; CHECK-GI-LABEL: cmgez4xi32_alt: 1097; CHECK-GI: // %bb.0: 1098; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31 1099; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1100; CHECK-GI-NEXT: ret 1101 %sign = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31> 1102 %not = xor <4 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1> 1103 ret <4 x i32> %not 1104} 1105 1106define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) { 1107; CHECK-SD-LABEL: cmgez2xi64_alt: 1108; CHECK-SD: // %bb.0: 1109; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0 1110; CHECK-SD-NEXT: ret 1111; 1112; CHECK-GI-LABEL: cmgez2xi64_alt: 1113; CHECK-GI: // %bb.0: 1114; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63 1115; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1116; CHECK-GI-NEXT: ret 1117 %sign = ashr <2 x i64> %A, <i64 63, i64 63> 1118 %not = xor <2 x i64> %sign, <i64 -1, i64 -1> 1119 ret <2 x i64> %not 1120} 1121 1122define <8 x i8> @cmgez8xi8_alt2(<8 x i8> %A) { 1123; CHECK-SD-LABEL: cmgez8xi8_alt2: 1124; CHECK-SD: // %bb.0: 1125; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0 1126; CHECK-SD-NEXT: ret 1127; 1128; CHECK-GI-LABEL: cmgez8xi8_alt2: 1129; CHECK-GI: // %bb.0: 1130; CHECK-GI-NEXT: movi d1, #0xffffffffffffffff 1131; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b 1132; CHECK-GI-NEXT: ret 1133 %tmp3 = icmp sgt <8 x i8> %A, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 1134 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1135 ret <8 x i8> %tmp4 1136} 1137 1138define <16 x i8> @cmgez16xi8_alt2(<16 x i8> %A) { 1139; CHECK-SD-LABEL: cmgez16xi8_alt2: 1140; CHECK-SD: // %bb.0: 1141; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0 1142; CHECK-SD-NEXT: ret 1143; 1144; CHECK-GI-LABEL: cmgez16xi8_alt2: 1145; CHECK-GI: // %bb.0: 1146; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff 1147; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b 1148; CHECK-GI-NEXT: ret 1149 %tmp3 = icmp sgt <16 x i8> %A, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 1150 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1151 ret <16 x i8> %tmp4 1152} 1153 1154define <4 x i16> @cmgez4xi16_alt2(<4 x i16> %A) { 1155; CHECK-SD-LABEL: cmgez4xi16_alt2: 1156; CHECK-SD: // %bb.0: 1157; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0 1158; CHECK-SD-NEXT: ret 1159; 1160; CHECK-GI-LABEL: cmgez4xi16_alt2: 1161; CHECK-GI: // %bb.0: 1162; CHECK-GI-NEXT: movi d1, #0xffffffffffffffff 1163; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h 1164; CHECK-GI-NEXT: ret 1165 %tmp3 = icmp sgt <4 x i16> %A, <i16 -1, i16 -1, i16 -1, i16 -1> 1166 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1167 ret <4 x i16> %tmp4 1168} 1169 1170define <8 x i16> @cmgez8xi16_alt2(<8 x i16> %A) { 1171; CHECK-SD-LABEL: cmgez8xi16_alt2: 1172; CHECK-SD: // %bb.0: 1173; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0 1174; CHECK-SD-NEXT: ret 1175; 1176; CHECK-GI-LABEL: cmgez8xi16_alt2: 1177; CHECK-GI: // %bb.0: 1178; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff 1179; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h 1180; CHECK-GI-NEXT: ret 1181 %tmp3 = icmp sgt <8 x i16> %A, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 1182 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1183 ret <8 x i16> %tmp4 1184} 1185 1186define <2 x i32> @cmgez2xi32_alt2(<2 x i32> %A) { 1187; CHECK-SD-LABEL: cmgez2xi32_alt2: 1188; CHECK-SD: // %bb.0: 1189; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0 1190; CHECK-SD-NEXT: ret 1191; 1192; CHECK-GI-LABEL: cmgez2xi32_alt2: 1193; CHECK-GI: // %bb.0: 1194; CHECK-GI-NEXT: movi d1, #0xffffffffffffffff 1195; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s 1196; CHECK-GI-NEXT: ret 1197 %tmp3 = icmp sgt <2 x i32> %A, <i32 -1, i32 -1> 1198 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1199 ret <2 x i32> %tmp4 1200} 1201 1202define <4 x i32> @cmgez4xi32_alt2(<4 x i32> %A) { 1203; CHECK-SD-LABEL: cmgez4xi32_alt2: 1204; CHECK-SD: // %bb.0: 1205; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0 1206; CHECK-SD-NEXT: ret 1207; 1208; CHECK-GI-LABEL: cmgez4xi32_alt2: 1209; CHECK-GI: // %bb.0: 1210; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff 1211; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s 1212; CHECK-GI-NEXT: ret 1213 %tmp3 = icmp sgt <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1> 1214 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1215 ret <4 x i32> %tmp4 1216} 1217 1218define <2 x i64> @cmgez2xi64_alt2(<2 x i64> %A) { 1219; CHECK-SD-LABEL: cmgez2xi64_alt2: 1220; CHECK-SD: // %bb.0: 1221; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0 1222; CHECK-SD-NEXT: ret 1223; 1224; CHECK-GI-LABEL: cmgez2xi64_alt2: 1225; CHECK-GI: // %bb.0: 1226; CHECK-GI-NEXT: movi v1.2d, #0xffffffffffffffff 1227; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d 1228; CHECK-GI-NEXT: ret 1229 %tmp3 = icmp sgt <2 x i64> %A, <i64 -1, i64 -1> 1230 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1231 ret <2 x i64> %tmp4 1232} 1233 1234 1235define <8 x i8> @cmgtz8xi8(<8 x i8> %A) { 1236; CHECK-LABEL: cmgtz8xi8: 1237; CHECK: // %bb.0: 1238; CHECK-NEXT: cmgt v0.8b, v0.8b, #0 1239; CHECK-NEXT: ret 1240 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer 1241 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1242 ret <8 x i8> %tmp4 1243} 1244 1245define <16 x i8> @cmgtz16xi8(<16 x i8> %A) { 1246; CHECK-LABEL: cmgtz16xi8: 1247; CHECK: // %bb.0: 1248; CHECK-NEXT: cmgt v0.16b, v0.16b, #0 1249; CHECK-NEXT: ret 1250 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer 1251 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1252 ret <16 x i8> %tmp4 1253} 1254 1255define <4 x i16> @cmgtz4xi16(<4 x i16> %A) { 1256; CHECK-LABEL: cmgtz4xi16: 1257; CHECK: // %bb.0: 1258; CHECK-NEXT: cmgt v0.4h, v0.4h, #0 1259; CHECK-NEXT: ret 1260 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer 1261 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1262 ret <4 x i16> %tmp4 1263} 1264 1265define <8 x i16> @cmgtz8xi16(<8 x i16> %A) { 1266; CHECK-LABEL: cmgtz8xi16: 1267; CHECK: // %bb.0: 1268; CHECK-NEXT: cmgt v0.8h, v0.8h, #0 1269; CHECK-NEXT: ret 1270 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer 1271 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1272 ret <8 x i16> %tmp4 1273} 1274 1275define <2 x i32> @cmgtz2xi32(<2 x i32> %A) { 1276; CHECK-LABEL: cmgtz2xi32: 1277; CHECK: // %bb.0: 1278; CHECK-NEXT: cmgt v0.2s, v0.2s, #0 1279; CHECK-NEXT: ret 1280 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer 1281 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1282 ret <2 x i32> %tmp4 1283} 1284 1285define <4 x i32> @cmgtz4xi32(<4 x i32> %A) { 1286; CHECK-LABEL: cmgtz4xi32: 1287; CHECK: // %bb.0: 1288; CHECK-NEXT: cmgt v0.4s, v0.4s, #0 1289; CHECK-NEXT: ret 1290 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer 1291 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1292 ret <4 x i32> %tmp4 1293} 1294 1295define <2 x i64> @cmgtz2xi64(<2 x i64> %A) { 1296; CHECK-LABEL: cmgtz2xi64: 1297; CHECK: // %bb.0: 1298; CHECK-NEXT: cmgt v0.2d, v0.2d, #0 1299; CHECK-NEXT: ret 1300 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer 1301 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1302 ret <2 x i64> %tmp4 1303} 1304 1305define <8 x i8> @cmlez8xi8(<8 x i8> %A) { 1306; CHECK-LABEL: cmlez8xi8: 1307; CHECK: // %bb.0: 1308; CHECK-NEXT: cmle v0.8b, v0.8b, #0 1309; CHECK-NEXT: ret 1310 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer 1311 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1312 ret <8 x i8> %tmp4 1313} 1314 1315define <16 x i8> @cmlez16xi8(<16 x i8> %A) { 1316; CHECK-LABEL: cmlez16xi8: 1317; CHECK: // %bb.0: 1318; CHECK-NEXT: cmle v0.16b, v0.16b, #0 1319; CHECK-NEXT: ret 1320 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer 1321 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1322 ret <16 x i8> %tmp4 1323} 1324 1325define <4 x i16> @cmlez4xi16(<4 x i16> %A) { 1326; CHECK-LABEL: cmlez4xi16: 1327; CHECK: // %bb.0: 1328; CHECK-NEXT: cmle v0.4h, v0.4h, #0 1329; CHECK-NEXT: ret 1330 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer 1331 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1332 ret <4 x i16> %tmp4 1333} 1334 1335define <8 x i16> @cmlez8xi16(<8 x i16> %A) { 1336; CHECK-LABEL: cmlez8xi16: 1337; CHECK: // %bb.0: 1338; CHECK-NEXT: cmle v0.8h, v0.8h, #0 1339; CHECK-NEXT: ret 1340 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer 1341 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1342 ret <8 x i16> %tmp4 1343} 1344 1345define <2 x i32> @cmlez2xi32(<2 x i32> %A) { 1346; CHECK-LABEL: cmlez2xi32: 1347; CHECK: // %bb.0: 1348; CHECK-NEXT: cmle v0.2s, v0.2s, #0 1349; CHECK-NEXT: ret 1350 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer 1351 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1352 ret <2 x i32> %tmp4 1353} 1354 1355define <4 x i32> @cmlez4xi32(<4 x i32> %A) { 1356; CHECK-LABEL: cmlez4xi32: 1357; CHECK: // %bb.0: 1358; CHECK-NEXT: cmle v0.4s, v0.4s, #0 1359; CHECK-NEXT: ret 1360 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer 1361 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1362 ret <4 x i32> %tmp4 1363} 1364 1365define <2 x i64> @cmlez2xi64(<2 x i64> %A) { 1366; CHECK-LABEL: cmlez2xi64: 1367; CHECK: // %bb.0: 1368; CHECK-NEXT: cmle v0.2d, v0.2d, #0 1369; CHECK-NEXT: ret 1370 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer 1371 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1372 ret <2 x i64> %tmp4 1373} 1374 1375define <8 x i8> @cmlez8xi8_alt(<8 x i8> %A) { 1376; CHECK-SD-LABEL: cmlez8xi8_alt: 1377; CHECK-SD: // %bb.0: 1378; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0 1379; CHECK-SD-NEXT: ret 1380; 1381; CHECK-GI-LABEL: cmlez8xi8_alt: 1382; CHECK-GI: // %bb.0: 1383; CHECK-GI-NEXT: movi v1.8b, #1 1384; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b 1385; CHECK-GI-NEXT: ret 1386 %tmp3 = icmp slt <8 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1387 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1388 ret <8 x i8> %tmp4 1389} 1390 1391define <16 x i8> @cmlez16xi8_alt(<16 x i8> %A) { 1392; CHECK-SD-LABEL: cmlez16xi8_alt: 1393; CHECK-SD: // %bb.0: 1394; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0 1395; CHECK-SD-NEXT: ret 1396; 1397; CHECK-GI-LABEL: cmlez16xi8_alt: 1398; CHECK-GI: // %bb.0: 1399; CHECK-GI-NEXT: movi v1.16b, #1 1400; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b 1401; CHECK-GI-NEXT: ret 1402 %tmp3 = icmp slt <16 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1403 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1404 ret <16 x i8> %tmp4 1405} 1406 1407define <4 x i16> @cmlez4xi16_alt(<4 x i16> %A) { 1408; CHECK-SD-LABEL: cmlez4xi16_alt: 1409; CHECK-SD: // %bb.0: 1410; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0 1411; CHECK-SD-NEXT: ret 1412; 1413; CHECK-GI-LABEL: cmlez4xi16_alt: 1414; CHECK-GI: // %bb.0: 1415; CHECK-GI-NEXT: movi v1.4h, #1 1416; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h 1417; CHECK-GI-NEXT: ret 1418 %tmp3 = icmp slt <4 x i16> %A, <i16 1, i16 1, i16 1, i16 1> 1419 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1420 ret <4 x i16> %tmp4 1421} 1422 1423define <8 x i16> @cmlez8xi16_alt(<8 x i16> %A) { 1424; CHECK-SD-LABEL: cmlez8xi16_alt: 1425; CHECK-SD: // %bb.0: 1426; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0 1427; CHECK-SD-NEXT: ret 1428; 1429; CHECK-GI-LABEL: cmlez8xi16_alt: 1430; CHECK-GI: // %bb.0: 1431; CHECK-GI-NEXT: movi v1.8h, #1 1432; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h 1433; CHECK-GI-NEXT: ret 1434 %tmp3 = icmp slt <8 x i16> %A, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 1435 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1436 ret <8 x i16> %tmp4 1437} 1438 1439define <2 x i32> @cmlez2xi32_alt(<2 x i32> %A) { 1440; CHECK-SD-LABEL: cmlez2xi32_alt: 1441; CHECK-SD: // %bb.0: 1442; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0 1443; CHECK-SD-NEXT: ret 1444; 1445; CHECK-GI-LABEL: cmlez2xi32_alt: 1446; CHECK-GI: // %bb.0: 1447; CHECK-GI-NEXT: movi v1.2s, #1 1448; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s 1449; CHECK-GI-NEXT: ret 1450 %tmp3 = icmp slt <2 x i32> %A, <i32 1, i32 1> 1451 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1452 ret <2 x i32> %tmp4 1453} 1454 1455define <4 x i32> @cmlez4xi32_alt(<4 x i32> %A) { 1456; CHECK-SD-LABEL: cmlez4xi32_alt: 1457; CHECK-SD: // %bb.0: 1458; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0 1459; CHECK-SD-NEXT: ret 1460; 1461; CHECK-GI-LABEL: cmlez4xi32_alt: 1462; CHECK-GI: // %bb.0: 1463; CHECK-GI-NEXT: movi v1.4s, #1 1464; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s 1465; CHECK-GI-NEXT: ret 1466 %tmp3 = icmp slt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1> 1467 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1468 ret <4 x i32> %tmp4 1469} 1470 1471define <2 x i64> @cmlez2xi64_alt(<2 x i64> %A) { 1472; CHECK-SD-LABEL: cmlez2xi64_alt: 1473; CHECK-SD: // %bb.0: 1474; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0 1475; CHECK-SD-NEXT: ret 1476; 1477; CHECK-GI-LABEL: cmlez2xi64_alt: 1478; CHECK-GI: // %bb.0: 1479; CHECK-GI-NEXT: adrp x8, .LCPI125_0 1480; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0] 1481; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d 1482; CHECK-GI-NEXT: ret 1483 %tmp3 = icmp slt <2 x i64> %A, <i64 1, i64 1> 1484 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1485 ret <2 x i64> %tmp4 1486} 1487 1488define <8 x i8> @cmltz8xi8(<8 x i8> %A) { 1489; CHECK-LABEL: cmltz8xi8: 1490; CHECK: // %bb.0: 1491; CHECK-NEXT: cmlt v0.8b, v0.8b, #0 1492; CHECK-NEXT: ret 1493 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer 1494 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1495 ret <8 x i8> %tmp4 1496} 1497 1498define <16 x i8> @cmltz16xi8(<16 x i8> %A) { 1499; CHECK-LABEL: cmltz16xi8: 1500; CHECK: // %bb.0: 1501; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 1502; CHECK-NEXT: ret 1503 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer 1504 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1505 ret <16 x i8> %tmp4 1506} 1507 1508define <4 x i16> @cmltz4xi16(<4 x i16> %A) { 1509; CHECK-LABEL: cmltz4xi16: 1510; CHECK: // %bb.0: 1511; CHECK-NEXT: cmlt v0.4h, v0.4h, #0 1512; CHECK-NEXT: ret 1513 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer 1514 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1515 ret <4 x i16> %tmp4 1516} 1517 1518define <8 x i16> @cmltz8xi16(<8 x i16> %A) { 1519; CHECK-LABEL: cmltz8xi16: 1520; CHECK: // %bb.0: 1521; CHECK-NEXT: cmlt v0.8h, v0.8h, #0 1522; CHECK-NEXT: ret 1523 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer 1524 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1525 ret <8 x i16> %tmp4 1526} 1527 1528define <2 x i32> @cmltz2xi32(<2 x i32> %A) { 1529; CHECK-LABEL: cmltz2xi32: 1530; CHECK: // %bb.0: 1531; CHECK-NEXT: cmlt v0.2s, v0.2s, #0 1532; CHECK-NEXT: ret 1533 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer 1534 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1535 ret <2 x i32> %tmp4 1536} 1537 1538define <4 x i32> @cmltz4xi32(<4 x i32> %A) { 1539; CHECK-LABEL: cmltz4xi32: 1540; CHECK: // %bb.0: 1541; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 1542; CHECK-NEXT: ret 1543 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer 1544 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1545 ret <4 x i32> %tmp4 1546} 1547 1548define <2 x i64> @cmltz2xi64(<2 x i64> %A) { 1549; CHECK-LABEL: cmltz2xi64: 1550; CHECK: // %bb.0: 1551; CHECK-NEXT: cmlt v0.2d, v0.2d, #0 1552; CHECK-NEXT: ret 1553 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer 1554 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1555 ret <2 x i64> %tmp4 1556} 1557 1558define <8 x i1> @not_cmle8xi8(<8 x i8> %0) { 1559; CHECK-SD-LABEL: not_cmle8xi8: 1560; CHECK-SD: // %bb.0: 1561; CHECK-SD-NEXT: movi v1.2s, #1 1562; CHECK-SD-NEXT: cmgt v0.8b, v1.8b, v0.8b 1563; CHECK-SD-NEXT: ret 1564; 1565; CHECK-GI-LABEL: not_cmle8xi8: 1566; CHECK-GI: // %bb.0: 1567; CHECK-GI-NEXT: adrp x8, .LCPI133_0 1568; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0] 1569; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b 1570; CHECK-GI-NEXT: ret 1571 %cmp.i = icmp slt <8 x i8> %0, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0> 1572 ret <8 x i1> %cmp.i 1573} 1574 1575define <4 x i1> @not_cmle16xi8(<4 x i32> %0) { 1576; CHECK-SD-LABEL: not_cmle16xi8: 1577; CHECK-SD: // %bb.0: // %entry 1578; CHECK-SD-NEXT: movi v1.8h, #1 1579; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s 1580; CHECK-SD-NEXT: xtn v0.4h, v0.4s 1581; CHECK-SD-NEXT: ret 1582; 1583; CHECK-GI-LABEL: not_cmle16xi8: 1584; CHECK-GI: // %bb.0: // %entry 1585; CHECK-GI-NEXT: adrp x8, .LCPI134_0 1586; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI134_0] 1587; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s 1588; CHECK-GI-NEXT: xtn v0.4h, v0.4s 1589; CHECK-GI-NEXT: ret 1590entry: 1591 %bc = bitcast <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0> to <4 x i32> 1592 %cmp.i = icmp slt <4 x i32> %0, %bc 1593 ret <4 x i1> %cmp.i 1594} 1595 1596define <8 x i8> @cmltz8xi8_alt(<8 x i8> %A) { 1597; CHECK-SD-LABEL: cmltz8xi8_alt: 1598; CHECK-SD: // %bb.0: 1599; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0 1600; CHECK-SD-NEXT: ret 1601; 1602; CHECK-GI-LABEL: cmltz8xi8_alt: 1603; CHECK-GI: // %bb.0: 1604; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7 1605; CHECK-GI-NEXT: ret 1606 %A.lobit = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 1607 ret <8 x i8> %A.lobit 1608} 1609 1610define <16 x i8> @cmltz16xi8_alt(<16 x i8> %A) { 1611; CHECK-SD-LABEL: cmltz16xi8_alt: 1612; CHECK-SD: // %bb.0: 1613; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0 1614; CHECK-SD-NEXT: ret 1615; 1616; CHECK-GI-LABEL: cmltz16xi8_alt: 1617; CHECK-GI: // %bb.0: 1618; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7 1619; CHECK-GI-NEXT: ret 1620 %A.lobit = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 1621 ret <16 x i8> %A.lobit 1622} 1623 1624define <4 x i16> @cmltz4xi16_alt(<4 x i16> %A) { 1625; CHECK-SD-LABEL: cmltz4xi16_alt: 1626; CHECK-SD: // %bb.0: 1627; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0 1628; CHECK-SD-NEXT: ret 1629; 1630; CHECK-GI-LABEL: cmltz4xi16_alt: 1631; CHECK-GI: // %bb.0: 1632; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15 1633; CHECK-GI-NEXT: ret 1634 %A.lobit = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15> 1635 ret <4 x i16> %A.lobit 1636} 1637 1638define <8 x i16> @cmltz8xi16_alt(<8 x i16> %A) { 1639; CHECK-SD-LABEL: cmltz8xi16_alt: 1640; CHECK-SD: // %bb.0: 1641; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0 1642; CHECK-SD-NEXT: ret 1643; 1644; CHECK-GI-LABEL: cmltz8xi16_alt: 1645; CHECK-GI: // %bb.0: 1646; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15 1647; CHECK-GI-NEXT: ret 1648 %A.lobit = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 1649 ret <8 x i16> %A.lobit 1650} 1651 1652define <2 x i32> @cmltz2xi32_alt(<2 x i32> %A) { 1653; CHECK-SD-LABEL: cmltz2xi32_alt: 1654; CHECK-SD: // %bb.0: 1655; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0 1656; CHECK-SD-NEXT: ret 1657; 1658; CHECK-GI-LABEL: cmltz2xi32_alt: 1659; CHECK-GI: // %bb.0: 1660; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31 1661; CHECK-GI-NEXT: ret 1662 %A.lobit = ashr <2 x i32> %A, <i32 31, i32 31> 1663 ret <2 x i32> %A.lobit 1664} 1665 1666define <4 x i32> @cmltz4xi32_alt(<4 x i32> %A) { 1667; CHECK-SD-LABEL: cmltz4xi32_alt: 1668; CHECK-SD: // %bb.0: 1669; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0 1670; CHECK-SD-NEXT: ret 1671; 1672; CHECK-GI-LABEL: cmltz4xi32_alt: 1673; CHECK-GI: // %bb.0: 1674; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31 1675; CHECK-GI-NEXT: ret 1676 %A.lobit = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31> 1677 ret <4 x i32> %A.lobit 1678} 1679 1680define <2 x i64> @cmltz2xi64_alt(<2 x i64> %A) { 1681; CHECK-SD-LABEL: cmltz2xi64_alt: 1682; CHECK-SD: // %bb.0: 1683; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0 1684; CHECK-SD-NEXT: ret 1685; 1686; CHECK-GI-LABEL: cmltz2xi64_alt: 1687; CHECK-GI: // %bb.0: 1688; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63 1689; CHECK-GI-NEXT: ret 1690 %A.lobit = ashr <2 x i64> %A, <i64 63, i64 63> 1691 ret <2 x i64> %A.lobit 1692} 1693 1694define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { 1695; CHECK-SD-LABEL: cmneqz8xi8: 1696; CHECK-SD: // %bb.0: 1697; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v0.8b 1698; CHECK-SD-NEXT: ret 1699; 1700; CHECK-GI-LABEL: cmneqz8xi8: 1701; CHECK-GI: // %bb.0: 1702; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0 1703; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1704; CHECK-GI-NEXT: ret 1705 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer 1706 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1707 ret <8 x i8> %tmp4 1708} 1709 1710define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { 1711; CHECK-SD-LABEL: cmneqz16xi8: 1712; CHECK-SD: // %bb.0: 1713; CHECK-SD-NEXT: cmtst v0.16b, v0.16b, v0.16b 1714; CHECK-SD-NEXT: ret 1715; 1716; CHECK-GI-LABEL: cmneqz16xi8: 1717; CHECK-GI: // %bb.0: 1718; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, #0 1719; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1720; CHECK-GI-NEXT: ret 1721 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer 1722 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1723 ret <16 x i8> %tmp4 1724} 1725 1726define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { 1727; CHECK-SD-LABEL: cmneqz4xi16: 1728; CHECK-SD: // %bb.0: 1729; CHECK-SD-NEXT: cmtst v0.4h, v0.4h, v0.4h 1730; CHECK-SD-NEXT: ret 1731; 1732; CHECK-GI-LABEL: cmneqz4xi16: 1733; CHECK-GI: // %bb.0: 1734; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, #0 1735; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1736; CHECK-GI-NEXT: ret 1737 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer 1738 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1739 ret <4 x i16> %tmp4 1740} 1741 1742define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { 1743; CHECK-SD-LABEL: cmneqz8xi16: 1744; CHECK-SD: // %bb.0: 1745; CHECK-SD-NEXT: cmtst v0.8h, v0.8h, v0.8h 1746; CHECK-SD-NEXT: ret 1747; 1748; CHECK-GI-LABEL: cmneqz8xi16: 1749; CHECK-GI: // %bb.0: 1750; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0 1751; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1752; CHECK-GI-NEXT: ret 1753 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer 1754 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1755 ret <8 x i16> %tmp4 1756} 1757 1758define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { 1759; CHECK-SD-LABEL: cmneqz2xi32: 1760; CHECK-SD: // %bb.0: 1761; CHECK-SD-NEXT: cmtst v0.2s, v0.2s, v0.2s 1762; CHECK-SD-NEXT: ret 1763; 1764; CHECK-GI-LABEL: cmneqz2xi32: 1765; CHECK-GI: // %bb.0: 1766; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, #0 1767; CHECK-GI-NEXT: mvn v0.8b, v0.8b 1768; CHECK-GI-NEXT: ret 1769 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer 1770 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1771 ret <2 x i32> %tmp4 1772} 1773 1774define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { 1775; CHECK-SD-LABEL: cmneqz4xi32: 1776; CHECK-SD: // %bb.0: 1777; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v0.4s 1778; CHECK-SD-NEXT: ret 1779; 1780; CHECK-GI-LABEL: cmneqz4xi32: 1781; CHECK-GI: // %bb.0: 1782; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0 1783; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1784; CHECK-GI-NEXT: ret 1785 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer 1786 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1787 ret <4 x i32> %tmp4 1788} 1789 1790define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { 1791; CHECK-SD-LABEL: cmneqz2xi64: 1792; CHECK-SD: // %bb.0: 1793; CHECK-SD-NEXT: cmtst v0.2d, v0.2d, v0.2d 1794; CHECK-SD-NEXT: ret 1795; 1796; CHECK-GI-LABEL: cmneqz2xi64: 1797; CHECK-GI: // %bb.0: 1798; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, #0 1799; CHECK-GI-NEXT: mvn v0.16b, v0.16b 1800; CHECK-GI-NEXT: ret 1801 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer 1802 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1803 ret <2 x i64> %tmp4 1804} 1805 1806define <8 x i8> @cmhsz8xi8(<8 x i8> %A) { 1807; CHECK-LABEL: cmhsz8xi8: 1808; CHECK: // %bb.0: 1809; CHECK-NEXT: movi v1.8b, #2 1810; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b 1811; CHECK-NEXT: ret 1812 %tmp3 = icmp uge <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1813 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1814 ret <8 x i8> %tmp4 1815} 1816 1817define <16 x i8> @cmhsz16xi8(<16 x i8> %A) { 1818; CHECK-LABEL: cmhsz16xi8: 1819; CHECK: // %bb.0: 1820; CHECK-NEXT: movi v1.16b, #2 1821; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b 1822; CHECK-NEXT: ret 1823 %tmp3 = icmp uge <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 1824 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1825 ret <16 x i8> %tmp4 1826} 1827 1828define <4 x i16> @cmhsz4xi16(<4 x i16> %A) { 1829; CHECK-LABEL: cmhsz4xi16: 1830; CHECK: // %bb.0: 1831; CHECK-NEXT: movi v1.4h, #2 1832; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h 1833; CHECK-NEXT: ret 1834 %tmp3 = icmp uge <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2> 1835 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1836 ret <4 x i16> %tmp4 1837} 1838 1839define <8 x i16> @cmhsz8xi16(<8 x i16> %A) { 1840; CHECK-LABEL: cmhsz8xi16: 1841; CHECK: // %bb.0: 1842; CHECK-NEXT: movi v1.8h, #2 1843; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h 1844; CHECK-NEXT: ret 1845 %tmp3 = icmp uge <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 1846 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1847 ret <8 x i16> %tmp4 1848} 1849 1850define <2 x i32> @cmhsz2xi32(<2 x i32> %A) { 1851; CHECK-LABEL: cmhsz2xi32: 1852; CHECK: // %bb.0: 1853; CHECK-NEXT: movi v1.2s, #2 1854; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s 1855; CHECK-NEXT: ret 1856 %tmp3 = icmp uge <2 x i32> %A, <i32 2, i32 2> 1857 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1858 ret <2 x i32> %tmp4 1859} 1860 1861define <4 x i32> @cmhsz4xi32(<4 x i32> %A) { 1862; CHECK-LABEL: cmhsz4xi32: 1863; CHECK: // %bb.0: 1864; CHECK-NEXT: movi v1.4s, #2 1865; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s 1866; CHECK-NEXT: ret 1867 %tmp3 = icmp uge <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2> 1868 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1869 ret <4 x i32> %tmp4 1870} 1871 1872define <2 x i64> @cmhsz2xi64(<2 x i64> %A) { 1873; CHECK-SD-LABEL: cmhsz2xi64: 1874; CHECK-SD: // %bb.0: 1875; CHECK-SD-NEXT: mov w8, #2 // =0x2 1876; CHECK-SD-NEXT: dup v1.2d, x8 1877; CHECK-SD-NEXT: cmhs v0.2d, v0.2d, v1.2d 1878; CHECK-SD-NEXT: ret 1879; 1880; CHECK-GI-LABEL: cmhsz2xi64: 1881; CHECK-GI: // %bb.0: 1882; CHECK-GI-NEXT: adrp x8, .LCPI155_0 1883; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI155_0] 1884; CHECK-GI-NEXT: cmhs v0.2d, v0.2d, v1.2d 1885; CHECK-GI-NEXT: ret 1886 %tmp3 = icmp uge <2 x i64> %A, <i64 2, i64 2> 1887 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1888 ret <2 x i64> %tmp4 1889} 1890 1891 1892define <8 x i8> @cmhiz8xi8(<8 x i8> %A) { 1893; CHECK-LABEL: cmhiz8xi8: 1894; CHECK: // %bb.0: 1895; CHECK-NEXT: movi v1.8b, #1 1896; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b 1897; CHECK-NEXT: ret 1898 %tmp3 = icmp ugt <8 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1899 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1900 ret <8 x i8> %tmp4 1901} 1902 1903define <16 x i8> @cmhiz16xi8(<16 x i8> %A) { 1904; CHECK-LABEL: cmhiz16xi8: 1905; CHECK: // %bb.0: 1906; CHECK-NEXT: movi v1.16b, #1 1907; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b 1908; CHECK-NEXT: ret 1909 %tmp3 = icmp ugt <16 x i8> %A, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 1910 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1911 ret <16 x i8> %tmp4 1912} 1913 1914define <4 x i16> @cmhiz4xi16(<4 x i16> %A) { 1915; CHECK-LABEL: cmhiz4xi16: 1916; CHECK: // %bb.0: 1917; CHECK-NEXT: movi v1.4h, #1 1918; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h 1919; CHECK-NEXT: ret 1920 %tmp3 = icmp ugt <4 x i16> %A, <i16 1, i16 1, i16 1, i16 1> 1921 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1922 ret <4 x i16> %tmp4 1923} 1924 1925define <8 x i16> @cmhiz8xi16(<8 x i16> %A) { 1926; CHECK-LABEL: cmhiz8xi16: 1927; CHECK: // %bb.0: 1928; CHECK-NEXT: movi v1.8h, #1 1929; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h 1930; CHECK-NEXT: ret 1931 %tmp3 = icmp ugt <8 x i16> %A, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 1932 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1933 ret <8 x i16> %tmp4 1934} 1935 1936define <2 x i32> @cmhiz2xi32(<2 x i32> %A) { 1937; CHECK-LABEL: cmhiz2xi32: 1938; CHECK: // %bb.0: 1939; CHECK-NEXT: movi v1.2s, #1 1940; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s 1941; CHECK-NEXT: ret 1942 %tmp3 = icmp ugt <2 x i32> %A, <i32 1, i32 1> 1943 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1944 ret <2 x i32> %tmp4 1945} 1946 1947define <4 x i32> @cmhiz4xi32(<4 x i32> %A) { 1948; CHECK-LABEL: cmhiz4xi32: 1949; CHECK: // %bb.0: 1950; CHECK-NEXT: movi v1.4s, #1 1951; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s 1952; CHECK-NEXT: ret 1953 %tmp3 = icmp ugt <4 x i32> %A, <i32 1, i32 1, i32 1, i32 1> 1954 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1955 ret <4 x i32> %tmp4 1956} 1957 1958define <2 x i64> @cmhiz2xi64(<2 x i64> %A) { 1959; CHECK-SD-LABEL: cmhiz2xi64: 1960; CHECK-SD: // %bb.0: 1961; CHECK-SD-NEXT: mov w8, #1 // =0x1 1962; CHECK-SD-NEXT: dup v1.2d, x8 1963; CHECK-SD-NEXT: cmhi v0.2d, v0.2d, v1.2d 1964; CHECK-SD-NEXT: ret 1965; 1966; CHECK-GI-LABEL: cmhiz2xi64: 1967; CHECK-GI: // %bb.0: 1968; CHECK-GI-NEXT: adrp x8, .LCPI162_0 1969; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0] 1970; CHECK-GI-NEXT: cmhi v0.2d, v0.2d, v1.2d 1971; CHECK-GI-NEXT: ret 1972 %tmp3 = icmp ugt <2 x i64> %A, <i64 1, i64 1> 1973 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1974 ret <2 x i64> %tmp4 1975} 1976 1977; LS implemented as HS, so check reversed operands. 1978define <8 x i8> @cmlsz8xi8(<8 x i8> %A) { 1979; CHECK-LABEL: cmlsz8xi8: 1980; CHECK: // %bb.0: 1981; CHECK-NEXT: movi v1.2d, #0000000000000000 1982; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b 1983; CHECK-NEXT: ret 1984 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer 1985 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1986 ret <8 x i8> %tmp4 1987} 1988 1989; LS implemented as HS, so check reversed operands. 1990define <16 x i8> @cmlsz16xi8(<16 x i8> %A) { 1991; CHECK-LABEL: cmlsz16xi8: 1992; CHECK: // %bb.0: 1993; CHECK-NEXT: movi v1.2d, #0000000000000000 1994; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b 1995; CHECK-NEXT: ret 1996 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer 1997 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1998 ret <16 x i8> %tmp4 1999} 2000 2001; LS implemented as HS, so check reversed operands. 2002define <4 x i16> @cmlsz4xi16(<4 x i16> %A) { 2003; CHECK-LABEL: cmlsz4xi16: 2004; CHECK: // %bb.0: 2005; CHECK-NEXT: movi v1.2d, #0000000000000000 2006; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h 2007; CHECK-NEXT: ret 2008 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer 2009 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 2010 ret <4 x i16> %tmp4 2011} 2012 2013; LS implemented as HS, so check reversed operands. 2014define <8 x i16> @cmlsz8xi16(<8 x i16> %A) { 2015; CHECK-LABEL: cmlsz8xi16: 2016; CHECK: // %bb.0: 2017; CHECK-NEXT: movi v1.2d, #0000000000000000 2018; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h 2019; CHECK-NEXT: ret 2020 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer 2021 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 2022 ret <8 x i16> %tmp4 2023} 2024 2025; LS implemented as HS, so check reversed operands. 2026define <2 x i32> @cmlsz2xi32(<2 x i32> %A) { 2027; CHECK-LABEL: cmlsz2xi32: 2028; CHECK: // %bb.0: 2029; CHECK-NEXT: movi v1.2d, #0000000000000000 2030; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s 2031; CHECK-NEXT: ret 2032 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer 2033 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2034 ret <2 x i32> %tmp4 2035} 2036 2037; LS implemented as HS, so check reversed operands. 2038define <4 x i32> @cmlsz4xi32(<4 x i32> %A) { 2039; CHECK-LABEL: cmlsz4xi32: 2040; CHECK: // %bb.0: 2041; CHECK-NEXT: movi v1.2d, #0000000000000000 2042; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 2043; CHECK-NEXT: ret 2044 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer 2045 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2046 ret <4 x i32> %tmp4 2047} 2048 2049; LS implemented as HS, so check reversed operands. 2050define <2 x i64> @cmlsz2xi64(<2 x i64> %A) { 2051; CHECK-LABEL: cmlsz2xi64: 2052; CHECK: // %bb.0: 2053; CHECK-NEXT: movi v1.2d, #0000000000000000 2054; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d 2055; CHECK-NEXT: ret 2056 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer 2057 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2058 ret <2 x i64> %tmp4 2059} 2060 2061; LO implemented as HI, so check reversed operands. 2062define <8 x i8> @cmloz8xi8(<8 x i8> %A) { 2063; CHECK-LABEL: cmloz8xi8: 2064; CHECK: // %bb.0: 2065; CHECK-NEXT: movi v1.8b, #2 2066; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b 2067; CHECK-NEXT: ret 2068 %tmp3 = icmp ult <8 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 2069 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 2070 ret <8 x i8> %tmp4 2071} 2072 2073; LO implemented as HI, so check reversed operands. 2074define <16 x i8> @cmloz16xi8(<16 x i8> %A) { 2075; CHECK-LABEL: cmloz16xi8: 2076; CHECK: // %bb.0: 2077; CHECK-NEXT: movi v1.16b, #2 2078; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b 2079; CHECK-NEXT: ret 2080 %tmp3 = icmp ult <16 x i8> %A, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> 2081 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 2082 ret <16 x i8> %tmp4 2083} 2084 2085; LO implemented as HI, so check reversed operands. 2086define <4 x i16> @cmloz4xi16(<4 x i16> %A) { 2087; CHECK-LABEL: cmloz4xi16: 2088; CHECK: // %bb.0: 2089; CHECK-NEXT: movi v1.4h, #2 2090; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h 2091; CHECK-NEXT: ret 2092 %tmp3 = icmp ult <4 x i16> %A, <i16 2, i16 2, i16 2, i16 2> 2093 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 2094 ret <4 x i16> %tmp4 2095} 2096 2097; LO implemented as HI, so check reversed operands. 2098define <8 x i16> @cmloz8xi16(<8 x i16> %A) { 2099; CHECK-LABEL: cmloz8xi16: 2100; CHECK: // %bb.0: 2101; CHECK-NEXT: movi v1.8h, #2 2102; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h 2103; CHECK-NEXT: ret 2104 %tmp3 = icmp ult <8 x i16> %A, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> 2105 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 2106 ret <8 x i16> %tmp4 2107} 2108 2109; LO implemented as HI, so check reversed operands. 2110define <2 x i32> @cmloz2xi32(<2 x i32> %A) { 2111; CHECK-LABEL: cmloz2xi32: 2112; CHECK: // %bb.0: 2113; CHECK-NEXT: movi v1.2s, #2 2114; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s 2115; CHECK-NEXT: ret 2116 %tmp3 = icmp ult <2 x i32> %A, <i32 2, i32 2> 2117 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2118 ret <2 x i32> %tmp4 2119} 2120 2121; LO implemented as HI, so check reversed operands. 2122define <4 x i32> @cmloz4xi32(<4 x i32> %A) { 2123; CHECK-LABEL: cmloz4xi32: 2124; CHECK: // %bb.0: 2125; CHECK-NEXT: movi v1.4s, #2 2126; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s 2127; CHECK-NEXT: ret 2128 %tmp3 = icmp ult <4 x i32> %A, <i32 2, i32 2, i32 2, i32 2> 2129 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2130 ret <4 x i32> %tmp4 2131} 2132 2133; LO implemented as HI, so check reversed operands. 2134define <2 x i64> @cmloz2xi64(<2 x i64> %A) { 2135; CHECK-SD-LABEL: cmloz2xi64: 2136; CHECK-SD: // %bb.0: 2137; CHECK-SD-NEXT: mov w8, #2 // =0x2 2138; CHECK-SD-NEXT: dup v1.2d, x8 2139; CHECK-SD-NEXT: cmhi v0.2d, v1.2d, v0.2d 2140; CHECK-SD-NEXT: ret 2141; 2142; CHECK-GI-LABEL: cmloz2xi64: 2143; CHECK-GI: // %bb.0: 2144; CHECK-GI-NEXT: adrp x8, .LCPI176_0 2145; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI176_0] 2146; CHECK-GI-NEXT: cmhi v0.2d, v1.2d, v0.2d 2147; CHECK-GI-NEXT: ret 2148 %tmp3 = icmp ult <2 x i64> %A, <i64 2, i64 2> 2149 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2150 ret <2 x i64> %tmp4 2151} 2152 2153define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) { 2154; CHECK-LABEL: fcmoeq2xfloat: 2155; CHECK: // %bb.0: 2156; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s 2157; CHECK-NEXT: ret 2158 %tmp3 = fcmp oeq <2 x float> %A, %B 2159 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2160 ret <2 x i32> %tmp4 2161} 2162 2163define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) { 2164; CHECK-LABEL: fcmoeq4xfloat: 2165; CHECK: // %bb.0: 2166; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s 2167; CHECK-NEXT: ret 2168 %tmp3 = fcmp oeq <4 x float> %A, %B 2169 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2170 ret <4 x i32> %tmp4 2171} 2172define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) { 2173; CHECK-LABEL: fcmoeq2xdouble: 2174; CHECK: // %bb.0: 2175; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d 2176; CHECK-NEXT: ret 2177 %tmp3 = fcmp oeq <2 x double> %A, %B 2178 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2179 ret <2 x i64> %tmp4 2180} 2181 2182define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) { 2183; CHECK-LABEL: fcmoge2xfloat: 2184; CHECK: // %bb.0: 2185; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s 2186; CHECK-NEXT: ret 2187 %tmp3 = fcmp oge <2 x float> %A, %B 2188 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2189 ret <2 x i32> %tmp4 2190} 2191 2192define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) { 2193; CHECK-LABEL: fcmoge4xfloat: 2194; CHECK: // %bb.0: 2195; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s 2196; CHECK-NEXT: ret 2197 %tmp3 = fcmp oge <4 x float> %A, %B 2198 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2199 ret <4 x i32> %tmp4 2200} 2201define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) { 2202; CHECK-LABEL: fcmoge2xdouble: 2203; CHECK: // %bb.0: 2204; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d 2205; CHECK-NEXT: ret 2206 %tmp3 = fcmp oge <2 x double> %A, %B 2207 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2208 ret <2 x i64> %tmp4 2209} 2210 2211define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) { 2212; CHECK-LABEL: fcmogt2xfloat: 2213; CHECK: // %bb.0: 2214; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s 2215; CHECK-NEXT: ret 2216 %tmp3 = fcmp ogt <2 x float> %A, %B 2217 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2218 ret <2 x i32> %tmp4 2219} 2220 2221define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) { 2222; CHECK-LABEL: fcmogt4xfloat: 2223; CHECK: // %bb.0: 2224; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s 2225; CHECK-NEXT: ret 2226 %tmp3 = fcmp ogt <4 x float> %A, %B 2227 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2228 ret <4 x i32> %tmp4 2229} 2230define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) { 2231; CHECK-LABEL: fcmogt2xdouble: 2232; CHECK: // %bb.0: 2233; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d 2234; CHECK-NEXT: ret 2235 %tmp3 = fcmp ogt <2 x double> %A, %B 2236 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2237 ret <2 x i64> %tmp4 2238} 2239 2240; OLE implemented as OGE, so check reversed operands. 2241define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) { 2242; CHECK-LABEL: fcmole2xfloat: 2243; CHECK: // %bb.0: 2244; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s 2245; CHECK-NEXT: ret 2246 %tmp3 = fcmp ole <2 x float> %A, %B 2247 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2248 ret <2 x i32> %tmp4 2249} 2250 2251; OLE implemented as OGE, so check reversed operands. 2252define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) { 2253; CHECK-LABEL: fcmole4xfloat: 2254; CHECK: // %bb.0: 2255; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s 2256; CHECK-NEXT: ret 2257 %tmp3 = fcmp ole <4 x float> %A, %B 2258 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2259 ret <4 x i32> %tmp4 2260} 2261 2262; OLE implemented as OGE, so check reversed operands. 2263define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) { 2264; CHECK-LABEL: fcmole2xdouble: 2265; CHECK: // %bb.0: 2266; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d 2267; CHECK-NEXT: ret 2268 %tmp3 = fcmp ole <2 x double> %A, %B 2269 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2270 ret <2 x i64> %tmp4 2271} 2272 2273; OLE implemented as OGE, so check reversed operands. 2274define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) { 2275; CHECK-LABEL: fcmolt2xfloat: 2276; CHECK: // %bb.0: 2277; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2278; CHECK-NEXT: ret 2279 %tmp3 = fcmp olt <2 x float> %A, %B 2280 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2281 ret <2 x i32> %tmp4 2282} 2283 2284; OLE implemented as OGE, so check reversed operands. 2285define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) { 2286; CHECK-LABEL: fcmolt4xfloat: 2287; CHECK: // %bb.0: 2288; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2289; CHECK-NEXT: ret 2290 %tmp3 = fcmp olt <4 x float> %A, %B 2291 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2292 ret <4 x i32> %tmp4 2293} 2294 2295; OLE implemented as OGE, so check reversed operands. 2296define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) { 2297; CHECK-LABEL: fcmolt2xdouble: 2298; CHECK: // %bb.0: 2299; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2300; CHECK-NEXT: ret 2301 %tmp3 = fcmp olt <2 x double> %A, %B 2302 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2303 ret <2 x i64> %tmp4 2304} 2305 2306; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 2307define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) { 2308; CHECK-LABEL: fcmone2xfloat: 2309; CHECK: // %bb.0: 2310; CHECK-NEXT: fcmgt v2.2s, v0.2s, v1.2s 2311; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2312; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 2313; CHECK-NEXT: ret 2314 %tmp3 = fcmp one <2 x float> %A, %B 2315 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2316 ret <2 x i32> %tmp4 2317} 2318 2319; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 2320define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) { 2321; CHECK-LABEL: fcmone4xfloat: 2322; CHECK: // %bb.0: 2323; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s 2324; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2325; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2326; CHECK-NEXT: ret 2327 %tmp3 = fcmp one <4 x float> %A, %B 2328 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2329 ret <4 x i32> %tmp4 2330} 2331 2332; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 2333; todo check reversed operands 2334define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) { 2335; CHECK-LABEL: fcmone2xdouble: 2336; CHECK: // %bb.0: 2337; CHECK-NEXT: fcmgt v2.2d, v0.2d, v1.2d 2338; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2339; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2340; CHECK-NEXT: ret 2341 %tmp3 = fcmp one <2 x double> %A, %B 2342 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2343 ret <2 x i64> %tmp4 2344} 2345 2346; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 2347define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) { 2348; CHECK-LABEL: fcmord2xfloat: 2349; CHECK: // %bb.0: 2350; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s 2351; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2352; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 2353; CHECK-NEXT: ret 2354 %tmp3 = fcmp ord <2 x float> %A, %B 2355 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2356 ret <2 x i32> %tmp4 2357} 2358 2359; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 2360define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) { 2361; CHECK-LABEL: fcmord4xfloat: 2362; CHECK: // %bb.0: 2363; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s 2364; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2365; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2366; CHECK-NEXT: ret 2367 %tmp3 = fcmp ord <4 x float> %A, %B 2368 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2369 ret <4 x i32> %tmp4 2370} 2371 2372; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 2373define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) { 2374; CHECK-LABEL: fcmord2xdouble: 2375; CHECK: // %bb.0: 2376; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d 2377; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2378; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2379; CHECK-NEXT: ret 2380 %tmp3 = fcmp ord <2 x double> %A, %B 2381 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2382 ret <2 x i64> %tmp4 2383} 2384 2385 2386; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 2387define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) { 2388; CHECK-LABEL: fcmuno2xfloat: 2389; CHECK: // %bb.0: 2390; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s 2391; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2392; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 2393; CHECK-NEXT: mvn v0.8b, v0.8b 2394; CHECK-NEXT: ret 2395 %tmp3 = fcmp uno <2 x float> %A, %B 2396 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2397 ret <2 x i32> %tmp4 2398} 2399 2400; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 2401define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) { 2402; CHECK-LABEL: fcmuno4xfloat: 2403; CHECK: // %bb.0: 2404; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s 2405; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2406; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2407; CHECK-NEXT: mvn v0.16b, v0.16b 2408; CHECK-NEXT: ret 2409 %tmp3 = fcmp uno <4 x float> %A, %B 2410 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2411 ret <4 x i32> %tmp4 2412} 2413 2414; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 2415define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) { 2416; CHECK-LABEL: fcmuno2xdouble: 2417; CHECK: // %bb.0: 2418; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d 2419; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2420; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2421; CHECK-NEXT: mvn v0.16b, v0.16b 2422; CHECK-NEXT: ret 2423 %tmp3 = fcmp uno <2 x double> %A, %B 2424 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2425 ret <2 x i64> %tmp4 2426} 2427 2428; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 2429define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) { 2430; CHECK-LABEL: fcmueq2xfloat: 2431; CHECK: // %bb.0: 2432; CHECK-NEXT: fcmgt v2.2s, v0.2s, v1.2s 2433; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2434; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 2435; CHECK-NEXT: mvn v0.8b, v0.8b 2436; CHECK-NEXT: ret 2437 %tmp3 = fcmp ueq <2 x float> %A, %B 2438 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2439 ret <2 x i32> %tmp4 2440} 2441 2442; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 2443define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) { 2444; CHECK-LABEL: fcmueq4xfloat: 2445; CHECK: // %bb.0: 2446; CHECK-NEXT: fcmgt v2.4s, v0.4s, v1.4s 2447; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2448; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2449; CHECK-NEXT: mvn v0.16b, v0.16b 2450; CHECK-NEXT: ret 2451 %tmp3 = fcmp ueq <4 x float> %A, %B 2452 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2453 ret <4 x i32> %tmp4 2454} 2455 2456; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 2457define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) { 2458; CHECK-LABEL: fcmueq2xdouble: 2459; CHECK: // %bb.0: 2460; CHECK-NEXT: fcmgt v2.2d, v0.2d, v1.2d 2461; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2462; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 2463; CHECK-NEXT: mvn v0.16b, v0.16b 2464; CHECK-NEXT: ret 2465 %tmp3 = fcmp ueq <2 x double> %A, %B 2466 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2467 ret <2 x i64> %tmp4 2468} 2469 2470; UGE = ULE with swapped operands, ULE implemented as !OGT. 2471define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) { 2472; CHECK-LABEL: fcmuge2xfloat: 2473; CHECK: // %bb.0: 2474; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 2475; CHECK-NEXT: mvn v0.8b, v0.8b 2476; CHECK-NEXT: ret 2477 %tmp3 = fcmp uge <2 x float> %A, %B 2478 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2479 ret <2 x i32> %tmp4 2480} 2481 2482; UGE = ULE with swapped operands, ULE implemented as !OGT. 2483define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) { 2484; CHECK-LABEL: fcmuge4xfloat: 2485; CHECK: // %bb.0: 2486; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 2487; CHECK-NEXT: mvn v0.16b, v0.16b 2488; CHECK-NEXT: ret 2489 %tmp3 = fcmp uge <4 x float> %A, %B 2490 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2491 ret <4 x i32> %tmp4 2492} 2493 2494; UGE = ULE with swapped operands, ULE implemented as !OGT. 2495define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) { 2496; CHECK-LABEL: fcmuge2xdouble: 2497; CHECK: // %bb.0: 2498; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 2499; CHECK-NEXT: mvn v0.16b, v0.16b 2500; CHECK-NEXT: ret 2501 %tmp3 = fcmp uge <2 x double> %A, %B 2502 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2503 ret <2 x i64> %tmp4 2504} 2505 2506; UGT = ULT with swapped operands, ULT implemented as !OGE. 2507define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) { 2508; CHECK-LABEL: fcmugt2xfloat: 2509; CHECK: // %bb.0: 2510; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s 2511; CHECK-NEXT: mvn v0.8b, v0.8b 2512; CHECK-NEXT: ret 2513 %tmp3 = fcmp ugt <2 x float> %A, %B 2514 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2515 ret <2 x i32> %tmp4 2516} 2517 2518; UGT = ULT with swapped operands, ULT implemented as !OGE. 2519define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) { 2520; CHECK-LABEL: fcmugt4xfloat: 2521; CHECK: // %bb.0: 2522; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s 2523; CHECK-NEXT: mvn v0.16b, v0.16b 2524; CHECK-NEXT: ret 2525 %tmp3 = fcmp ugt <4 x float> %A, %B 2526 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2527 ret <4 x i32> %tmp4 2528} 2529 2530define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) { 2531; CHECK-LABEL: fcmugt2xdouble: 2532; CHECK: // %bb.0: 2533; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d 2534; CHECK-NEXT: mvn v0.16b, v0.16b 2535; CHECK-NEXT: ret 2536 %tmp3 = fcmp ugt <2 x double> %A, %B 2537 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2538 ret <2 x i64> %tmp4 2539} 2540 2541; ULE implemented as !OGT. 2542define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) { 2543; CHECK-LABEL: fcmule2xfloat: 2544; CHECK: // %bb.0: 2545; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s 2546; CHECK-NEXT: mvn v0.8b, v0.8b 2547; CHECK-NEXT: ret 2548 %tmp3 = fcmp ule <2 x float> %A, %B 2549 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2550 ret <2 x i32> %tmp4 2551} 2552 2553; ULE implemented as !OGT. 2554define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) { 2555; CHECK-LABEL: fcmule4xfloat: 2556; CHECK: // %bb.0: 2557; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s 2558; CHECK-NEXT: mvn v0.16b, v0.16b 2559; CHECK-NEXT: ret 2560 %tmp3 = fcmp ule <4 x float> %A, %B 2561 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2562 ret <4 x i32> %tmp4 2563} 2564 2565; ULE implemented as !OGT. 2566define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) { 2567; CHECK-LABEL: fcmule2xdouble: 2568; CHECK: // %bb.0: 2569; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d 2570; CHECK-NEXT: mvn v0.16b, v0.16b 2571; CHECK-NEXT: ret 2572 %tmp3 = fcmp ule <2 x double> %A, %B 2573 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2574 ret <2 x i64> %tmp4 2575} 2576 2577; ULT implemented as !OGE. 2578define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) { 2579; CHECK-LABEL: fcmult2xfloat: 2580; CHECK: // %bb.0: 2581; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s 2582; CHECK-NEXT: mvn v0.8b, v0.8b 2583; CHECK-NEXT: ret 2584 %tmp3 = fcmp ult <2 x float> %A, %B 2585 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2586 ret <2 x i32> %tmp4 2587} 2588 2589; ULT implemented as !OGE. 2590define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) { 2591; CHECK-LABEL: fcmult4xfloat: 2592; CHECK: // %bb.0: 2593; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s 2594; CHECK-NEXT: mvn v0.16b, v0.16b 2595; CHECK-NEXT: ret 2596 %tmp3 = fcmp ult <4 x float> %A, %B 2597 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2598 ret <4 x i32> %tmp4 2599} 2600 2601; ULT implemented as !OGE. 2602define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) { 2603; CHECK-LABEL: fcmult2xdouble: 2604; CHECK: // %bb.0: 2605; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d 2606; CHECK-NEXT: mvn v0.16b, v0.16b 2607; CHECK-NEXT: ret 2608 %tmp3 = fcmp ult <2 x double> %A, %B 2609 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2610 ret <2 x i64> %tmp4 2611} 2612 2613; UNE = !OEQ. 2614define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) { 2615; CHECK-LABEL: fcmune2xfloat: 2616; CHECK: // %bb.0: 2617; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s 2618; CHECK-NEXT: mvn v0.8b, v0.8b 2619; CHECK-NEXT: ret 2620 %tmp3 = fcmp une <2 x float> %A, %B 2621 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2622 ret <2 x i32> %tmp4 2623} 2624 2625; UNE = !OEQ. 2626define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) { 2627; CHECK-LABEL: fcmune4xfloat: 2628; CHECK: // %bb.0: 2629; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s 2630; CHECK-NEXT: mvn v0.16b, v0.16b 2631; CHECK-NEXT: ret 2632 %tmp3 = fcmp une <4 x float> %A, %B 2633 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2634 ret <4 x i32> %tmp4 2635} 2636 2637; UNE = !OEQ. 2638define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) { 2639; CHECK-LABEL: fcmune2xdouble: 2640; CHECK: // %bb.0: 2641; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d 2642; CHECK-NEXT: mvn v0.16b, v0.16b 2643; CHECK-NEXT: ret 2644 %tmp3 = fcmp une <2 x double> %A, %B 2645 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2646 ret <2 x i64> %tmp4 2647} 2648 2649define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) { 2650; CHECK-SD-LABEL: fcmal2xfloat: 2651; CHECK-SD: // %bb.0: 2652; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff 2653; CHECK-SD-NEXT: ret 2654; 2655; CHECK-GI-LABEL: fcmal2xfloat: 2656; CHECK-GI: // %bb.0: 2657; CHECK-GI-NEXT: movi v0.2s, #1 2658; CHECK-GI-NEXT: shl v0.2s, v0.2s, #31 2659; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31 2660; CHECK-GI-NEXT: ret 2661 %tmp3 = fcmp true <2 x float> %A, %B 2662 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2663 ret <2 x i32> %tmp4 2664} 2665 2666define <4 x i32> @fcmal4xfloat(<4 x float> %A, <4 x float> %B) { 2667; CHECK-SD-LABEL: fcmal4xfloat: 2668; CHECK-SD: // %bb.0: 2669; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff 2670; CHECK-SD-NEXT: ret 2671; 2672; CHECK-GI-LABEL: fcmal4xfloat: 2673; CHECK-GI: // %bb.0: 2674; CHECK-GI-NEXT: mov w8, #1 // =0x1 2675; CHECK-GI-NEXT: dup v0.2s, w8 2676; CHECK-GI-NEXT: mov v0.d[1], v0.d[0] 2677; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31 2678; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31 2679; CHECK-GI-NEXT: ret 2680 %tmp3 = fcmp true <4 x float> %A, %B 2681 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2682 ret <4 x i32> %tmp4 2683} 2684define <2 x i64> @fcmal2xdouble(<2 x double> %A, <2 x double> %B) { 2685; CHECK-SD-LABEL: fcmal2xdouble: 2686; CHECK-SD: // %bb.0: 2687; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff 2688; CHECK-SD-NEXT: ret 2689; 2690; CHECK-GI-LABEL: fcmal2xdouble: 2691; CHECK-GI: // %bb.0: 2692; CHECK-GI-NEXT: adrp x8, .LCPI221_0 2693; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI221_0] 2694; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63 2695; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63 2696; CHECK-GI-NEXT: ret 2697 %tmp3 = fcmp true <2 x double> %A, %B 2698 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2699 ret <2 x i64> %tmp4 2700} 2701 2702define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) { 2703; CHECK-LABEL: fcmnv2xfloat: 2704; CHECK: // %bb.0: 2705; CHECK-NEXT: movi v0.2d, #0000000000000000 2706; CHECK-NEXT: ret 2707 %tmp3 = fcmp false <2 x float> %A, %B 2708 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2709 ret <2 x i32> %tmp4 2710} 2711 2712define <4 x i32> @fcmnv4xfloat(<4 x float> %A, <4 x float> %B) { 2713; CHECK-SD-LABEL: fcmnv4xfloat: 2714; CHECK-SD: // %bb.0: 2715; CHECK-SD-NEXT: movi v0.2d, #0000000000000000 2716; CHECK-SD-NEXT: ret 2717; 2718; CHECK-GI-LABEL: fcmnv4xfloat: 2719; CHECK-GI: // %bb.0: 2720; CHECK-GI-NEXT: mov w8, #0 // =0x0 2721; CHECK-GI-NEXT: mov v0.s[0], w8 2722; CHECK-GI-NEXT: mov v0.s[1], w8 2723; CHECK-GI-NEXT: mov v0.d[1], v0.d[0] 2724; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31 2725; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31 2726; CHECK-GI-NEXT: ret 2727 %tmp3 = fcmp false <4 x float> %A, %B 2728 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2729 ret <4 x i32> %tmp4 2730} 2731define <2 x i64> @fcmnv2xdouble(<2 x double> %A, <2 x double> %B) { 2732; CHECK-LABEL: fcmnv2xdouble: 2733; CHECK: // %bb.0: 2734; CHECK-NEXT: movi v0.2d, #0000000000000000 2735; CHECK-NEXT: ret 2736 %tmp3 = fcmp false <2 x double> %A, %B 2737 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2738 ret <2 x i64> %tmp4 2739} 2740 2741define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) { 2742; CHECK-LABEL: fcmoeqz2xfloat: 2743; CHECK: // %bb.0: 2744; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0 2745; CHECK-NEXT: ret 2746 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer 2747 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2748 ret <2 x i32> %tmp4 2749} 2750 2751define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) { 2752; CHECK-LABEL: fcmoeqz4xfloat: 2753; CHECK: // %bb.0: 2754; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0 2755; CHECK-NEXT: ret 2756 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer 2757 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2758 ret <4 x i32> %tmp4 2759} 2760define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) { 2761; CHECK-LABEL: fcmoeqz2xdouble: 2762; CHECK: // %bb.0: 2763; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0 2764; CHECK-NEXT: ret 2765 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer 2766 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2767 ret <2 x i64> %tmp4 2768} 2769 2770 2771define <2 x i32> @fcmogez2xfloat(<2 x float> %A) { 2772; CHECK-LABEL: fcmogez2xfloat: 2773; CHECK: // %bb.0: 2774; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0 2775; CHECK-NEXT: ret 2776 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer 2777 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2778 ret <2 x i32> %tmp4 2779} 2780 2781define <4 x i32> @fcmogez4xfloat(<4 x float> %A) { 2782; CHECK-LABEL: fcmogez4xfloat: 2783; CHECK: // %bb.0: 2784; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0 2785; CHECK-NEXT: ret 2786 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer 2787 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2788 ret <4 x i32> %tmp4 2789} 2790define <2 x i64> @fcmogez2xdouble(<2 x double> %A) { 2791; CHECK-LABEL: fcmogez2xdouble: 2792; CHECK: // %bb.0: 2793; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0 2794; CHECK-NEXT: ret 2795 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer 2796 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2797 ret <2 x i64> %tmp4 2798} 2799 2800define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) { 2801; CHECK-LABEL: fcmogtz2xfloat: 2802; CHECK: // %bb.0: 2803; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0 2804; CHECK-NEXT: ret 2805 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer 2806 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2807 ret <2 x i32> %tmp4 2808} 2809 2810define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) { 2811; CHECK-LABEL: fcmogtz4xfloat: 2812; CHECK: // %bb.0: 2813; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0 2814; CHECK-NEXT: ret 2815 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer 2816 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2817 ret <4 x i32> %tmp4 2818} 2819define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) { 2820; CHECK-LABEL: fcmogtz2xdouble: 2821; CHECK: // %bb.0: 2822; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0 2823; CHECK-NEXT: ret 2824 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer 2825 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2826 ret <2 x i64> %tmp4 2827} 2828 2829define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) { 2830; CHECK-LABEL: fcmoltz2xfloat: 2831; CHECK: // %bb.0: 2832; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0 2833; CHECK-NEXT: ret 2834 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer 2835 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2836 ret <2 x i32> %tmp4 2837} 2838 2839define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) { 2840; CHECK-LABEL: fcmoltz4xfloat: 2841; CHECK: // %bb.0: 2842; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0 2843; CHECK-NEXT: ret 2844 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer 2845 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2846 ret <4 x i32> %tmp4 2847} 2848 2849define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) { 2850; CHECK-LABEL: fcmoltz2xdouble: 2851; CHECK: // %bb.0: 2852; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0 2853; CHECK-NEXT: ret 2854 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer 2855 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2856 ret <2 x i64> %tmp4 2857} 2858 2859define <2 x i32> @fcmolez2xfloat(<2 x float> %A) { 2860; CHECK-LABEL: fcmolez2xfloat: 2861; CHECK: // %bb.0: 2862; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0 2863; CHECK-NEXT: ret 2864 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer 2865 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2866 ret <2 x i32> %tmp4 2867} 2868 2869define <4 x i32> @fcmolez4xfloat(<4 x float> %A) { 2870; CHECK-LABEL: fcmolez4xfloat: 2871; CHECK: // %bb.0: 2872; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0 2873; CHECK-NEXT: ret 2874 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer 2875 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2876 ret <4 x i32> %tmp4 2877} 2878 2879define <2 x i64> @fcmolez2xdouble(<2 x double> %A) { 2880; CHECK-LABEL: fcmolez2xdouble: 2881; CHECK: // %bb.0: 2882; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0 2883; CHECK-NEXT: ret 2884 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer 2885 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2886 ret <2 x i64> %tmp4 2887} 2888 2889; ONE with zero = OLT | OGT 2890define <2 x i32> @fcmonez2xfloat(<2 x float> %A) { 2891; CHECK-LABEL: fcmonez2xfloat: 2892; CHECK: // %bb.0: 2893; CHECK-NEXT: fcmgt v1.2s, v0.2s, #0.0 2894; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0 2895; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 2896; CHECK-NEXT: ret 2897 %tmp3 = fcmp one <2 x float> %A, zeroinitializer 2898 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2899 ret <2 x i32> %tmp4 2900} 2901 2902; ONE with zero = OLT | OGT 2903define <4 x i32> @fcmonez4xfloat(<4 x float> %A) { 2904; CHECK-LABEL: fcmonez4xfloat: 2905; CHECK: // %bb.0: 2906; CHECK-NEXT: fcmgt v1.4s, v0.4s, #0.0 2907; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0 2908; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2909; CHECK-NEXT: ret 2910 %tmp3 = fcmp one <4 x float> %A, zeroinitializer 2911 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2912 ret <4 x i32> %tmp4 2913} 2914 2915; ONE with zero = OLT | OGT 2916define <2 x i64> @fcmonez2xdouble(<2 x double> %A) { 2917; CHECK-LABEL: fcmonez2xdouble: 2918; CHECK: // %bb.0: 2919; CHECK-NEXT: fcmgt v1.2d, v0.2d, #0.0 2920; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0 2921; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2922; CHECK-NEXT: ret 2923 %tmp3 = fcmp one <2 x double> %A, zeroinitializer 2924 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2925 ret <2 x i64> %tmp4 2926} 2927 2928; ORD A, zero = EQ A, A 2929define <2 x i32> @fcmordz2xfloat(<2 x float> %A) { 2930; CHECK-LABEL: fcmordz2xfloat: 2931; CHECK: // %bb.0: 2932; CHECK-NEXT: fcmeq v0.2s, v0.2s, v0.2s 2933; CHECK-NEXT: ret 2934 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer 2935 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2936 ret <2 x i32> %tmp4 2937} 2938 2939; ORD A, zero = EQ A, A 2940define <4 x i32> @fcmordz4xfloat(<4 x float> %A) { 2941; CHECK-LABEL: fcmordz4xfloat: 2942; CHECK: // %bb.0: 2943; CHECK-NEXT: fcmeq v0.4s, v0.4s, v0.4s 2944; CHECK-NEXT: ret 2945 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer 2946 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2947 ret <4 x i32> %tmp4 2948} 2949 2950; ORD A, zero = EQ A, A 2951define <2 x i64> @fcmordz2xdouble(<2 x double> %A) { 2952; CHECK-LABEL: fcmordz2xdouble: 2953; CHECK: // %bb.0: 2954; CHECK-NEXT: fcmeq v0.2d, v0.2d, v0.2d 2955; CHECK-NEXT: ret 2956 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer 2957 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2958 ret <2 x i64> %tmp4 2959} 2960 2961; UEQ with zero = !ONE = !(OLT |OGT) 2962define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) { 2963; CHECK-LABEL: fcmueqz2xfloat: 2964; CHECK: // %bb.0: 2965; CHECK-NEXT: fcmgt v1.2s, v0.2s, #0.0 2966; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0 2967; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b 2968; CHECK-NEXT: mvn v0.8b, v0.8b 2969; CHECK-NEXT: ret 2970 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer 2971 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2972 ret <2 x i32> %tmp4 2973} 2974 2975; UEQ with zero = !ONE = !(OLT |OGT) 2976define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) { 2977; CHECK-LABEL: fcmueqz4xfloat: 2978; CHECK: // %bb.0: 2979; CHECK-NEXT: fcmgt v1.4s, v0.4s, #0.0 2980; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0 2981; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2982; CHECK-NEXT: mvn v0.16b, v0.16b 2983; CHECK-NEXT: ret 2984 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer 2985 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2986 ret <4 x i32> %tmp4 2987} 2988 2989; UEQ with zero = !ONE = !(OLT |OGT) 2990define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { 2991; CHECK-LABEL: fcmueqz2xdouble: 2992; CHECK: // %bb.0: 2993; CHECK-NEXT: fcmgt v1.2d, v0.2d, #0.0 2994; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0 2995; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b 2996; CHECK-NEXT: mvn v0.16b, v0.16b 2997; CHECK-NEXT: ret 2998 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer 2999 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3000 ret <2 x i64> %tmp4 3001} 3002 3003; UGE with zero = !OLT 3004define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { 3005; CHECK-LABEL: fcmugez2xfloat: 3006; CHECK: // %bb.0: 3007; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0 3008; CHECK-NEXT: mvn v0.8b, v0.8b 3009; CHECK-NEXT: ret 3010 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer 3011 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3012 ret <2 x i32> %tmp4 3013} 3014 3015; UGE with zero = !OLT 3016define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { 3017; CHECK-LABEL: fcmugez4xfloat: 3018; CHECK: // %bb.0: 3019; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0 3020; CHECK-NEXT: mvn v0.16b, v0.16b 3021; CHECK-NEXT: ret 3022 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer 3023 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3024 ret <4 x i32> %tmp4 3025} 3026 3027; UGE with zero = !OLT 3028define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { 3029; CHECK-LABEL: fcmugez2xdouble: 3030; CHECK: // %bb.0: 3031; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0 3032; CHECK-NEXT: mvn v0.16b, v0.16b 3033; CHECK-NEXT: ret 3034 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer 3035 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3036 ret <2 x i64> %tmp4 3037} 3038 3039; UGT with zero = !OLE 3040define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { 3041; CHECK-LABEL: fcmugtz2xfloat: 3042; CHECK: // %bb.0: 3043; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0 3044; CHECK-NEXT: mvn v0.8b, v0.8b 3045; CHECK-NEXT: ret 3046 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer 3047 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3048 ret <2 x i32> %tmp4 3049} 3050 3051; UGT with zero = !OLE 3052define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { 3053; CHECK-LABEL: fcmugtz4xfloat: 3054; CHECK: // %bb.0: 3055; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0 3056; CHECK-NEXT: mvn v0.16b, v0.16b 3057; CHECK-NEXT: ret 3058 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer 3059 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3060 ret <4 x i32> %tmp4 3061} 3062 3063; UGT with zero = !OLE 3064define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { 3065; CHECK-LABEL: fcmugtz2xdouble: 3066; CHECK: // %bb.0: 3067; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0 3068; CHECK-NEXT: mvn v0.16b, v0.16b 3069; CHECK-NEXT: ret 3070 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer 3071 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3072 ret <2 x i64> %tmp4 3073} 3074 3075; ULT with zero = !OGE 3076define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { 3077; CHECK-LABEL: fcmultz2xfloat: 3078; CHECK: // %bb.0: 3079; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0 3080; CHECK-NEXT: mvn v0.8b, v0.8b 3081; CHECK-NEXT: ret 3082 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer 3083 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3084 ret <2 x i32> %tmp4 3085} 3086 3087define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { 3088; CHECK-LABEL: fcmultz4xfloat: 3089; CHECK: // %bb.0: 3090; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0 3091; CHECK-NEXT: mvn v0.16b, v0.16b 3092; CHECK-NEXT: ret 3093 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer 3094 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3095 ret <4 x i32> %tmp4 3096} 3097 3098define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { 3099; CHECK-LABEL: fcmultz2xdouble: 3100; CHECK: // %bb.0: 3101; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0 3102; CHECK-NEXT: mvn v0.16b, v0.16b 3103; CHECK-NEXT: ret 3104 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer 3105 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3106 ret <2 x i64> %tmp4 3107} 3108 3109; ULE with zero = !OGT 3110define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { 3111; CHECK-LABEL: fcmulez2xfloat: 3112; CHECK: // %bb.0: 3113; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0 3114; CHECK-NEXT: mvn v0.8b, v0.8b 3115; CHECK-NEXT: ret 3116 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer 3117 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3118 ret <2 x i32> %tmp4 3119} 3120 3121; ULE with zero = !OGT 3122define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { 3123; CHECK-LABEL: fcmulez4xfloat: 3124; CHECK: // %bb.0: 3125; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0 3126; CHECK-NEXT: mvn v0.16b, v0.16b 3127; CHECK-NEXT: ret 3128 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer 3129 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3130 ret <4 x i32> %tmp4 3131} 3132 3133; ULE with zero = !OGT 3134define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { 3135; CHECK-LABEL: fcmulez2xdouble: 3136; CHECK: // %bb.0: 3137; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0 3138; CHECK-NEXT: mvn v0.16b, v0.16b 3139; CHECK-NEXT: ret 3140 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer 3141 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3142 ret <2 x i64> %tmp4 3143} 3144 3145; UNE with zero = !OEQ with zero 3146define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { 3147; CHECK-LABEL: fcmunez2xfloat: 3148; CHECK: // %bb.0: 3149; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0 3150; CHECK-NEXT: mvn v0.8b, v0.8b 3151; CHECK-NEXT: ret 3152 %tmp3 = fcmp une <2 x float> %A, zeroinitializer 3153 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3154 ret <2 x i32> %tmp4 3155} 3156 3157; UNE with zero = !OEQ with zero 3158define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { 3159; CHECK-LABEL: fcmunez4xfloat: 3160; CHECK: // %bb.0: 3161; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0 3162; CHECK-NEXT: mvn v0.16b, v0.16b 3163; CHECK-NEXT: ret 3164 %tmp3 = fcmp une <4 x float> %A, zeroinitializer 3165 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3166 ret <4 x i32> %tmp4 3167} 3168 3169; UNE with zero = !OEQ with zero 3170define <2 x i64> @fcmunez2xdouble(<2 x double> %A) { 3171; CHECK-LABEL: fcmunez2xdouble: 3172; CHECK: // %bb.0: 3173; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0 3174; CHECK-NEXT: mvn v0.16b, v0.16b 3175; CHECK-NEXT: ret 3176 %tmp3 = fcmp une <2 x double> %A, zeroinitializer 3177 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3178 ret <2 x i64> %tmp4 3179} 3180 3181; UNO A, zero = !(ORD A, zero) = !(EQ A, A) 3182define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) { 3183; CHECK-LABEL: fcmunoz2xfloat: 3184; CHECK: // %bb.0: 3185; CHECK-NEXT: fcmeq v0.2s, v0.2s, v0.2s 3186; CHECK-NEXT: mvn v0.8b, v0.8b 3187; CHECK-NEXT: ret 3188 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer 3189 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3190 ret <2 x i32> %tmp4 3191} 3192 3193; UNO A, zero = !(ORD A, zero) = !(EQ A, A) 3194define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) { 3195; CHECK-LABEL: fcmunoz4xfloat: 3196; CHECK: // %bb.0: 3197; CHECK-NEXT: fcmeq v0.4s, v0.4s, v0.4s 3198; CHECK-NEXT: mvn v0.16b, v0.16b 3199; CHECK-NEXT: ret 3200 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer 3201 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3202 ret <4 x i32> %tmp4 3203} 3204 3205; UNO A, zero = !(ORD A, zero) = !(EQ A, A) 3206define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) { 3207; CHECK-LABEL: fcmunoz2xdouble: 3208; CHECK: // %bb.0: 3209; CHECK-NEXT: fcmeq v0.2d, v0.2d, v0.2d 3210; CHECK-NEXT: mvn v0.16b, v0.16b 3211; CHECK-NEXT: ret 3212 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer 3213 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3214 ret <2 x i64> %tmp4 3215 3216} 3217 3218define <2 x i32> @fcmoeq2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3219; CHECK-LABEL: fcmoeq2xfloat_fast: 3220; CHECK: // %bb.0: 3221; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s 3222; CHECK-NEXT: ret 3223 %tmp3 = fcmp fast oeq <2 x float> %A, %B 3224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3225 ret <2 x i32> %tmp4 3226} 3227 3228define <4 x i32> @fcmoeq4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3229; CHECK-LABEL: fcmoeq4xfloat_fast: 3230; CHECK: // %bb.0: 3231; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s 3232; CHECK-NEXT: ret 3233 %tmp3 = fcmp fast oeq <4 x float> %A, %B 3234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3235 ret <4 x i32> %tmp4 3236} 3237define <2 x i64> @fcmoeq2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3238; CHECK-LABEL: fcmoeq2xdouble_fast: 3239; CHECK: // %bb.0: 3240; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d 3241; CHECK-NEXT: ret 3242 %tmp3 = fcmp fast oeq <2 x double> %A, %B 3243 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3244 ret <2 x i64> %tmp4 3245} 3246 3247define <2 x i32> @fcmoge2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3248; CHECK-LABEL: fcmoge2xfloat_fast: 3249; CHECK: // %bb.0: 3250; CHECK-NEXT: fcmge v0.2s, v0.2s, v1.2s 3251; CHECK-NEXT: ret 3252 %tmp3 = fcmp fast oge <2 x float> %A, %B 3253 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3254 ret <2 x i32> %tmp4 3255} 3256 3257define <4 x i32> @fcmoge4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3258; CHECK-LABEL: fcmoge4xfloat_fast: 3259; CHECK: // %bb.0: 3260; CHECK-NEXT: fcmge v0.4s, v0.4s, v1.4s 3261; CHECK-NEXT: ret 3262 %tmp3 = fcmp fast oge <4 x float> %A, %B 3263 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3264 ret <4 x i32> %tmp4 3265} 3266define <2 x i64> @fcmoge2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3267; CHECK-LABEL: fcmoge2xdouble_fast: 3268; CHECK: // %bb.0: 3269; CHECK-NEXT: fcmge v0.2d, v0.2d, v1.2d 3270; CHECK-NEXT: ret 3271 %tmp3 = fcmp fast oge <2 x double> %A, %B 3272 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3273 ret <2 x i64> %tmp4 3274} 3275 3276define <2 x i32> @fcmogt2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3277; CHECK-LABEL: fcmogt2xfloat_fast: 3278; CHECK: // %bb.0: 3279; CHECK-NEXT: fcmgt v0.2s, v0.2s, v1.2s 3280; CHECK-NEXT: ret 3281 %tmp3 = fcmp fast ogt <2 x float> %A, %B 3282 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3283 ret <2 x i32> %tmp4 3284} 3285 3286define <4 x i32> @fcmogt4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3287; CHECK-LABEL: fcmogt4xfloat_fast: 3288; CHECK: // %bb.0: 3289; CHECK-NEXT: fcmgt v0.4s, v0.4s, v1.4s 3290; CHECK-NEXT: ret 3291 %tmp3 = fcmp fast ogt <4 x float> %A, %B 3292 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3293 ret <4 x i32> %tmp4 3294} 3295define <2 x i64> @fcmogt2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3296; CHECK-LABEL: fcmogt2xdouble_fast: 3297; CHECK: // %bb.0: 3298; CHECK-NEXT: fcmgt v0.2d, v0.2d, v1.2d 3299; CHECK-NEXT: ret 3300 %tmp3 = fcmp fast ogt <2 x double> %A, %B 3301 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3302 ret <2 x i64> %tmp4 3303} 3304 3305define <2 x i32> @fcmole2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3306; CHECK-LABEL: fcmole2xfloat_fast: 3307; CHECK: // %bb.0: 3308; CHECK-NEXT: fcmge v0.2s, v1.2s, v0.2s 3309; CHECK-NEXT: ret 3310 %tmp3 = fcmp fast ole <2 x float> %A, %B 3311 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3312 ret <2 x i32> %tmp4 3313} 3314 3315define <4 x i32> @fcmole4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3316; CHECK-LABEL: fcmole4xfloat_fast: 3317; CHECK: // %bb.0: 3318; CHECK-NEXT: fcmge v0.4s, v1.4s, v0.4s 3319; CHECK-NEXT: ret 3320 %tmp3 = fcmp fast ole <4 x float> %A, %B 3321 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3322 ret <4 x i32> %tmp4 3323} 3324 3325define <2 x i64> @fcmole2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3326; CHECK-LABEL: fcmole2xdouble_fast: 3327; CHECK: // %bb.0: 3328; CHECK-NEXT: fcmge v0.2d, v1.2d, v0.2d 3329; CHECK-NEXT: ret 3330 %tmp3 = fcmp fast ole <2 x double> %A, %B 3331 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3332 ret <2 x i64> %tmp4 3333} 3334 3335define <2 x i32> @fcmolt2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3336; CHECK-LABEL: fcmolt2xfloat_fast: 3337; CHECK: // %bb.0: 3338; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3339; CHECK-NEXT: ret 3340 %tmp3 = fcmp fast olt <2 x float> %A, %B 3341 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3342 ret <2 x i32> %tmp4 3343} 3344 3345define <4 x i32> @fcmolt4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3346; CHECK-LABEL: fcmolt4xfloat_fast: 3347; CHECK: // %bb.0: 3348; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3349; CHECK-NEXT: ret 3350 %tmp3 = fcmp fast olt <4 x float> %A, %B 3351 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3352 ret <4 x i32> %tmp4 3353} 3354 3355define <2 x i64> @fcmolt2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3356; CHECK-LABEL: fcmolt2xdouble_fast: 3357; CHECK: // %bb.0: 3358; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3359; CHECK-NEXT: ret 3360 %tmp3 = fcmp fast olt <2 x double> %A, %B 3361 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3362 ret <2 x i64> %tmp4 3363} 3364 3365define <2 x i32> @fcmone2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3366; CHECK-SD-LABEL: fcmone2xfloat_fast: 3367; CHECK-SD: // %bb.0: 3368; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, v1.2s 3369; CHECK-SD-NEXT: mvn v0.8b, v0.8b 3370; CHECK-SD-NEXT: ret 3371; 3372; CHECK-GI-LABEL: fcmone2xfloat_fast: 3373; CHECK-GI: // %bb.0: 3374; CHECK-GI-NEXT: fcmgt v2.2s, v0.2s, v1.2s 3375; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3376; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b 3377; CHECK-GI-NEXT: ret 3378 %tmp3 = fcmp fast one <2 x float> %A, %B 3379 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3380 ret <2 x i32> %tmp4 3381} 3382 3383define <4 x i32> @fcmone4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3384; CHECK-SD-LABEL: fcmone4xfloat_fast: 3385; CHECK-SD: // %bb.0: 3386; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s 3387; CHECK-SD-NEXT: mvn v0.16b, v0.16b 3388; CHECK-SD-NEXT: ret 3389; 3390; CHECK-GI-LABEL: fcmone4xfloat_fast: 3391; CHECK-GI: // %bb.0: 3392; CHECK-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s 3393; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3394; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 3395; CHECK-GI-NEXT: ret 3396 %tmp3 = fcmp fast one <4 x float> %A, %B 3397 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3398 ret <4 x i32> %tmp4 3399} 3400 3401define <2 x i64> @fcmone2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3402; CHECK-SD-LABEL: fcmone2xdouble_fast: 3403; CHECK-SD: // %bb.0: 3404; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v1.2d 3405; CHECK-SD-NEXT: mvn v0.16b, v0.16b 3406; CHECK-SD-NEXT: ret 3407; 3408; CHECK-GI-LABEL: fcmone2xdouble_fast: 3409; CHECK-GI: // %bb.0: 3410; CHECK-GI-NEXT: fcmgt v2.2d, v0.2d, v1.2d 3411; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3412; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 3413; CHECK-GI-NEXT: ret 3414 %tmp3 = fcmp fast one <2 x double> %A, %B 3415 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3416 ret <2 x i64> %tmp4 3417} 3418 3419define <2 x i32> @fcmord2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3420; CHECK-LABEL: fcmord2xfloat_fast: 3421; CHECK: // %bb.0: 3422; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s 3423; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3424; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 3425; CHECK-NEXT: ret 3426 %tmp3 = fcmp fast ord <2 x float> %A, %B 3427 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3428 ret <2 x i32> %tmp4 3429} 3430 3431define <4 x i32> @fcmord4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3432; CHECK-LABEL: fcmord4xfloat_fast: 3433; CHECK: // %bb.0: 3434; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s 3435; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3436; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 3437; CHECK-NEXT: ret 3438 %tmp3 = fcmp fast ord <4 x float> %A, %B 3439 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3440 ret <4 x i32> %tmp4 3441} 3442 3443define <2 x i64> @fcmord2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3444; CHECK-LABEL: fcmord2xdouble_fast: 3445; CHECK: // %bb.0: 3446; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d 3447; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3448; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 3449; CHECK-NEXT: ret 3450 %tmp3 = fcmp fast ord <2 x double> %A, %B 3451 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3452 ret <2 x i64> %tmp4 3453} 3454 3455 3456define <2 x i32> @fcmuno2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3457; CHECK-LABEL: fcmuno2xfloat_fast: 3458; CHECK: // %bb.0: 3459; CHECK-NEXT: fcmge v2.2s, v0.2s, v1.2s 3460; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3461; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 3462; CHECK-NEXT: mvn v0.8b, v0.8b 3463; CHECK-NEXT: ret 3464 %tmp3 = fcmp fast uno <2 x float> %A, %B 3465 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3466 ret <2 x i32> %tmp4 3467} 3468 3469define <4 x i32> @fcmuno4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3470; CHECK-LABEL: fcmuno4xfloat_fast: 3471; CHECK: // %bb.0: 3472; CHECK-NEXT: fcmge v2.4s, v0.4s, v1.4s 3473; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3474; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 3475; CHECK-NEXT: mvn v0.16b, v0.16b 3476; CHECK-NEXT: ret 3477 %tmp3 = fcmp fast uno <4 x float> %A, %B 3478 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3479 ret <4 x i32> %tmp4 3480} 3481 3482define <2 x i64> @fcmuno2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3483; CHECK-LABEL: fcmuno2xdouble_fast: 3484; CHECK: // %bb.0: 3485; CHECK-NEXT: fcmge v2.2d, v0.2d, v1.2d 3486; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3487; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b 3488; CHECK-NEXT: mvn v0.16b, v0.16b 3489; CHECK-NEXT: ret 3490 %tmp3 = fcmp fast uno <2 x double> %A, %B 3491 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3492 ret <2 x i64> %tmp4 3493} 3494 3495define <2 x i32> @fcmueq2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3496; CHECK-SD-LABEL: fcmueq2xfloat_fast: 3497; CHECK-SD: // %bb.0: 3498; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, v1.2s 3499; CHECK-SD-NEXT: ret 3500; 3501; CHECK-GI-LABEL: fcmueq2xfloat_fast: 3502; CHECK-GI: // %bb.0: 3503; CHECK-GI-NEXT: fcmgt v2.2s, v0.2s, v1.2s 3504; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3505; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b 3506; CHECK-GI-NEXT: mvn v0.8b, v0.8b 3507; CHECK-GI-NEXT: ret 3508 %tmp3 = fcmp fast ueq <2 x float> %A, %B 3509 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3510 ret <2 x i32> %tmp4 3511} 3512 3513define <4 x i32> @fcmueq4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3514; CHECK-SD-LABEL: fcmueq4xfloat_fast: 3515; CHECK-SD: // %bb.0: 3516; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s 3517; CHECK-SD-NEXT: ret 3518; 3519; CHECK-GI-LABEL: fcmueq4xfloat_fast: 3520; CHECK-GI: // %bb.0: 3521; CHECK-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s 3522; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3523; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 3524; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3525; CHECK-GI-NEXT: ret 3526 %tmp3 = fcmp fast ueq <4 x float> %A, %B 3527 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3528 ret <4 x i32> %tmp4 3529} 3530 3531define <2 x i64> @fcmueq2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3532; CHECK-SD-LABEL: fcmueq2xdouble_fast: 3533; CHECK-SD: // %bb.0: 3534; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v1.2d 3535; CHECK-SD-NEXT: ret 3536; 3537; CHECK-GI-LABEL: fcmueq2xdouble_fast: 3538; CHECK-GI: // %bb.0: 3539; CHECK-GI-NEXT: fcmgt v2.2d, v0.2d, v1.2d 3540; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3541; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b 3542; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3543; CHECK-GI-NEXT: ret 3544 %tmp3 = fcmp fast ueq <2 x double> %A, %B 3545 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3546 ret <2 x i64> %tmp4 3547} 3548 3549define <2 x i32> @fcmuge2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3550; CHECK-SD-LABEL: fcmuge2xfloat_fast: 3551; CHECK-SD: // %bb.0: 3552; CHECK-SD-NEXT: fcmge v0.2s, v0.2s, v1.2s 3553; CHECK-SD-NEXT: ret 3554; 3555; CHECK-GI-LABEL: fcmuge2xfloat_fast: 3556; CHECK-GI: // %bb.0: 3557; CHECK-GI-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3558; CHECK-GI-NEXT: mvn v0.8b, v0.8b 3559; CHECK-GI-NEXT: ret 3560 %tmp3 = fcmp fast uge <2 x float> %A, %B 3561 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3562 ret <2 x i32> %tmp4 3563} 3564 3565define <4 x i32> @fcmuge4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3566; CHECK-SD-LABEL: fcmuge4xfloat_fast: 3567; CHECK-SD: // %bb.0: 3568; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s 3569; CHECK-SD-NEXT: ret 3570; 3571; CHECK-GI-LABEL: fcmuge4xfloat_fast: 3572; CHECK-GI: // %bb.0: 3573; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3574; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3575; CHECK-GI-NEXT: ret 3576 %tmp3 = fcmp fast uge <4 x float> %A, %B 3577 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3578 ret <4 x i32> %tmp4 3579} 3580 3581define <2 x i64> @fcmuge2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3582; CHECK-SD-LABEL: fcmuge2xdouble_fast: 3583; CHECK-SD: // %bb.0: 3584; CHECK-SD-NEXT: fcmge v0.2d, v0.2d, v1.2d 3585; CHECK-SD-NEXT: ret 3586; 3587; CHECK-GI-LABEL: fcmuge2xdouble_fast: 3588; CHECK-GI: // %bb.0: 3589; CHECK-GI-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3590; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3591; CHECK-GI-NEXT: ret 3592 %tmp3 = fcmp fast uge <2 x double> %A, %B 3593 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3594 ret <2 x i64> %tmp4 3595} 3596 3597define <2 x i32> @fcmugt2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3598; CHECK-SD-LABEL: fcmugt2xfloat_fast: 3599; CHECK-SD: // %bb.0: 3600; CHECK-SD-NEXT: fcmgt v0.2s, v0.2s, v1.2s 3601; CHECK-SD-NEXT: ret 3602; 3603; CHECK-GI-LABEL: fcmugt2xfloat_fast: 3604; CHECK-GI: // %bb.0: 3605; CHECK-GI-NEXT: fcmge v0.2s, v1.2s, v0.2s 3606; CHECK-GI-NEXT: mvn v0.8b, v0.8b 3607; CHECK-GI-NEXT: ret 3608 %tmp3 = fcmp fast ugt <2 x float> %A, %B 3609 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3610 ret <2 x i32> %tmp4 3611} 3612 3613define <4 x i32> @fcmugt4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3614; CHECK-SD-LABEL: fcmugt4xfloat_fast: 3615; CHECK-SD: // %bb.0: 3616; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s 3617; CHECK-SD-NEXT: ret 3618; 3619; CHECK-GI-LABEL: fcmugt4xfloat_fast: 3620; CHECK-GI: // %bb.0: 3621; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s 3622; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3623; CHECK-GI-NEXT: ret 3624 %tmp3 = fcmp fast ugt <4 x float> %A, %B 3625 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3626 ret <4 x i32> %tmp4 3627} 3628 3629define <2 x i64> @fcmugt2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3630; CHECK-SD-LABEL: fcmugt2xdouble_fast: 3631; CHECK-SD: // %bb.0: 3632; CHECK-SD-NEXT: fcmgt v0.2d, v0.2d, v1.2d 3633; CHECK-SD-NEXT: ret 3634; 3635; CHECK-GI-LABEL: fcmugt2xdouble_fast: 3636; CHECK-GI: // %bb.0: 3637; CHECK-GI-NEXT: fcmge v0.2d, v1.2d, v0.2d 3638; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3639; CHECK-GI-NEXT: ret 3640 %tmp3 = fcmp fast ugt <2 x double> %A, %B 3641 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3642 ret <2 x i64> %tmp4 3643} 3644 3645define <2 x i32> @fcmule2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3646; CHECK-SD-LABEL: fcmule2xfloat_fast: 3647; CHECK-SD: // %bb.0: 3648; CHECK-SD-NEXT: fcmge v0.2s, v1.2s, v0.2s 3649; CHECK-SD-NEXT: ret 3650; 3651; CHECK-GI-LABEL: fcmule2xfloat_fast: 3652; CHECK-GI: // %bb.0: 3653; CHECK-GI-NEXT: fcmgt v0.2s, v0.2s, v1.2s 3654; CHECK-GI-NEXT: mvn v0.8b, v0.8b 3655; CHECK-GI-NEXT: ret 3656 %tmp3 = fcmp fast ule <2 x float> %A, %B 3657 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3658 ret <2 x i32> %tmp4 3659} 3660 3661define <4 x i32> @fcmule4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3662; CHECK-SD-LABEL: fcmule4xfloat_fast: 3663; CHECK-SD: // %bb.0: 3664; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s 3665; CHECK-SD-NEXT: ret 3666; 3667; CHECK-GI-LABEL: fcmule4xfloat_fast: 3668; CHECK-GI: // %bb.0: 3669; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s 3670; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3671; CHECK-GI-NEXT: ret 3672 %tmp3 = fcmp fast ule <4 x float> %A, %B 3673 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3674 ret <4 x i32> %tmp4 3675} 3676 3677define <2 x i64> @fcmule2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3678; CHECK-SD-LABEL: fcmule2xdouble_fast: 3679; CHECK-SD: // %bb.0: 3680; CHECK-SD-NEXT: fcmge v0.2d, v1.2d, v0.2d 3681; CHECK-SD-NEXT: ret 3682; 3683; CHECK-GI-LABEL: fcmule2xdouble_fast: 3684; CHECK-GI: // %bb.0: 3685; CHECK-GI-NEXT: fcmgt v0.2d, v0.2d, v1.2d 3686; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3687; CHECK-GI-NEXT: ret 3688 %tmp3 = fcmp fast ule <2 x double> %A, %B 3689 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3690 ret <2 x i64> %tmp4 3691} 3692 3693define <2 x i32> @fcmult2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3694; CHECK-SD-LABEL: fcmult2xfloat_fast: 3695; CHECK-SD: // %bb.0: 3696; CHECK-SD-NEXT: fcmgt v0.2s, v1.2s, v0.2s 3697; CHECK-SD-NEXT: ret 3698; 3699; CHECK-GI-LABEL: fcmult2xfloat_fast: 3700; CHECK-GI: // %bb.0: 3701; CHECK-GI-NEXT: fcmge v0.2s, v0.2s, v1.2s 3702; CHECK-GI-NEXT: mvn v0.8b, v0.8b 3703; CHECK-GI-NEXT: ret 3704 %tmp3 = fcmp fast ult <2 x float> %A, %B 3705 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3706 ret <2 x i32> %tmp4 3707} 3708 3709define <4 x i32> @fcmult4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3710; CHECK-SD-LABEL: fcmult4xfloat_fast: 3711; CHECK-SD: // %bb.0: 3712; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s 3713; CHECK-SD-NEXT: ret 3714; 3715; CHECK-GI-LABEL: fcmult4xfloat_fast: 3716; CHECK-GI: // %bb.0: 3717; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s 3718; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3719; CHECK-GI-NEXT: ret 3720 %tmp3 = fcmp fast ult <4 x float> %A, %B 3721 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3722 ret <4 x i32> %tmp4 3723} 3724 3725define <2 x i64> @fcmult2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3726; CHECK-SD-LABEL: fcmult2xdouble_fast: 3727; CHECK-SD: // %bb.0: 3728; CHECK-SD-NEXT: fcmgt v0.2d, v1.2d, v0.2d 3729; CHECK-SD-NEXT: ret 3730; 3731; CHECK-GI-LABEL: fcmult2xdouble_fast: 3732; CHECK-GI: // %bb.0: 3733; CHECK-GI-NEXT: fcmge v0.2d, v0.2d, v1.2d 3734; CHECK-GI-NEXT: mvn v0.16b, v0.16b 3735; CHECK-GI-NEXT: ret 3736 %tmp3 = fcmp fast ult <2 x double> %A, %B 3737 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3738 ret <2 x i64> %tmp4 3739} 3740 3741define <2 x i32> @fcmune2xfloat_fast(<2 x float> %A, <2 x float> %B) { 3742; CHECK-LABEL: fcmune2xfloat_fast: 3743; CHECK: // %bb.0: 3744; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s 3745; CHECK-NEXT: mvn v0.8b, v0.8b 3746; CHECK-NEXT: ret 3747 %tmp3 = fcmp fast une <2 x float> %A, %B 3748 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3749 ret <2 x i32> %tmp4 3750} 3751 3752define <4 x i32> @fcmune4xfloat_fast(<4 x float> %A, <4 x float> %B) { 3753; CHECK-LABEL: fcmune4xfloat_fast: 3754; CHECK: // %bb.0: 3755; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s 3756; CHECK-NEXT: mvn v0.16b, v0.16b 3757; CHECK-NEXT: ret 3758 %tmp3 = fcmp fast une <4 x float> %A, %B 3759 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3760 ret <4 x i32> %tmp4 3761} 3762 3763define <2 x i64> @fcmune2xdouble_fast(<2 x double> %A, <2 x double> %B) { 3764; CHECK-LABEL: fcmune2xdouble_fast: 3765; CHECK: // %bb.0: 3766; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d 3767; CHECK-NEXT: mvn v0.16b, v0.16b 3768; CHECK-NEXT: ret 3769 %tmp3 = fcmp fast une <2 x double> %A, %B 3770 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3771 ret <2 x i64> %tmp4 3772} 3773 3774define <2 x i32> @fcmoeqz2xfloat_fast(<2 x float> %A) { 3775; CHECK-LABEL: fcmoeqz2xfloat_fast: 3776; CHECK: // %bb.0: 3777; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0 3778; CHECK-NEXT: ret 3779 %tmp3 = fcmp fast oeq <2 x float> %A, zeroinitializer 3780 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3781 ret <2 x i32> %tmp4 3782} 3783 3784define <4 x i32> @fcmoeqz4xfloat_fast(<4 x float> %A) { 3785; CHECK-LABEL: fcmoeqz4xfloat_fast: 3786; CHECK: // %bb.0: 3787; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0 3788; CHECK-NEXT: ret 3789 %tmp3 = fcmp fast oeq <4 x float> %A, zeroinitializer 3790 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3791 ret <4 x i32> %tmp4 3792} 3793define <2 x i64> @fcmoeqz2xdouble_fast(<2 x double> %A) { 3794; CHECK-LABEL: fcmoeqz2xdouble_fast: 3795; CHECK: // %bb.0: 3796; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0 3797; CHECK-NEXT: ret 3798 %tmp3 = fcmp fast oeq <2 x double> %A, zeroinitializer 3799 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3800 ret <2 x i64> %tmp4 3801} 3802 3803 3804define <2 x i32> @fcmogez2xfloat_fast(<2 x float> %A) { 3805; CHECK-LABEL: fcmogez2xfloat_fast: 3806; CHECK: // %bb.0: 3807; CHECK-NEXT: fcmge v0.2s, v0.2s, #0.0 3808; CHECK-NEXT: ret 3809 %tmp3 = fcmp fast oge <2 x float> %A, zeroinitializer 3810 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3811 ret <2 x i32> %tmp4 3812} 3813 3814define <4 x i32> @fcmogez4xfloat_fast(<4 x float> %A) { 3815; CHECK-LABEL: fcmogez4xfloat_fast: 3816; CHECK: // %bb.0: 3817; CHECK-NEXT: fcmge v0.4s, v0.4s, #0.0 3818; CHECK-NEXT: ret 3819 %tmp3 = fcmp fast oge <4 x float> %A, zeroinitializer 3820 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3821 ret <4 x i32> %tmp4 3822} 3823define <2 x i64> @fcmogez2xdouble_fast(<2 x double> %A) { 3824; CHECK-LABEL: fcmogez2xdouble_fast: 3825; CHECK: // %bb.0: 3826; CHECK-NEXT: fcmge v0.2d, v0.2d, #0.0 3827; CHECK-NEXT: ret 3828 %tmp3 = fcmp fast oge <2 x double> %A, zeroinitializer 3829 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3830 ret <2 x i64> %tmp4 3831} 3832 3833define <2 x i32> @fcmogtz2xfloat_fast(<2 x float> %A) { 3834; CHECK-LABEL: fcmogtz2xfloat_fast: 3835; CHECK: // %bb.0: 3836; CHECK-NEXT: fcmgt v0.2s, v0.2s, #0.0 3837; CHECK-NEXT: ret 3838 %tmp3 = fcmp fast ogt <2 x float> %A, zeroinitializer 3839 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3840 ret <2 x i32> %tmp4 3841} 3842 3843define <4 x i32> @fcmogtz4xfloat_fast(<4 x float> %A) { 3844; CHECK-LABEL: fcmogtz4xfloat_fast: 3845; CHECK: // %bb.0: 3846; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0 3847; CHECK-NEXT: ret 3848 %tmp3 = fcmp fast ogt <4 x float> %A, zeroinitializer 3849 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3850 ret <4 x i32> %tmp4 3851} 3852define <2 x i64> @fcmogtz2xdouble_fast(<2 x double> %A) { 3853; CHECK-LABEL: fcmogtz2xdouble_fast: 3854; CHECK: // %bb.0: 3855; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0 3856; CHECK-NEXT: ret 3857 %tmp3 = fcmp fast ogt <2 x double> %A, zeroinitializer 3858 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3859 ret <2 x i64> %tmp4 3860} 3861 3862define <2 x i32> @fcmoltz2xfloat_fast(<2 x float> %A) { 3863; CHECK-LABEL: fcmoltz2xfloat_fast: 3864; CHECK: // %bb.0: 3865; CHECK-NEXT: fcmlt v0.2s, v0.2s, #0.0 3866; CHECK-NEXT: ret 3867 %tmp3 = fcmp fast olt <2 x float> %A, zeroinitializer 3868 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3869 ret <2 x i32> %tmp4 3870} 3871 3872define <4 x i32> @fcmoltz4xfloat_fast(<4 x float> %A) { 3873; CHECK-LABEL: fcmoltz4xfloat_fast: 3874; CHECK: // %bb.0: 3875; CHECK-NEXT: fcmlt v0.4s, v0.4s, #0.0 3876; CHECK-NEXT: ret 3877 %tmp3 = fcmp fast olt <4 x float> %A, zeroinitializer 3878 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3879 ret <4 x i32> %tmp4 3880} 3881 3882define <2 x i64> @fcmoltz2xdouble_fast(<2 x double> %A) { 3883; CHECK-LABEL: fcmoltz2xdouble_fast: 3884; CHECK: // %bb.0: 3885; CHECK-NEXT: fcmlt v0.2d, v0.2d, #0.0 3886; CHECK-NEXT: ret 3887 %tmp3 = fcmp fast olt <2 x double> %A, zeroinitializer 3888 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3889 ret <2 x i64> %tmp4 3890} 3891 3892define <2 x i32> @fcmolez2xfloat_fast(<2 x float> %A) { 3893; CHECK-LABEL: fcmolez2xfloat_fast: 3894; CHECK: // %bb.0: 3895; CHECK-NEXT: fcmle v0.2s, v0.2s, #0.0 3896; CHECK-NEXT: ret 3897 %tmp3 = fcmp fast ole <2 x float> %A, zeroinitializer 3898 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3899 ret <2 x i32> %tmp4 3900} 3901 3902define <4 x i32> @fcmolez4xfloat_fast(<4 x float> %A) { 3903; CHECK-LABEL: fcmolez4xfloat_fast: 3904; CHECK: // %bb.0: 3905; CHECK-NEXT: fcmle v0.4s, v0.4s, #0.0 3906; CHECK-NEXT: ret 3907 %tmp3 = fcmp fast ole <4 x float> %A, zeroinitializer 3908 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3909 ret <4 x i32> %tmp4 3910} 3911 3912define <2 x i64> @fcmolez2xdouble_fast(<2 x double> %A) { 3913; CHECK-LABEL: fcmolez2xdouble_fast: 3914; CHECK: // %bb.0: 3915; CHECK-NEXT: fcmle v0.2d, v0.2d, #0.0 3916; CHECK-NEXT: ret 3917 %tmp3 = fcmp fast ole <2 x double> %A, zeroinitializer 3918 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3919 ret <2 x i64> %tmp4 3920} 3921 3922define <2 x i32> @fcmonez2xfloat_fast(<2 x float> %A) { 3923; CHECK-SD-LABEL: fcmonez2xfloat_fast: 3924; CHECK-SD: // %bb.0: 3925; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, #0.0 3926; CHECK-SD-NEXT: mvn v0.8b, v0.8b 3927; CHECK-SD-NEXT: ret 3928; 3929; CHECK-GI-LABEL: fcmonez2xfloat_fast: 3930; CHECK-GI: // %bb.0: 3931; CHECK-GI-NEXT: fcmgt v1.2s, v0.2s, #0.0 3932; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0 3933; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 3934; CHECK-GI-NEXT: ret 3935 %tmp3 = fcmp fast one <2 x float> %A, zeroinitializer 3936 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3937 ret <2 x i32> %tmp4 3938} 3939 3940define <4 x i32> @fcmonez4xfloat_fast(<4 x float> %A) { 3941; CHECK-SD-LABEL: fcmonez4xfloat_fast: 3942; CHECK-SD: // %bb.0: 3943; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, #0.0 3944; CHECK-SD-NEXT: mvn v0.16b, v0.16b 3945; CHECK-SD-NEXT: ret 3946; 3947; CHECK-GI-LABEL: fcmonez4xfloat_fast: 3948; CHECK-GI: // %bb.0: 3949; CHECK-GI-NEXT: fcmgt v1.4s, v0.4s, #0.0 3950; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0 3951; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3952; CHECK-GI-NEXT: ret 3953 %tmp3 = fcmp fast one <4 x float> %A, zeroinitializer 3954 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3955 ret <4 x i32> %tmp4 3956} 3957 3958define <2 x i64> @fcmonez2xdouble_fast(<2 x double> %A) { 3959; CHECK-SD-LABEL: fcmonez2xdouble_fast: 3960; CHECK-SD: // %bb.0: 3961; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, #0.0 3962; CHECK-SD-NEXT: mvn v0.16b, v0.16b 3963; CHECK-SD-NEXT: ret 3964; 3965; CHECK-GI-LABEL: fcmonez2xdouble_fast: 3966; CHECK-GI: // %bb.0: 3967; CHECK-GI-NEXT: fcmgt v1.2d, v0.2d, #0.0 3968; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0 3969; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 3970; CHECK-GI-NEXT: ret 3971 %tmp3 = fcmp fast one <2 x double> %A, zeroinitializer 3972 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 3973 ret <2 x i64> %tmp4 3974} 3975 3976define <2 x i32> @fcmordz2xfloat_fast(<2 x float> %A) { 3977; CHECK-LABEL: fcmordz2xfloat_fast: 3978; CHECK: // %bb.0: 3979; CHECK-NEXT: fcmeq v0.2s, v0.2s, v0.2s 3980; CHECK-NEXT: ret 3981 %tmp3 = fcmp fast ord <2 x float> %A, zeroinitializer 3982 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 3983 ret <2 x i32> %tmp4 3984} 3985 3986define <4 x i32> @fcmordz4xfloat_fast(<4 x float> %A) { 3987; CHECK-LABEL: fcmordz4xfloat_fast: 3988; CHECK: // %bb.0: 3989; CHECK-NEXT: fcmeq v0.4s, v0.4s, v0.4s 3990; CHECK-NEXT: ret 3991 %tmp3 = fcmp fast ord <4 x float> %A, zeroinitializer 3992 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 3993 ret <4 x i32> %tmp4 3994} 3995 3996define <2 x i64> @fcmordz2xdouble_fast(<2 x double> %A) { 3997; CHECK-LABEL: fcmordz2xdouble_fast: 3998; CHECK: // %bb.0: 3999; CHECK-NEXT: fcmeq v0.2d, v0.2d, v0.2d 4000; CHECK-NEXT: ret 4001 %tmp3 = fcmp fast ord <2 x double> %A, zeroinitializer 4002 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4003 ret <2 x i64> %tmp4 4004} 4005 4006define <2 x i32> @fcmueqz2xfloat_fast(<2 x float> %A) { 4007; CHECK-SD-LABEL: fcmueqz2xfloat_fast: 4008; CHECK-SD: // %bb.0: 4009; CHECK-SD-NEXT: fcmeq v0.2s, v0.2s, #0.0 4010; CHECK-SD-NEXT: ret 4011; 4012; CHECK-GI-LABEL: fcmueqz2xfloat_fast: 4013; CHECK-GI: // %bb.0: 4014; CHECK-GI-NEXT: fcmgt v1.2s, v0.2s, #0.0 4015; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0 4016; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b 4017; CHECK-GI-NEXT: mvn v0.8b, v0.8b 4018; CHECK-GI-NEXT: ret 4019 %tmp3 = fcmp fast ueq <2 x float> %A, zeroinitializer 4020 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4021 ret <2 x i32> %tmp4 4022} 4023 4024define <4 x i32> @fcmueqz4xfloat_fast(<4 x float> %A) { 4025; CHECK-SD-LABEL: fcmueqz4xfloat_fast: 4026; CHECK-SD: // %bb.0: 4027; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, #0.0 4028; CHECK-SD-NEXT: ret 4029; 4030; CHECK-GI-LABEL: fcmueqz4xfloat_fast: 4031; CHECK-GI: // %bb.0: 4032; CHECK-GI-NEXT: fcmgt v1.4s, v0.4s, #0.0 4033; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0 4034; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4035; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4036; CHECK-GI-NEXT: ret 4037 %tmp3 = fcmp fast ueq <4 x float> %A, zeroinitializer 4038 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4039 ret <4 x i32> %tmp4 4040} 4041 4042define <2 x i64> @fcmueqz2xdouble_fast(<2 x double> %A) { 4043; CHECK-SD-LABEL: fcmueqz2xdouble_fast: 4044; CHECK-SD: // %bb.0: 4045; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, #0.0 4046; CHECK-SD-NEXT: ret 4047; 4048; CHECK-GI-LABEL: fcmueqz2xdouble_fast: 4049; CHECK-GI: // %bb.0: 4050; CHECK-GI-NEXT: fcmgt v1.2d, v0.2d, #0.0 4051; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0 4052; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b 4053; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4054; CHECK-GI-NEXT: ret 4055 %tmp3 = fcmp fast ueq <2 x double> %A, zeroinitializer 4056 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4057 ret <2 x i64> %tmp4 4058} 4059 4060define <2 x i32> @fcmugez2xfloat_fast(<2 x float> %A) { 4061; CHECK-SD-LABEL: fcmugez2xfloat_fast: 4062; CHECK-SD: // %bb.0: 4063; CHECK-SD-NEXT: fcmge v0.2s, v0.2s, #0.0 4064; CHECK-SD-NEXT: ret 4065; 4066; CHECK-GI-LABEL: fcmugez2xfloat_fast: 4067; CHECK-GI: // %bb.0: 4068; CHECK-GI-NEXT: fcmlt v0.2s, v0.2s, #0.0 4069; CHECK-GI-NEXT: mvn v0.8b, v0.8b 4070; CHECK-GI-NEXT: ret 4071 %tmp3 = fcmp fast uge <2 x float> %A, zeroinitializer 4072 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4073 ret <2 x i32> %tmp4 4074} 4075 4076define <4 x i32> @fcmugez4xfloat_fast(<4 x float> %A) { 4077; CHECK-SD-LABEL: fcmugez4xfloat_fast: 4078; CHECK-SD: // %bb.0: 4079; CHECK-SD-NEXT: fcmge v0.4s, v0.4s, #0.0 4080; CHECK-SD-NEXT: ret 4081; 4082; CHECK-GI-LABEL: fcmugez4xfloat_fast: 4083; CHECK-GI: // %bb.0: 4084; CHECK-GI-NEXT: fcmlt v0.4s, v0.4s, #0.0 4085; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4086; CHECK-GI-NEXT: ret 4087 %tmp3 = fcmp fast uge <4 x float> %A, zeroinitializer 4088 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4089 ret <4 x i32> %tmp4 4090} 4091 4092define <2 x i64> @fcmugez2xdouble_fast(<2 x double> %A) { 4093; CHECK-SD-LABEL: fcmugez2xdouble_fast: 4094; CHECK-SD: // %bb.0: 4095; CHECK-SD-NEXT: fcmge v0.2d, v0.2d, #0.0 4096; CHECK-SD-NEXT: ret 4097; 4098; CHECK-GI-LABEL: fcmugez2xdouble_fast: 4099; CHECK-GI: // %bb.0: 4100; CHECK-GI-NEXT: fcmlt v0.2d, v0.2d, #0.0 4101; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4102; CHECK-GI-NEXT: ret 4103 %tmp3 = fcmp fast uge <2 x double> %A, zeroinitializer 4104 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4105 ret <2 x i64> %tmp4 4106} 4107 4108define <2 x i32> @fcmugtz2xfloat_fast(<2 x float> %A) { 4109; CHECK-SD-LABEL: fcmugtz2xfloat_fast: 4110; CHECK-SD: // %bb.0: 4111; CHECK-SD-NEXT: fcmgt v0.2s, v0.2s, #0.0 4112; CHECK-SD-NEXT: ret 4113; 4114; CHECK-GI-LABEL: fcmugtz2xfloat_fast: 4115; CHECK-GI: // %bb.0: 4116; CHECK-GI-NEXT: fcmle v0.2s, v0.2s, #0.0 4117; CHECK-GI-NEXT: mvn v0.8b, v0.8b 4118; CHECK-GI-NEXT: ret 4119 %tmp3 = fcmp fast ugt <2 x float> %A, zeroinitializer 4120 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4121 ret <2 x i32> %tmp4 4122} 4123 4124define <4 x i32> @fcmugtz4xfloat_fast(<4 x float> %A) { 4125; CHECK-SD-LABEL: fcmugtz4xfloat_fast: 4126; CHECK-SD: // %bb.0: 4127; CHECK-SD-NEXT: fcmgt v0.4s, v0.4s, #0.0 4128; CHECK-SD-NEXT: ret 4129; 4130; CHECK-GI-LABEL: fcmugtz4xfloat_fast: 4131; CHECK-GI: // %bb.0: 4132; CHECK-GI-NEXT: fcmle v0.4s, v0.4s, #0.0 4133; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4134; CHECK-GI-NEXT: ret 4135 %tmp3 = fcmp fast ugt <4 x float> %A, zeroinitializer 4136 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4137 ret <4 x i32> %tmp4 4138} 4139 4140define <2 x i64> @fcmugtz2xdouble_fast(<2 x double> %A) { 4141; CHECK-SD-LABEL: fcmugtz2xdouble_fast: 4142; CHECK-SD: // %bb.0: 4143; CHECK-SD-NEXT: fcmgt v0.2d, v0.2d, #0.0 4144; CHECK-SD-NEXT: ret 4145; 4146; CHECK-GI-LABEL: fcmugtz2xdouble_fast: 4147; CHECK-GI: // %bb.0: 4148; CHECK-GI-NEXT: fcmle v0.2d, v0.2d, #0.0 4149; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4150; CHECK-GI-NEXT: ret 4151 %tmp3 = fcmp fast ugt <2 x double> %A, zeroinitializer 4152 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4153 ret <2 x i64> %tmp4 4154} 4155 4156define <2 x i32> @fcmultz2xfloat_fast(<2 x float> %A) { 4157; CHECK-SD-LABEL: fcmultz2xfloat_fast: 4158; CHECK-SD: // %bb.0: 4159; CHECK-SD-NEXT: fcmlt v0.2s, v0.2s, #0.0 4160; CHECK-SD-NEXT: ret 4161; 4162; CHECK-GI-LABEL: fcmultz2xfloat_fast: 4163; CHECK-GI: // %bb.0: 4164; CHECK-GI-NEXT: fcmge v0.2s, v0.2s, #0.0 4165; CHECK-GI-NEXT: mvn v0.8b, v0.8b 4166; CHECK-GI-NEXT: ret 4167 %tmp3 = fcmp fast ult <2 x float> %A, zeroinitializer 4168 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4169 ret <2 x i32> %tmp4 4170} 4171 4172define <4 x i32> @fcmultz4xfloat_fast(<4 x float> %A) { 4173; CHECK-SD-LABEL: fcmultz4xfloat_fast: 4174; CHECK-SD: // %bb.0: 4175; CHECK-SD-NEXT: fcmlt v0.4s, v0.4s, #0.0 4176; CHECK-SD-NEXT: ret 4177; 4178; CHECK-GI-LABEL: fcmultz4xfloat_fast: 4179; CHECK-GI: // %bb.0: 4180; CHECK-GI-NEXT: fcmge v0.4s, v0.4s, #0.0 4181; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4182; CHECK-GI-NEXT: ret 4183 %tmp3 = fcmp fast ult <4 x float> %A, zeroinitializer 4184 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4185 ret <4 x i32> %tmp4 4186} 4187 4188define <2 x i64> @fcmultz2xdouble_fast(<2 x double> %A) { 4189; CHECK-SD-LABEL: fcmultz2xdouble_fast: 4190; CHECK-SD: // %bb.0: 4191; CHECK-SD-NEXT: fcmlt v0.2d, v0.2d, #0.0 4192; CHECK-SD-NEXT: ret 4193; 4194; CHECK-GI-LABEL: fcmultz2xdouble_fast: 4195; CHECK-GI: // %bb.0: 4196; CHECK-GI-NEXT: fcmge v0.2d, v0.2d, #0.0 4197; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4198; CHECK-GI-NEXT: ret 4199 %tmp3 = fcmp fast ult <2 x double> %A, zeroinitializer 4200 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4201 ret <2 x i64> %tmp4 4202} 4203 4204; ULE with zero = !OGT 4205define <2 x i32> @fcmulez2xfloat_fast(<2 x float> %A) { 4206; CHECK-SD-LABEL: fcmulez2xfloat_fast: 4207; CHECK-SD: // %bb.0: 4208; CHECK-SD-NEXT: fcmle v0.2s, v0.2s, #0.0 4209; CHECK-SD-NEXT: ret 4210; 4211; CHECK-GI-LABEL: fcmulez2xfloat_fast: 4212; CHECK-GI: // %bb.0: 4213; CHECK-GI-NEXT: fcmgt v0.2s, v0.2s, #0.0 4214; CHECK-GI-NEXT: mvn v0.8b, v0.8b 4215; CHECK-GI-NEXT: ret 4216 %tmp3 = fcmp fast ule <2 x float> %A, zeroinitializer 4217 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4218 ret <2 x i32> %tmp4 4219} 4220 4221define <4 x i32> @fcmulez4xfloat_fast(<4 x float> %A) { 4222; CHECK-SD-LABEL: fcmulez4xfloat_fast: 4223; CHECK-SD: // %bb.0: 4224; CHECK-SD-NEXT: fcmle v0.4s, v0.4s, #0.0 4225; CHECK-SD-NEXT: ret 4226; 4227; CHECK-GI-LABEL: fcmulez4xfloat_fast: 4228; CHECK-GI: // %bb.0: 4229; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, #0.0 4230; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4231; CHECK-GI-NEXT: ret 4232 %tmp3 = fcmp fast ule <4 x float> %A, zeroinitializer 4233 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4234 ret <4 x i32> %tmp4 4235} 4236 4237define <2 x i64> @fcmulez2xdouble_fast(<2 x double> %A) { 4238; CHECK-SD-LABEL: fcmulez2xdouble_fast: 4239; CHECK-SD: // %bb.0: 4240; CHECK-SD-NEXT: fcmle v0.2d, v0.2d, #0.0 4241; CHECK-SD-NEXT: ret 4242; 4243; CHECK-GI-LABEL: fcmulez2xdouble_fast: 4244; CHECK-GI: // %bb.0: 4245; CHECK-GI-NEXT: fcmgt v0.2d, v0.2d, #0.0 4246; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4247; CHECK-GI-NEXT: ret 4248 %tmp3 = fcmp fast ule <2 x double> %A, zeroinitializer 4249 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4250 ret <2 x i64> %tmp4 4251} 4252 4253define <2 x i32> @fcmunez2xfloat_fast(<2 x float> %A) { 4254; CHECK-LABEL: fcmunez2xfloat_fast: 4255; CHECK: // %bb.0: 4256; CHECK-NEXT: fcmeq v0.2s, v0.2s, #0.0 4257; CHECK-NEXT: mvn v0.8b, v0.8b 4258; CHECK-NEXT: ret 4259 %tmp3 = fcmp fast une <2 x float> %A, zeroinitializer 4260 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4261 ret <2 x i32> %tmp4 4262} 4263 4264define <4 x i32> @fcmunez4xfloat_fast(<4 x float> %A) { 4265; CHECK-LABEL: fcmunez4xfloat_fast: 4266; CHECK: // %bb.0: 4267; CHECK-NEXT: fcmeq v0.4s, v0.4s, #0.0 4268; CHECK-NEXT: mvn v0.16b, v0.16b 4269; CHECK-NEXT: ret 4270 %tmp3 = fcmp fast une <4 x float> %A, zeroinitializer 4271 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4272 ret <4 x i32> %tmp4 4273} 4274 4275define <2 x i64> @fcmunez2xdouble_fast(<2 x double> %A) { 4276; CHECK-LABEL: fcmunez2xdouble_fast: 4277; CHECK: // %bb.0: 4278; CHECK-NEXT: fcmeq v0.2d, v0.2d, #0.0 4279; CHECK-NEXT: mvn v0.16b, v0.16b 4280; CHECK-NEXT: ret 4281 %tmp3 = fcmp fast une <2 x double> %A, zeroinitializer 4282 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4283 ret <2 x i64> %tmp4 4284} 4285 4286define <2 x i32> @fcmunoz2xfloat_fast(<2 x float> %A) { 4287; CHECK-LABEL: fcmunoz2xfloat_fast: 4288; CHECK: // %bb.0: 4289; CHECK-NEXT: fcmeq v0.2s, v0.2s, v0.2s 4290; CHECK-NEXT: mvn v0.8b, v0.8b 4291; CHECK-NEXT: ret 4292 %tmp3 = fcmp fast uno <2 x float> %A, zeroinitializer 4293 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 4294 ret <2 x i32> %tmp4 4295} 4296 4297define <4 x i32> @fcmunoz4xfloat_fast(<4 x float> %A) { 4298; CHECK-LABEL: fcmunoz4xfloat_fast: 4299; CHECK: // %bb.0: 4300; CHECK-NEXT: fcmeq v0.4s, v0.4s, v0.4s 4301; CHECK-NEXT: mvn v0.16b, v0.16b 4302; CHECK-NEXT: ret 4303 %tmp3 = fcmp fast uno <4 x float> %A, zeroinitializer 4304 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 4305 ret <4 x i32> %tmp4 4306} 4307 4308define <2 x i64> @fcmunoz2xdouble_fast(<2 x double> %A) { 4309; CHECK-LABEL: fcmunoz2xdouble_fast: 4310; CHECK: // %bb.0: 4311; CHECK-NEXT: fcmeq v0.2d, v0.2d, v0.2d 4312; CHECK-NEXT: mvn v0.16b, v0.16b 4313; CHECK-NEXT: ret 4314 %tmp3 = fcmp fast uno <2 x double> %A, zeroinitializer 4315 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 4316 ret <2 x i64> %tmp4 4317 4318} 4319 4320; Test SETCC fast-math flags are propagated when combining zext(setcc). 4321define <4 x i32> @fcmule4xfloat_fast_zext(<4 x float> %A, <4 x float> %B) { 4322; CHECK-SD-LABEL: fcmule4xfloat_fast_zext: 4323; CHECK-SD: // %bb.0: 4324; CHECK-SD-NEXT: movi v2.4s, #1 4325; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s 4326; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b 4327; CHECK-SD-NEXT: ret 4328; 4329; CHECK-GI-LABEL: fcmule4xfloat_fast_zext: 4330; CHECK-GI: // %bb.0: 4331; CHECK-GI-NEXT: movi v2.4s, #1 4332; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s 4333; CHECK-GI-NEXT: bic v0.16b, v2.16b, v0.16b 4334; CHECK-GI-NEXT: ret 4335 %tmp3 = fcmp fast ule <4 x float> %A, %B 4336 %tmp4 = zext <4 x i1> %tmp3 to <4 x i32> 4337 ret <4 x i32> %tmp4 4338} 4339 4340; Test SETCC fast-math flags are propagated when combining aext(setcc). 4341define <4 x i1> @fcmule4xfloat_fast_aext(<4 x float> %A, <4 x float> %B) { 4342; CHECK-SD-LABEL: fcmule4xfloat_fast_aext: 4343; CHECK-SD: // %bb.0: 4344; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s 4345; CHECK-SD-NEXT: xtn v0.4h, v0.4s 4346; CHECK-SD-NEXT: ret 4347; 4348; CHECK-GI-LABEL: fcmule4xfloat_fast_aext: 4349; CHECK-GI: // %bb.0: 4350; CHECK-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s 4351; CHECK-GI-NEXT: mvn v0.16b, v0.16b 4352; CHECK-GI-NEXT: xtn v0.4h, v0.4s 4353; CHECK-GI-NEXT: ret 4354 %tmp3 = fcmp fast ule <4 x float> %A, %B 4355 ret <4 x i1> %tmp3 4356} 4357 4358define <4 x i64> @fcmoeq4xdouble(<4 x double> %A, <4 x double> %B) { 4359; CHECK-SD-LABEL: fcmoeq4xdouble: 4360; CHECK-SD: // %bb.0: 4361; CHECK-SD-NEXT: fcmeq v1.2d, v1.2d, v3.2d 4362; CHECK-SD-NEXT: fcmeq v0.2d, v0.2d, v2.2d 4363; CHECK-SD-NEXT: ret 4364; 4365; CHECK-GI-LABEL: fcmoeq4xdouble: 4366; CHECK-GI: // %bb.0: 4367; CHECK-GI-NEXT: fcmeq v0.2d, v0.2d, v2.2d 4368; CHECK-GI-NEXT: fcmeq v1.2d, v1.2d, v3.2d 4369; CHECK-GI-NEXT: ret 4370 %tmp3 = fcmp oeq <4 x double> %A, %B 4371 %tmp4 = sext <4 x i1> %tmp3 to <4 x i64> 4372 ret <4 x i64> %tmp4 4373} 4374 4375define <8 x i32> @fcmoeq8xfloat(<8 x float> %A, <8 x float> %B) { 4376; CHECK-SD-LABEL: fcmoeq8xfloat: 4377; CHECK-SD: // %bb.0: 4378; CHECK-SD-NEXT: fcmeq v1.4s, v1.4s, v3.4s 4379; CHECK-SD-NEXT: fcmeq v0.4s, v0.4s, v2.4s 4380; CHECK-SD-NEXT: ret 4381; 4382; CHECK-GI-LABEL: fcmoeq8xfloat: 4383; CHECK-GI: // %bb.0: 4384; CHECK-GI-NEXT: fcmeq v0.4s, v0.4s, v2.4s 4385; CHECK-GI-NEXT: fcmeq v1.4s, v1.4s, v3.4s 4386; CHECK-GI-NEXT: ret 4387 %tmp3 = fcmp oeq <8 x float> %A, %B 4388 %tmp4 = sext <8 x i1> %tmp3 to <8 x i32> 4389 ret <8 x i32> %tmp4 4390} 4391