1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3 4target triple = "aarch64" 5 6; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL 7; during ISEL. 8; 9; Subtly different from a plain vector bit select: operand representing the 10; condition has been negated (-v, not to be confused with bitwise_not(v)). 11 12; Each vbsl_neg_cond_xxxx tests one of the 16 permutations of the operands. 13 14define <4 x i32> @vbsl_neg_cond_0000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 15; CHECK-LABEL: vbsl_neg_cond_0000: 16; CHECK: // %bb.0: 17; CHECK-NEXT: neg v0.4s, v0.4s 18; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 19; CHECK-NEXT: ret 20 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 21 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 22 %left_bits_0 = and <4 x i32> %neg_cond, %left 23 %right_bits_0 = and <4 x i32> %min_cond, %right 24 %bsl0000 = or <4 x i32> %right_bits_0, %left_bits_0 25 ret <4 x i32> %bsl0000 26} 27 28define <4 x i32> @vbsl_neg_cond_0001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 29; CHECK-LABEL: vbsl_neg_cond_0001: 30; CHECK: // %bb.0: 31; CHECK-NEXT: neg v0.4s, v0.4s 32; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 33; CHECK-NEXT: ret 34 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 35 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 36 %left_bits_1 = and <4 x i32> %left, %neg_cond 37 %right_bits_0 = and <4 x i32> %min_cond, %right 38 %bsl0001 = or <4 x i32> %right_bits_0, %left_bits_1 39 ret <4 x i32> %bsl0001 40} 41 42define <4 x i32> @vbsl_neg_cond_0010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 43; CHECK-LABEL: vbsl_neg_cond_0010: 44; CHECK: // %bb.0: 45; CHECK-NEXT: neg v0.4s, v0.4s 46; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 47; CHECK-NEXT: ret 48 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 49 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 50 %left_bits_0 = and <4 x i32> %neg_cond, %left 51 %right_bits_1 = and <4 x i32> %right, %min_cond 52 %bsl0010 = or <4 x i32> %right_bits_1, %left_bits_0 53 ret <4 x i32> %bsl0010 54} 55 56define <4 x i32> @vbsl_neg_cond_0011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 57; CHECK-LABEL: vbsl_neg_cond_0011: 58; CHECK: // %bb.0: 59; CHECK-NEXT: neg v0.4s, v0.4s 60; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 61; CHECK-NEXT: ret 62 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 63 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 64 %left_bits_1 = and <4 x i32> %left, %neg_cond 65 %right_bits_1 = and <4 x i32> %right, %min_cond 66 %bsl0011 = or <4 x i32> %right_bits_1, %left_bits_1 67 ret <4 x i32> %bsl0011 68} 69 70define <4 x i32> @vbsl_neg_cond_0100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 71; CHECK-LABEL: vbsl_neg_cond_0100: 72; CHECK: // %bb.0: 73; CHECK-NEXT: neg v0.4s, v0.4s 74; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 75; CHECK-NEXT: ret 76 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 77 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 78 %left_bits_0 = and <4 x i32> %neg_cond, %left 79 %right_bits_0 = and <4 x i32> %min_cond, %right 80 %bsl0100 = or <4 x i32> %left_bits_0, %right_bits_0 81 ret <4 x i32> %bsl0100 82} 83 84define <4 x i32> @vbsl_neg_cond_0101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 85; CHECK-LABEL: vbsl_neg_cond_0101: 86; CHECK: // %bb.0: 87; CHECK-NEXT: neg v0.4s, v0.4s 88; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 89; CHECK-NEXT: ret 90 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 91 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 92 %left_bits_0 = and <4 x i32> %neg_cond, %left 93 %right_bits_1 = and <4 x i32> %right, %min_cond 94 %bsl0101 = or <4 x i32> %left_bits_0, %right_bits_1 95 ret <4 x i32> %bsl0101 96} 97 98define <4 x i32> @vbsl_neg_cond_0110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 99; CHECK-LABEL: vbsl_neg_cond_0110: 100; CHECK: // %bb.0: 101; CHECK-NEXT: neg v0.4s, v0.4s 102; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 103; CHECK-NEXT: ret 104 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 105 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 106 %left_bits_1 = and <4 x i32> %left, %neg_cond 107 %right_bits_0 = and <4 x i32> %min_cond, %right 108 %bsl0110 = or <4 x i32> %left_bits_1, %right_bits_0 109 ret <4 x i32> %bsl0110 110} 111 112define <4 x i32> @vbsl_neg_cond_0111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 113; CHECK-LABEL: vbsl_neg_cond_0111: 114; CHECK: // %bb.0: 115; CHECK-NEXT: neg v0.4s, v0.4s 116; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b 117; CHECK-NEXT: ret 118 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 119 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 120 %left_bits_1 = and <4 x i32> %left, %neg_cond 121 %right_bits_1 = and <4 x i32> %right, %min_cond 122 %bsl0111 = or <4 x i32> %left_bits_1, %right_bits_1 123 ret <4 x i32> %bsl0111 124} 125 126define <4 x i32> @vbsl_neg_cond_1000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 127; CHECK-LABEL: vbsl_neg_cond_1000: 128; CHECK: // %bb.0: 129; CHECK-NEXT: neg v0.4s, v0.4s 130; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 131; CHECK-NEXT: ret 132 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 133 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 134 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left 135 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right 136 %bsl1000 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_0 137 ret <4 x i32> %bsl1000 138} 139 140define <4 x i32> @vbsl_neg_cond_1001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 141; CHECK-LABEL: vbsl_neg_cond_1001: 142; CHECK: // %bb.0: 143; CHECK-NEXT: neg v0.4s, v0.4s 144; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 145; CHECK-NEXT: ret 146 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 147 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 148 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond 149 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right 150 %bsl1001 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_1 151 ret <4 x i32> %bsl1001 152} 153 154define <4 x i32> @vbsl_neg_cond_1010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 155; CHECK-LABEL: vbsl_neg_cond_1010: 156; CHECK: // %bb.0: 157; CHECK-NEXT: neg v0.4s, v0.4s 158; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 159; CHECK-NEXT: ret 160 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 161 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 162 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left 163 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond 164 %bsl1010 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_0 165 ret <4 x i32> %bsl1010 166} 167 168define <4 x i32> @vbsl_neg_cond_1011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 169; CHECK-LABEL: vbsl_neg_cond_1011: 170; CHECK: // %bb.0: 171; CHECK-NEXT: neg v0.4s, v0.4s 172; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 173; CHECK-NEXT: ret 174 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 175 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 176 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond 177 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond 178 %bsl1011 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_1 179 ret <4 x i32> %bsl1011 180} 181 182define <4 x i32> @vbsl_neg_cond_1100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 183; CHECK-LABEL: vbsl_neg_cond_1100: 184; CHECK: // %bb.0: 185; CHECK-NEXT: neg v0.4s, v0.4s 186; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 187; CHECK-NEXT: ret 188 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 189 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 190 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left 191 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right 192 %bsl1100 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_0 193 ret <4 x i32> %bsl1100 194} 195 196define <4 x i32> @vbsl_neg_cond_1101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 197; CHECK-LABEL: vbsl_neg_cond_1101: 198; CHECK: // %bb.0: 199; CHECK-NEXT: neg v0.4s, v0.4s 200; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 201; CHECK-NEXT: ret 202 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 203 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 204 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left 205 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond 206 %bsl1101 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_1 207 ret <4 x i32> %bsl1101 208} 209 210define <4 x i32> @vbsl_neg_cond_1110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 211; CHECK-LABEL: vbsl_neg_cond_1110: 212; CHECK: // %bb.0: 213; CHECK-NEXT: neg v0.4s, v0.4s 214; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 215; CHECK-NEXT: ret 216 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 217 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 218 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond 219 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right 220 %bsl1110 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_0 221 ret <4 x i32> %bsl1110 222} 223 224define <4 x i32> @vbsl_neg_cond_1111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 { 225; CHECK-LABEL: vbsl_neg_cond_1111: 226; CHECK: // %bb.0: 227; CHECK-NEXT: neg v0.4s, v0.4s 228; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b 229; CHECK-NEXT: ret 230 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond 231 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1> 232 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond 233 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond 234 %bsl1111 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_1 235 ret <4 x i32> %bsl1111 236} 237 238attributes #0 = { "target-features"="+neon" } 239