xref: /llvm-project/llvm/test/CodeGen/AArch64/neon-bitcast.ll (revision abcbca21cc2e8a2b256cd519df2b1559f29e8edd) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
3; RUN: llc -mtriple=aarch64_be-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE
4
5; From <8 x i8>
6
7define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
8; CHECK-LABEL: test_v8i8_to_v1i64:
9; CHECK:       // %bb.0:
10; CHECK-NEXT:    ret
11  %val = bitcast <8 x i8> %in to <1 x i64>
12  ret <1 x i64> %val
13}
14
15define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
16; CHECK-LABEL: test_v8i8_to_v2i32:
17; CHECK:       // %bb.0:
18; CHECK-NEXT:    ret
19  %val = bitcast <8 x i8> %in to <2 x i32>
20  ret <2 x i32> %val
21}
22
23define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
24; CHECK-LABEL: test_v8i8_to_v2f32:
25; CHECK:       // %bb.0:
26; CHECK-NEXT:    ret
27  %val = bitcast <8 x i8> %in to <2 x float>
28  ret <2 x float> %val
29}
30
31define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
32; CHECK-LABEL: test_v8i8_to_v4i16:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    ret
35  %val = bitcast <8 x i8> %in to <4 x i16>
36  ret <4 x i16> %val
37}
38
39define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
40; CHECK-LABEL: test_v8i8_to_v8i8:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    ret
43  %val = bitcast <8 x i8> %in to <8 x i8>
44  ret <8 x i8> %val
45}
46
47; From <4 x i16>
48
49define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
50; CHECK-LABEL: test_v4i16_to_v1i64:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    ret
53  %val = bitcast <4 x i16> %in to <1 x i64>
54  ret <1 x i64> %val
55}
56
57define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
58; CHECK-LABEL: test_v4i16_to_v2i32:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    ret
61  %val = bitcast <4 x i16> %in to <2 x i32>
62  ret <2 x i32> %val
63}
64
65define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
66; CHECK-LABEL: test_v4i16_to_v2f32:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    ret
69  %val = bitcast <4 x i16> %in to <2 x float>
70  ret <2 x float> %val
71}
72
73define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
74; CHECK-LABEL: test_v4i16_to_v4i16:
75; CHECK:       // %bb.0:
76; CHECK-NEXT:    ret
77  %val = bitcast <4 x i16> %in to <4 x i16>
78  ret <4 x i16> %val
79}
80
81define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
82; CHECK-LABEL: test_v4i16_to_v8i8:
83; CHECK:       // %bb.0:
84; CHECK-NEXT:    ret
85  %val = bitcast <4 x i16> %in to <8 x i8>
86  ret <8 x i8> %val
87}
88
89; From <2 x i32>
90
91define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
92; CHECK-LABEL: test_v2i32_to_v1i64:
93; CHECK:       // %bb.0:
94; CHECK-NEXT:    ret
95  %val = bitcast <2 x i32> %in to <1 x i64>
96  ret <1 x i64> %val
97}
98
99define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
100; CHECK-LABEL: test_v2i32_to_v2i32:
101; CHECK:       // %bb.0:
102; CHECK-NEXT:    ret
103  %val = bitcast <2 x i32> %in to <2 x i32>
104  ret <2 x i32> %val
105}
106
107define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
108; CHECK-LABEL: test_v2i32_to_v2f32:
109; CHECK:       // %bb.0:
110; CHECK-NEXT:    ret
111  %val = bitcast <2 x i32> %in to <2 x float>
112  ret <2 x float> %val
113}
114
115define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
116; CHECK-LABEL: test_v2i32_to_v4i16:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    ret
119  %val = bitcast <2 x i32> %in to <4 x i16>
120  ret <4 x i16> %val
121}
122
123define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
124; CHECK-LABEL: test_v2i32_to_v8i8:
125; CHECK:       // %bb.0:
126; CHECK-NEXT:    ret
127  %val = bitcast <2 x i32> %in to <8 x i8>
128  ret <8 x i8> %val
129}
130
131; From <2 x float>
132
133define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
134; CHECK-LABEL: test_v2f32_to_v1i64:
135; CHECK:       // %bb.0:
136; CHECK-NEXT:    ret
137  %val = bitcast <2 x float> %in to <1 x i64>
138  ret <1 x i64> %val
139}
140
141define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
142; CHECK-LABEL: test_v2f32_to_v2i32:
143; CHECK:       // %bb.0:
144; CHECK-NEXT:    ret
145  %val = bitcast <2 x float> %in to <2 x i32>
146  ret <2 x i32> %val
147}
148
149define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
150; CHECK-LABEL: test_v2f32_to_v2f32:
151; CHECK:       // %bb.0:
152; CHECK-NEXT:    ret
153  %val = bitcast <2 x float> %in to <2 x float>
154  ret <2 x float> %val
155}
156
157define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
158; CHECK-LABEL: test_v2f32_to_v4i16:
159; CHECK:       // %bb.0:
160; CHECK-NEXT:    ret
161  %val = bitcast <2 x float> %in to <4 x i16>
162  ret <4 x i16> %val
163}
164
165define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
166; CHECK-LABEL: test_v2f32_to_v8i8:
167; CHECK:       // %bb.0:
168; CHECK-NEXT:    ret
169  %val = bitcast <2 x float> %in to <8 x i8>
170  ret <8 x i8> %val
171}
172
173; From <1 x i64>
174
175define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
176; CHECK-LABEL: test_v1i64_to_v1i64:
177; CHECK:       // %bb.0:
178; CHECK-NEXT:    ret
179  %val = bitcast <1 x i64> %in to <1 x i64>
180  ret <1 x i64> %val
181}
182
183define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
184; CHECK-LABEL: test_v1i64_to_v2i32:
185; CHECK:       // %bb.0:
186; CHECK-NEXT:    ret
187  %val = bitcast <1 x i64> %in to <2 x i32>
188  ret <2 x i32> %val
189}
190
191define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
192; CHECK-LABEL: test_v1i64_to_v2f32:
193; CHECK:       // %bb.0:
194; CHECK-NEXT:    ret
195  %val = bitcast <1 x i64> %in to <2 x float>
196  ret <2 x float> %val
197}
198
199define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
200; CHECK-LABEL: test_v1i64_to_v4i16:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    ret
203  %val = bitcast <1 x i64> %in to <4 x i16>
204  ret <4 x i16> %val
205}
206
207define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
208; CHECK-LABEL: test_v1i64_to_v8i8:
209; CHECK:       // %bb.0:
210; CHECK-NEXT:    ret
211  %val = bitcast <1 x i64> %in to <8 x i8>
212  ret <8 x i8> %val
213}
214
215
216; From <16 x i8>
217
218define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
219; CHECK-LABEL: test_v16i8_to_v2f64:
220; CHECK:       // %bb.0:
221; CHECK-NEXT:    ret
222  %val = bitcast <16 x i8> %in to <2 x double>
223  ret <2 x double> %val
224}
225
226define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
227; CHECK-LABEL: test_v16i8_to_v2i64:
228; CHECK:       // %bb.0:
229; CHECK-NEXT:    ret
230  %val = bitcast <16 x i8> %in to <2 x i64>
231  ret <2 x i64> %val
232}
233
234define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
235; CHECK-LABEL: test_v16i8_to_v4i32:
236; CHECK:       // %bb.0:
237; CHECK-NEXT:    ret
238  %val = bitcast <16 x i8> %in to <4 x i32>
239  ret <4 x i32> %val
240}
241
242define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
243; CHECK-LABEL: test_v16i8_to_v2f32:
244; CHECK:       // %bb.0:
245; CHECK-NEXT:    ret
246  %val = bitcast <16 x i8> %in to <4 x float>
247  ret <4 x float> %val
248}
249
250define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
251; CHECK-LABEL: test_v16i8_to_v8i16:
252; CHECK:       // %bb.0:
253; CHECK-NEXT:    ret
254  %val = bitcast <16 x i8> %in to <8 x i16>
255  ret <8 x i16> %val
256}
257
258define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
259; CHECK-LABEL: test_v16i8_to_v16i8:
260; CHECK:       // %bb.0:
261; CHECK-NEXT:    ret
262  %val = bitcast <16 x i8> %in to <16 x i8>
263  ret <16 x i8> %val
264}
265
266; From <8 x i16>
267
268define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
269; CHECK-LABEL: test_v8i16_to_v2f64:
270; CHECK:       // %bb.0:
271; CHECK-NEXT:    ret
272  %val = bitcast <8 x i16> %in to <2 x double>
273  ret <2 x double> %val
274}
275
276define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
277;
278; CHECK-LABEL: test_v8i16_to_v2i64:
279; CHECK:       // %bb.0:
280; CHECK-NEXT:    ret
281  %val = bitcast <8 x i16> %in to <2 x i64>
282  ret <2 x i64> %val
283}
284
285define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
286; CHECK-LABEL: test_v8i16_to_v4i32:
287; CHECK:       // %bb.0:
288; CHECK-NEXT:    ret
289  %val = bitcast <8 x i16> %in to <4 x i32>
290  ret <4 x i32> %val
291}
292
293define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
294; CHECK-LABEL: test_v8i16_to_v2f32:
295; CHECK:       // %bb.0:
296; CHECK-NEXT:    ret
297  %val = bitcast <8 x i16> %in to <4 x float>
298  ret <4 x float> %val
299}
300
301define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
302; CHECK-LABEL: test_v8i16_to_v8i16:
303; CHECK:       // %bb.0:
304; CHECK-NEXT:    ret
305  %val = bitcast <8 x i16> %in to <8 x i16>
306  ret <8 x i16> %val
307}
308
309define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
310; CHECK-LABEL: test_v8i16_to_v16i8:
311; CHECK:       // %bb.0:
312; CHECK-NEXT:    ret
313  %val = bitcast <8 x i16> %in to <16 x i8>
314  ret <16 x i8> %val
315}
316
317; From <4 x i32>
318
319define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
320; CHECK-LABEL: test_v4i32_to_v2f64:
321; CHECK:       // %bb.0:
322; CHECK-NEXT:    ret
323  %val = bitcast <4 x i32> %in to <2 x double>
324  ret <2 x double> %val
325}
326
327define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
328; CHECK-LABEL: test_v4i32_to_v2i64:
329; CHECK:       // %bb.0:
330; CHECK-NEXT:    ret
331  %val = bitcast <4 x i32> %in to <2 x i64>
332  ret <2 x i64> %val
333}
334
335define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
336; CHECK-LABEL: test_v4i32_to_v4i32:
337; CHECK:       // %bb.0:
338; CHECK-NEXT:    ret
339  %val = bitcast <4 x i32> %in to <4 x i32>
340  ret <4 x i32> %val
341}
342
343define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
344; CHECK-LABEL: test_v4i32_to_v2f32:
345; CHECK:       // %bb.0:
346; CHECK-NEXT:    ret
347  %val = bitcast <4 x i32> %in to <4 x float>
348  ret <4 x float> %val
349}
350
351define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
352; CHECK-LABEL: test_v4i32_to_v8i16:
353; CHECK:       // %bb.0:
354; CHECK-NEXT:    ret
355  %val = bitcast <4 x i32> %in to <8 x i16>
356  ret <8 x i16> %val
357}
358
359define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
360; CHECK-LABEL: test_v4i32_to_v16i8:
361; CHECK:       // %bb.0:
362; CHECK-NEXT:    ret
363  %val = bitcast <4 x i32> %in to <16 x i8>
364  ret <16 x i8> %val
365}
366
367; From <4 x float>
368
369define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
370; CHECK-LABEL: test_v4f32_to_v2f64:
371; CHECK:       // %bb.0:
372; CHECK-NEXT:    ret
373  %val = bitcast <4 x float> %in to <2 x double>
374  ret <2 x double> %val
375}
376
377define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
378; CHECK-LABEL: test_v4f32_to_v2i64:
379; CHECK:       // %bb.0:
380; CHECK-NEXT:    ret
381  %val = bitcast <4 x float> %in to <2 x i64>
382  ret <2 x i64> %val
383}
384
385define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
386; CHECK-LABEL: test_v4f32_to_v4i32:
387; CHECK:       // %bb.0:
388; CHECK-NEXT:    ret
389  %val = bitcast <4 x float> %in to <4 x i32>
390  ret <4 x i32> %val
391}
392
393define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
394; CHECK-LABEL: test_v4f32_to_v4f32:
395; CHECK:       // %bb.0:
396; CHECK-NEXT:    ret
397  %val = bitcast <4 x float> %in to <4 x float>
398  ret <4 x float> %val
399}
400
401define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
402; CHECK-LABEL: test_v4f32_to_v8i16:
403; CHECK:       // %bb.0:
404; CHECK-NEXT:    ret
405  %val = bitcast <4 x float> %in to <8 x i16>
406  ret <8 x i16> %val
407}
408
409define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
410; CHECK-LABEL: test_v4f32_to_v16i8:
411; CHECK:       // %bb.0:
412; CHECK-NEXT:    ret
413  %val = bitcast <4 x float> %in to <16 x i8>
414  ret <16 x i8> %val
415}
416
417; From <2 x i64>
418
419define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
420; CHECK-LABEL: test_v2i64_to_v2f64:
421; CHECK:       // %bb.0:
422; CHECK-NEXT:    ret
423  %val = bitcast <2 x i64> %in to <2 x double>
424  ret <2 x double> %val
425}
426
427define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
428; CHECK-LABEL: test_v2i64_to_v2i64:
429; CHECK:       // %bb.0:
430; CHECK-NEXT:    ret
431  %val = bitcast <2 x i64> %in to <2 x i64>
432  ret <2 x i64> %val
433}
434
435define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
436; CHECK-LABEL: test_v2i64_to_v4i32:
437; CHECK:       // %bb.0:
438; CHECK-NEXT:    ret
439  %val = bitcast <2 x i64> %in to <4 x i32>
440  ret <4 x i32> %val
441}
442
443define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
444; CHECK-LABEL: test_v2i64_to_v4f32:
445; CHECK:       // %bb.0:
446; CHECK-NEXT:    ret
447  %val = bitcast <2 x i64> %in to <4 x float>
448  ret <4 x float> %val
449}
450
451define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
452; CHECK-LABEL: test_v2i64_to_v8i16:
453; CHECK:       // %bb.0:
454; CHECK-NEXT:    ret
455  %val = bitcast <2 x i64> %in to <8 x i16>
456  ret <8 x i16> %val
457}
458
459define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
460; CHECK-LABEL: test_v2i64_to_v16i8:
461; CHECK:       // %bb.0:
462; CHECK-NEXT:    ret
463  %val = bitcast <2 x i64> %in to <16 x i8>
464  ret <16 x i8> %val
465}
466
467; From <2 x double>
468
469define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
470; CHECK-LABEL: test_v2f64_to_v2f64:
471; CHECK:       // %bb.0:
472; CHECK-NEXT:    ret
473  %val = bitcast <2 x double> %in to <2 x double>
474  ret <2 x double> %val
475}
476
477define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
478; CHECK-LABEL: test_v2f64_to_v2i64:
479; CHECK:       // %bb.0:
480; CHECK-NEXT:    ret
481  %val = bitcast <2 x double> %in to <2 x i64>
482  ret <2 x i64> %val
483}
484
485define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
486; CHECK-LABEL: test_v2f64_to_v4i32:
487; CHECK:       // %bb.0:
488; CHECK-NEXT:    ret
489  %val = bitcast <2 x double> %in to <4 x i32>
490  ret <4 x i32> %val
491}
492
493define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
494; CHECK-LABEL: test_v2f64_to_v4f32:
495; CHECK:       // %bb.0:
496; CHECK-NEXT:    ret
497  %val = bitcast <2 x double> %in to <4 x float>
498  ret <4 x float> %val
499}
500
501define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
502; CHECK-LABEL: test_v2f64_to_v8i16:
503; CHECK:       // %bb.0:
504; CHECK-NEXT:    ret
505  %val = bitcast <2 x double> %in to <8 x i16>
506  ret <8 x i16> %val
507}
508
509define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{
510; CHECK-LABEL: test_v2f64_to_v16i8:
511; CHECK:       // %bb.0:
512; CHECK-NEXT:    ret
513  %val = bitcast <2 x double> %in to <16 x i8>
514  ret <16 x i8> %val
515}
516
517define <2 x i16> @bitcast_i32_to_v2i16(i32 %word) {
518; CHECK-LE-LABEL: bitcast_i32_to_v2i16:
519; CHECK-LE:       // %bb.0:
520; CHECK-LE-NEXT:    fmov s0, w0
521; CHECK-LE-NEXT:    ushll v0.4s, v0.4h, #0
522; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
523; CHECK-LE-NEXT:    ret
524;
525; CHECK-BE-LABEL: bitcast_i32_to_v2i16:
526; CHECK-BE:       // %bb.0:
527; CHECK-BE-NEXT:    fmov s0, w0
528; CHECK-BE-NEXT:    rev32 v0.4h, v0.4h
529; CHECK-BE-NEXT:    ushll v0.4s, v0.4h, #0
530; CHECK-BE-NEXT:    rev64 v0.2s, v0.2s
531; CHECK-BE-NEXT:    ret
532  %ret = bitcast i32 %word to <2 x i16>
533  ret <2 x i16> %ret
534}
535
536define <4 x i8> @bitcast_i32_to_v4i8(i32 %word) {
537; CHECK-LE-LABEL: bitcast_i32_to_v4i8:
538; CHECK-LE:       // %bb.0:
539; CHECK-LE-NEXT:    fmov s0, w0
540; CHECK-LE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
541; CHECK-LE-NEXT:    ret
542;
543; CHECK-BE-LABEL: bitcast_i32_to_v4i8:
544; CHECK-BE:       // %bb.0:
545; CHECK-BE-NEXT:    fmov s0, w0
546; CHECK-BE-NEXT:    rev32 v0.8b, v0.8b
547; CHECK-BE-NEXT:    zip1 v0.8b, v0.8b, v0.8b
548; CHECK-BE-NEXT:    rev64 v0.4h, v0.4h
549; CHECK-BE-NEXT:    ret
550  %ret = bitcast i32 %word to <4 x i8>
551  ret <4 x i8> %ret
552}
553
554; TODO: Eliminate redundant moving back and forth between gpr and vectors
555define <2 x i8> @bitcast_i16_to_v2i8(i16 %word) {
556; CHECK-LE-LABEL: bitcast_i16_to_v2i8:
557; CHECK-LE:       // %bb.0:
558; CHECK-LE-NEXT:    fmov s0, w0
559; CHECK-LE-NEXT:    umov w8, v0.b[0]
560; CHECK-LE-NEXT:    umov w9, v0.b[1]
561; CHECK-LE-NEXT:    fmov s0, w8
562; CHECK-LE-NEXT:    mov v0.s[1], w9
563; CHECK-LE-NEXT:    // kill: def $d0 killed $d0 killed $q0
564; CHECK-LE-NEXT:    ret
565;
566; CHECK-BE-LABEL: bitcast_i16_to_v2i8:
567; CHECK-BE:       // %bb.0:
568; CHECK-BE-NEXT:    fmov s0, w0
569; CHECK-BE-NEXT:    rev16 v0.16b, v0.16b
570; CHECK-BE-NEXT:    umov w8, v0.b[0]
571; CHECK-BE-NEXT:    umov w9, v0.b[1]
572; CHECK-BE-NEXT:    fmov s0, w8
573; CHECK-BE-NEXT:    mov v0.s[1], w9
574; CHECK-BE-NEXT:    rev64 v0.2s, v0.2s
575; CHECK-BE-NEXT:    ret
576  %ret = bitcast i16 %word to <2 x i8>
577  ret <2 x i8> %ret
578}
579
580