xref: /llvm-project/llvm/test/CodeGen/AArch64/neg-abs.ll (revision d29fc6e7d24f9bf67512180c0be3f08526049a27) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs \
3; RUN:   -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
4
5declare i64 @llvm.abs.i64(i64, i1 immarg)
6
7define i64 @neg_abs64(i64 %x) {
8; CHECK-LABEL: neg_abs64:
9; CHECK:       // %bb.0:
10; CHECK-NEXT:    cmp x0, #0
11; CHECK-NEXT:    cneg x0, x0, pl
12; CHECK-NEXT:    ret
13  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
14  %neg = sub nsw i64 0, %abs
15  ret i64 %neg
16}
17
18declare i32 @llvm.abs.i32(i32, i1 immarg)
19
20define i32 @neg_abs32(i32 %x) {
21; CHECK-LABEL: neg_abs32:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    cmp w0, #0
24; CHECK-NEXT:    cneg w0, w0, pl
25; CHECK-NEXT:    ret
26  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
27  %neg = sub nsw i32 0, %abs
28  ret i32 %neg
29}
30
31declare i16 @llvm.abs.i16(i16, i1 immarg)
32
33define i16 @neg_abs16(i16 %x) {
34; CHECK-LABEL: neg_abs16:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    sbfx w8, w0, #15, #1
37; CHECK-NEXT:    eor w9, w0, w8
38; CHECK-NEXT:    sub w0, w8, w9
39; CHECK-NEXT:    ret
40  %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
41  %neg = sub nsw i16 0, %abs
42  ret i16 %neg
43}
44
45
46declare i128 @llvm.abs.i128(i128, i1 immarg)
47
48define i128 @neg_abs128(i128 %x) {
49; CHECK-LABEL: neg_abs128:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    asr x8, x1, #63
52; CHECK-NEXT:    eor x9, x0, x8
53; CHECK-NEXT:    eor x10, x1, x8
54; CHECK-NEXT:    subs x0, x8, x9
55; CHECK-NEXT:    sbc x1, x8, x10
56; CHECK-NEXT:    ret
57  %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
58  %neg = sub nsw i128 0, %abs
59  ret i128 %neg
60}
61
62
63
64define i64 @abs64(i64 %x) {
65; CHECK-LABEL: abs64:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    cmp x0, #0
68; CHECK-NEXT:    cneg x0, x0, mi
69; CHECK-NEXT:    ret
70  %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
71  ret i64 %abs
72}
73
74define i32 @abs32(i32 %x) {
75; CHECK-LABEL: abs32:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    cmp w0, #0
78; CHECK-NEXT:    cneg w0, w0, mi
79; CHECK-NEXT:    ret
80  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
81  ret i32 %abs
82}
83
84define i16 @abs16(i16 %x) {
85; CHECK-LABEL: abs16:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    sxth w8, w0
88; CHECK-NEXT:    cmp w8, #0
89; CHECK-NEXT:    cneg w0, w8, mi
90; CHECK-NEXT:    ret
91  %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
92  ret i16 %abs
93}
94
95define i128 @abs128(i128 %x) {
96; CHECK-LABEL: abs128:
97; CHECK:       // %bb.0:
98; CHECK-NEXT:    asr x8, x1, #63
99; CHECK-NEXT:    eor x9, x0, x8
100; CHECK-NEXT:    eor x10, x1, x8
101; CHECK-NEXT:    subs x0, x9, x8
102; CHECK-NEXT:    sbc x1, x10, x8
103; CHECK-NEXT:    ret
104  %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
105  ret i128 %abs
106}
107
108