1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s | FileCheck %s 3 4target triple = "aarch64-unknown-linux-gnu" 5 6; 7; VECTOR_SPLICE (index) 8; 9 10define <16 x i8> @splice_v16i8_idx(<16 x i8> %a, <16 x i8> %b) #0 { 11; CHECK-LABEL: splice_v16i8_idx: 12; CHECK: // %bb.0: 13; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1 14; CHECK-NEXT: ret 15 %res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1) 16 ret <16 x i8> %res 17} 18 19define <2 x double> @splice_v2f64_idx(<2 x double> %a, <2 x double> %b) #0 { 20; CHECK-LABEL: splice_v2f64_idx: 21; CHECK: // %bb.0: 22; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 23; CHECK-NEXT: ret 24 %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 1) 25 ret <2 x double> %res 26} 27 28; Verify promote type legalisation works as expected. 29define <2 x i8> @splice_v2i8_idx(<2 x i8> %a, <2 x i8> %b) #0 { 30; CHECK-LABEL: splice_v2i8_idx: 31; CHECK: // %bb.0: 32; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 33; CHECK-NEXT: ret 34 %res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 1) 35 ret <2 x i8> %res 36} 37 38; Verify splitvec type legalisation works as expected. 39define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 { 40; CHECK-LABEL: splice_v8i32_idx: 41; CHECK: // %bb.0: 42; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 43; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4 44; CHECK-NEXT: ret 45 %res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5) 46 ret <8 x i32> %res 47} 48 49; Verify splitvec type legalisation works as expected. 50define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 { 51; CHECK-LABEL: splice_v16f32_idx: 52; CHECK: // %bb.0: 53; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12 54; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 55; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12 56; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12 57; CHECK-NEXT: mov v2.16b, v6.16b 58; CHECK-NEXT: ret 59 %res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7) 60 ret <16 x float> %res 61} 62 63; 64; VECTOR_SPLICE (trailing elements) 65; 66 67define <16 x i8> @splice_v16i8(<16 x i8> %a, <16 x i8> %b) #0 { 68; CHECK-LABEL: splice_v16i8: 69; CHECK: // %bb.0: 70; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1 71; CHECK-NEXT: ret 72 %res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 -15) 73 ret <16 x i8> %res 74} 75 76define <2 x double> @splice_v2f64(<2 x double> %a, <2 x double> %b) #0 { 77; CHECK-LABEL: splice_v2f64: 78; CHECK: // %bb.0: 79; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 80; CHECK-NEXT: ret 81 %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -1) 82 ret <2 x double> %res 83} 84 85; Verify promote type legalisation works as expected. 86define <2 x i8> @splice_v2i8(<2 x i8> %a, <2 x i8> %b) #0 { 87; CHECK-LABEL: splice_v2i8: 88; CHECK: // %bb.0: 89; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 90; CHECK-NEXT: ret 91 %res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 -1) 92 ret <2 x i8> %res 93} 94 95; Verify splitvec type legalisation works as expected. 96define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 { 97; CHECK-LABEL: splice_v8i32: 98; CHECK: // %bb.0: 99; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 100; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4 101; CHECK-NEXT: ret 102 %res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3) 103 ret <8 x i32> %res 104} 105 106; Verify splitvec type legalisation works as expected. 107define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 { 108; CHECK-LABEL: splice_v16f32: 109; CHECK: // %bb.0: 110; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12 111; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12 112; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12 113; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12 114; CHECK-NEXT: mov v2.16b, v6.16b 115; CHECK-NEXT: ret 116 %res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9) 117 ret <16 x float> %res 118} 119 120declare <2 x i8> @llvm.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) 121declare <16 x i8> @llvm.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) 122declare <8 x i32> @llvm.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) 123declare <16 x float> @llvm.vector.splice.v16f32(<16 x float>, <16 x float>, i32) 124declare <2 x double> @llvm.vector.splice.v2f64(<2 x double>, <2 x double>, i32) 125 126attributes #0 = { nounwind "target-features"="+neon" } 127