1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s 3 4; Tests to check that the scheduler dependencies derived from alias analysis are 5; correct when we have loads that have been split up so that they can later be 6; merged into STP. 7 8; Now that overwritten stores are elided in SelectionDAG, dependencies 9; are resolved and removed before MISCHED. Check that we have 10; equivalent pair of stp calls as a baseline. 11 12; CHECK-LABEL: test_splat 13; CHECK: ldr [[REG:w[0-9]+]], [x2] 14; CHECK-DAG: stp w0, [[REG]], [x2, #12] 15; CHECK-DAG: stp [[REG]], w1, [x2, #4] 16define void @test_splat(i32 %x, i32 %y, ptr %p) { 17entry: 18 %val = load i32, ptr %p, align 4 19 %0 = getelementptr inbounds i32, ptr %p, i64 1 20 %1 = getelementptr inbounds i32, ptr %p, i64 2 21 %2 = getelementptr inbounds i32, ptr %p, i64 3 22 %vec0 = insertelement <4 x i32> undef, i32 %val, i32 0 23 %vec1 = insertelement <4 x i32> %vec0, i32 %val, i32 1 24 %vec2 = insertelement <4 x i32> %vec1, i32 %val, i32 2 25 %vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 3 26 store <4 x i32> %vec3, ptr %0, align 4 27 store i32 %x, ptr %2, align 4 28 store i32 %y, ptr %1, align 4 29 ret void 30} 31 32declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) 33%struct.tree_common = type { ptr, ptr, i32 } 34 35; CHECK-LABEL: test_zero 36; CHECK-DAG: stp x2, xzr, [x0, #8] 37; CHECK-DAG: str w1, [x0, #16] 38; CHECK-DAG: str xzr, [x0] 39 40define void @test_zero(ptr %t, i32 %code, ptr %type) { 41entry: 42 tail call void @llvm.memset.p0.i64(ptr align 8 %t, i8 0, i64 24, i1 false) 43 %code1 = getelementptr inbounds %struct.tree_common, ptr %t, i64 0, i32 2 44 store i32 %code, ptr %code1, align 8 45 %type2 = getelementptr inbounds %struct.tree_common, ptr %t, i64 0, i32 1 46 store ptr %type, ptr %type2, align 8 47 ret void 48} 49