1; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-address | FileCheck %s 2; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a65 | FileCheck %s 3; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s 4; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s 5; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s 6; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1 | FileCheck %s 7; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1a | FileCheck %s 8; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1b | FileCheck %s 9 10target triple = "aarch64-unknown" 11 12@var_8bit = dso_local global i8 0 13@var_16bit = dso_local global i16 0 14@var_32bit = dso_local global i32 0 15@var_64bit = dso_local global i64 0 16@var_128bit = dso_local global i128 0 17@var_half = dso_local global half 0.0 18@var_float = dso_local global float 0.0 19@var_double = dso_local global double 0.0 20@var_double2 = dso_local global <2 x double> <double 0.0, double 0.0> 21 22define dso_local void @ldst_8bit() { 23 %val8 = load volatile i8, ptr @var_8bit 24 %ext = zext i8 %val8 to i64 25 %add = add i64 %ext, 1 26 %val16 = trunc i64 %add to i16 27 store volatile i16 %val16, ptr @var_16bit 28 ret void 29 30; CHECK-LABEL: ldst_8bit: 31; CHECK: adrp [[RB:x[0-9]+]], var_8bit 32; CHECK-NEXT: ldrb {{w[0-9]+}}, [[[RB]], {{#?}}:lo12:var_8bit] 33; CHECK: adrp [[RH:x[0-9]+]], var_16bit 34; CHECK-NEXT: strh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit] 35} 36 37define dso_local void @ldst_16bit() { 38 %val16 = load volatile i16, ptr @var_16bit 39 %ext = zext i16 %val16 to i64 40 %add = add i64 %ext, 1 41 %val32 = trunc i64 %add to i32 42 store volatile i32 %val32, ptr @var_32bit 43 ret void 44 45; CHECK-LABEL: ldst_16bit: 46; CHECK: adrp [[RH:x[0-9]+]], var_16bit 47; CHECK-NEXT: ldrh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit] 48; CHECK: adrp [[RW:x[0-9]+]], var_32bit 49; CHECK-NEXT: str {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit] 50} 51 52define dso_local void @ldst_32bit() { 53 %val32 = load volatile i32, ptr @var_32bit 54 %ext = zext i32 %val32 to i64 55 %val64 = add i64 %ext, 1 56 store volatile i64 %val64, ptr @var_64bit 57 ret void 58 59; CHECK-LABEL: ldst_32bit: 60; CHECK: adrp [[RW:x[0-9]+]], var_32bit 61; CHECK-NEXT: ldr {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit] 62; CHECK: adrp [[RL:x[0-9]+]], var_64bit 63; CHECK-NEXT: str {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit] 64} 65 66define dso_local void @ldst_64bit() { 67 %val64 = load volatile i64, ptr @var_64bit 68 %ext = zext i64 %val64 to i128 69 %val128 = add i128 %ext, 1 70 store volatile i128 %val128, ptr @var_128bit 71 ret void 72 73; CHECK-LABEL: ldst_64bit: 74; CHECK: adrp [[RL:x[0-9]+]], var_64bit 75; CHECK-NEXT: ldr {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit] 76; CHECK: adrp [[RQ:x[0-9]+]], var_128bit 77; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit 78} 79 80define dso_local void @ldst_half() { 81 %valh = load volatile half, ptr @var_half 82 %valf = fpext half %valh to float 83 store volatile float %valf, ptr @var_float 84 ret void 85 86; CHECK-LABEL: ldst_half: 87; CHECK: adrp [[RH:x[0-9]+]], var_half 88; CHECK-NEXT: ldr {{h[0-9]+}}, [[[RH]], {{#?}}:lo12:var_half] 89; CHECK: adrp [[RF:x[0-9]+]], var_float 90; CHECK-NEXT: str {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float] 91} 92 93define dso_local void @ldst_float() { 94 %valf = load volatile float, ptr @var_float 95 %vald = fpext float %valf to double 96 store volatile double %vald, ptr @var_double 97 ret void 98 99; CHECK-LABEL: ldst_float: 100; CHECK: adrp [[RF:x[0-9]+]], var_float 101; CHECK-NEXT: ldr {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float] 102; CHECK: adrp [[RD:x[0-9]+]], var_double 103; CHECK-NEXT: str {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double] 104} 105 106define dso_local void @ldst_double() { 107 %valf = load volatile float, ptr @var_float 108 %vale = fpext float %valf to double 109 %vald = load volatile double, ptr @var_double 110 %vald1 = insertelement <2 x double> undef, double %vald, i32 0 111 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1 112 store volatile <2 x double> %vald2, ptr @var_double2 113 ret void 114 115; CHECK-LABEL: ldst_double: 116; CHECK: adrp [[RD:x[0-9]+]], var_double 117; CHECK-NEXT: ldr {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double] 118; CHECK: adrp [[RQ:x[0-9]+]], var_double2 119; CHECK-NEXT: str {{q[0-9]+}}, [[[RQ]], {{#?}}:lo12:var_double2] 120} 121