xref: /llvm-project/llvm/test/CodeGen/AArch64/minmax.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
3
4define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: t1:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    smax v0.4s, v0.4s, v1.4s
8; CHECK-NEXT:    ret
9  %t1 = icmp sgt <4 x i32> %a, %b
10  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
11  ret <4 x i32> %t2
12}
13
14define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {
15; CHECK-LABEL: t2:
16; CHECK:       // %bb.0:
17; CHECK-NEXT:    smin v0.4s, v0.4s, v1.4s
18; CHECK-NEXT:    ret
19  %t1 = icmp slt <4 x i32> %a, %b
20  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
21  ret <4 x i32> %t2
22}
23
24define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {
25; CHECK-LABEL: t3:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    umax v0.4s, v0.4s, v1.4s
28; CHECK-NEXT:    ret
29  %t1 = icmp ugt <4 x i32> %a, %b
30  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
31  ret <4 x i32> %t2
32}
33
34define <8 x i8> @t4(<8 x i8> %a, <8 x i8> %b) {
35; CHECK-LABEL: t4:
36; CHECK:       // %bb.0:
37; CHECK-NEXT:    umin v0.8b, v0.8b, v1.8b
38; CHECK-NEXT:    ret
39  %t1 = icmp ult <8 x i8> %a, %b
40  %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
41  ret <8 x i8> %t2
42}
43
44define <4 x i16> @t5(<4 x i16> %a, <4 x i16> %b) {
45; CHECK-LABEL: t5:
46; CHECK:       // %bb.0:
47; CHECK-NEXT:    smin v0.4h, v1.4h, v0.4h
48; CHECK-NEXT:    ret
49  %t1 = icmp sgt <4 x i16> %b, %a
50  %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
51  ret <4 x i16> %t2
52}
53
54define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {
55; CHECK-LABEL: t6:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    smax v0.2s, v1.2s, v0.2s
58; CHECK-NEXT:    ret
59  %t1 = icmp slt <2 x i32> %b, %a
60  %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
61  ret <2 x i32> %t2
62}
63
64define <16 x i8> @t7(<16 x i8> %a, <16 x i8> %b) {
65; CHECK-LABEL: t7:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    umin v0.16b, v1.16b, v0.16b
68; CHECK-NEXT:    ret
69  %t1 = icmp ugt <16 x i8> %b, %a
70  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
71  ret <16 x i8> %t2
72}
73
74define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) {
75; CHECK-LABEL: t8:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    umax v0.8h, v1.8h, v0.8h
78; CHECK-NEXT:    ret
79  %t1 = icmp ult <8 x i16> %b, %a
80  %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
81  ret <8 x i16> %t2
82}
83
84define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
85; CHECK-LABEL: t9:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    umin v0.4s, v1.4s, v0.4s
88; CHECK-NEXT:    smax v0.4s, v0.4s, v2.4s
89; CHECK-NEXT:    ret
90  %t1 = icmp ugt <4 x i32> %b, %a
91  %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
92  %t3 = icmp sge <4 x i32> %t2, %c
93  %t4 = select <4 x i1> %t3, <4 x i32> %t2, <4 x i32> %c
94  ret <4 x i32> %t4
95}
96
97define <8 x i32> @t10(<8 x i32> %a, <8 x i32> %b) {
98; CHECK-LABEL: t10:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    smax v1.4s, v1.4s, v3.4s
101; CHECK-NEXT:    smax v0.4s, v0.4s, v2.4s
102; CHECK-NEXT:    ret
103  %t1 = icmp sgt <8 x i32> %a, %b
104  %t2 = select <8 x i1> %t1, <8 x i32> %a, <8 x i32> %b
105  ret <8 x i32> %t2
106}
107
108define <16 x i32> @t11(<16 x i32> %a, <16 x i32> %b) {
109; CHECK-LABEL: t11:
110; CHECK:       // %bb.0:
111; CHECK-NEXT:    smin v2.4s, v2.4s, v6.4s
112; CHECK-NEXT:    smin v0.4s, v0.4s, v4.4s
113; CHECK-NEXT:    smin v1.4s, v1.4s, v5.4s
114; CHECK-NEXT:    smin v3.4s, v3.4s, v7.4s
115; CHECK-NEXT:    ret
116  %t1 = icmp sle <16 x i32> %a, %b
117  %t2 = select <16 x i1> %t1, <16 x i32> %a, <16 x i32> %b
118  ret <16 x i32> %t2
119}
120
121; The icmp is used by two instructions, so don't produce a umin node.
122define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) {
123; CHECK-LABEL: t12:
124; CHECK:       // %bb.0:
125; CHECK-NEXT:    cmhi v2.16b, v1.16b, v0.16b
126; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
127; CHECK-NEXT:    sub v0.16b, v0.16b, v2.16b
128; CHECK-NEXT:    ret
129  %t1 = icmp ugt <16 x i8> %b, %a
130  %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
131  %t3 = zext <16 x i1> %t1 to <16 x i8>
132  %t4 = add <16 x i8> %t3, %t2
133  ret <16 x i8> %t4
134}
135
136define <1 x i64> @t13(<1 x i64> %a, <1 x i64> %b) {
137; CHECK-LABEL: t13:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    cmhi d2, d1, d0
140; CHECK-NEXT:    bif v0.8b, v1.8b, v2.8b
141; CHECK-NEXT:    ret
142  %t1 = icmp ult <1 x i64> %a, %b
143  %t2 = select <1 x i1> %t1, <1 x i64> %a, <1 x i64> %b
144  ret <1 x i64> %t2
145}
146
147define <2 x i64> @t14(<2 x i64> %a, <2 x i64> %b) {
148; CHECK-LABEL: t14:
149; CHECK:       // %bb.0:
150; CHECK-NEXT:    cmhi v2.2d, v0.2d, v1.2d
151; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
152; CHECK-NEXT:    ret
153  %t1 = icmp ugt <2 x i64> %a, %b
154  %t2 = select <2 x i1> %t1, <2 x i64> %a, <2 x i64> %b
155  ret <2 x i64> %t2
156}
157
158define <4 x i64> @t15(<4 x i64> %a, <4 x i64> %b) {
159; CHECK-LABEL: t15:
160; CHECK:       // %bb.0:
161; CHECK-NEXT:    cmhi v4.2d, v3.2d, v1.2d
162; CHECK-NEXT:    cmhi v5.2d, v2.2d, v0.2d
163; CHECK-NEXT:    bif v1.16b, v3.16b, v4.16b
164; CHECK-NEXT:    bif v0.16b, v2.16b, v5.16b
165; CHECK-NEXT:    ret
166  %t1 = icmp ule <4 x i64> %a, %b
167  %t2 = select <4 x i1> %t1, <4 x i64> %a, <4 x i64> %b
168  ret <4 x i64> %t2
169}
170