1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ISEL 3; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-FAST 4 5; Test that we use the correct register class. 6define i32 @mul_add_imm(i32 %a, i32 %b) { 7; CHECK-LABEL: mul_add_imm: 8; CHECK: ; %bb.0: 9; CHECK-NEXT: mov w8, #4 ; =0x4 10; CHECK-NEXT: madd w0, w0, w1, w8 11; CHECK-NEXT: ret 12 %1 = mul i32 %a, %b 13 %2 = add i32 %1, 4 14 ret i32 %2 15} 16 17define i32 @mul_sub_imm1(i32 %a, i32 %b) { 18; CHECK-LABEL: mul_sub_imm1: 19; CHECK: ; %bb.0: 20; CHECK-NEXT: mov w8, #4 ; =0x4 21; CHECK-NEXT: msub w0, w0, w1, w8 22; CHECK-NEXT: ret 23 %1 = mul i32 %a, %b 24 %2 = sub i32 4, %1 25 ret i32 %2 26} 27 28; bugpoint reduced test case. This only tests that we pass the MI verifier. 29define void @mul_add_imm2() { 30; CHECK-ISEL-LABEL: mul_add_imm2: 31; CHECK-ISEL: ; %bb.0: ; %entry 32; CHECK-ISEL-NEXT: mov w8, #1 ; =0x1 33; CHECK-ISEL-NEXT: LBB2_1: ; %for.body8 34; CHECK-ISEL-NEXT: ; =>This Inner Loop Header: Depth=1 35; CHECK-ISEL-NEXT: cbnz w8, LBB2_1 36; CHECK-ISEL-NEXT: ; %bb.2: ; %for.end20 37; CHECK-ISEL-NEXT: ret 38; 39; CHECK-FAST-LABEL: mul_add_imm2: 40; CHECK-FAST: ; %bb.0: ; %entry 41; CHECK-FAST-NEXT: mov x8, #-3 ; =0xfffffffffffffffd 42; CHECK-FAST-NEXT: mov x9, #-3 ; =0xfffffffffffffffd 43; CHECK-FAST-NEXT: madd x8, x8, x8, x9 44; CHECK-FAST-NEXT: mov x9, #45968 ; =0xb390 45; CHECK-FAST-NEXT: movk x9, #48484, lsl #16 46; CHECK-FAST-NEXT: movk x9, #323, lsl #32 47; CHECK-FAST-NEXT: LBB2_1: ; %for.body8 48; CHECK-FAST-NEXT: ; =>This Inner Loop Header: Depth=1 49; CHECK-FAST-NEXT: cmp x8, x9 50; CHECK-FAST-NEXT: b.lt LBB2_1 51; CHECK-FAST-NEXT: ; %bb.2: ; %for.end20 52; CHECK-FAST-NEXT: ret 53entry: 54 br label %for.body 55for.body: 56 br i1 undef, label %for.body, label %for.body8 57for.body8: 58 %0 = mul i64 undef, -3 59 %mul1971 = add i64 %0, -3 60 %cmp7 = icmp slt i64 %mul1971, 1390451930000 61 br i1 %cmp7, label %for.body8, label %for.end20 62for.end20: 63 ret void 64} 65 66define i32 @add1_mul_val1(i32 %a, i32 %b) { 67; CHECK-ISEL-LABEL: add1_mul_val1: 68; CHECK-ISEL: ; %bb.0: 69; CHECK-ISEL-NEXT: madd w0, w1, w0, w1 70; CHECK-ISEL-NEXT: ret 71; 72; CHECK-FAST-LABEL: add1_mul_val1: 73; CHECK-FAST: ; %bb.0: 74; CHECK-FAST-NEXT: add w8, w0, #1 75; CHECK-FAST-NEXT: mul w0, w8, w1 76; CHECK-FAST-NEXT: ret 77 %1 = add i32 %a, 1 78 %2 = mul i32 %1, %b 79 ret i32 %2 80} 81 82define i32 @add1_mul_val2(i32 %a, i32 %b) { 83; CHECK-ISEL-LABEL: add1_mul_val2: 84; CHECK-ISEL: ; %bb.0: 85; CHECK-ISEL-NEXT: madd w0, w0, w1, w0 86; CHECK-ISEL-NEXT: ret 87; 88; CHECK-FAST-LABEL: add1_mul_val2: 89; CHECK-FAST: ; %bb.0: 90; CHECK-FAST-NEXT: add w8, w1, #1 91; CHECK-FAST-NEXT: mul w0, w0, w8 92; CHECK-FAST-NEXT: ret 93 %1 = add i32 %b, 1 94 %2 = mul i32 %a, %1 95 ret i32 %2 96} 97 98define i64 @add1_mul_val3(i64 %a, i64 %b) { 99; CHECK-ISEL-LABEL: add1_mul_val3: 100; CHECK-ISEL: ; %bb.0: 101; CHECK-ISEL-NEXT: madd x0, x0, x1, x0 102; CHECK-ISEL-NEXT: ret 103; 104; CHECK-FAST-LABEL: add1_mul_val3: 105; CHECK-FAST: ; %bb.0: 106; CHECK-FAST-NEXT: add x8, x1, #1 107; CHECK-FAST-NEXT: mul x0, x0, x8 108; CHECK-FAST-NEXT: ret 109 %1 = add i64 %b, 1 110 %2 = mul i64 %a, %1 111 ret i64 %2 112} 113 114define i64 @add1_mul_val4(i64 %a, i64 %b, i64 %c) { 115; CHECK-ISEL-LABEL: add1_mul_val4: 116; CHECK-ISEL: ; %bb.0: 117; CHECK-ISEL-NEXT: add x8, x0, x2 118; CHECK-ISEL-NEXT: madd x0, x8, x1, x8 119; CHECK-ISEL-NEXT: ret 120; 121; CHECK-FAST-LABEL: add1_mul_val4: 122; CHECK-FAST: ; %bb.0: 123; CHECK-FAST-NEXT: add x8, x0, x2 124; CHECK-FAST-NEXT: add x9, x1, #1 125; CHECK-FAST-NEXT: mul x0, x8, x9 126; CHECK-FAST-NEXT: ret 127 %1 = add i64 %a, %c 128 %2 = add i64 %b, 1 129 %3 = mul i64 %1, %2 130 ret i64 %3 131} 132 133define i32 @sub1_mul_val1(i32 %a, i32 %b) { 134; CHECK-ISEL-LABEL: sub1_mul_val1: 135; CHECK-ISEL: ; %bb.0: 136; CHECK-ISEL-NEXT: msub w0, w1, w0, w1 137; CHECK-ISEL-NEXT: ret 138; 139; CHECK-FAST-LABEL: sub1_mul_val1: 140; CHECK-FAST: ; %bb.0: 141; CHECK-FAST-NEXT: mov w8, #1 ; =0x1 142; CHECK-FAST-NEXT: sub w8, w8, w0 143; CHECK-FAST-NEXT: mul w0, w8, w1 144; CHECK-FAST-NEXT: ret 145 %1 = sub i32 1, %a 146 %2 = mul i32 %1, %b 147 ret i32 %2 148} 149 150define i32 @sub1_mul_val2(i32 %a, i32 %b) { 151; CHECK-ISEL-LABEL: sub1_mul_val2: 152; CHECK-ISEL: ; %bb.0: 153; CHECK-ISEL-NEXT: msub w0, w0, w1, w0 154; CHECK-ISEL-NEXT: ret 155; 156; CHECK-FAST-LABEL: sub1_mul_val2: 157; CHECK-FAST: ; %bb.0: 158; CHECK-FAST-NEXT: mov w8, #1 ; =0x1 159; CHECK-FAST-NEXT: sub w8, w8, w1 160; CHECK-FAST-NEXT: mul w0, w0, w8 161; CHECK-FAST-NEXT: ret 162 %1 = sub i32 1, %b 163 %2 = mul i32 %a, %1 164 ret i32 %2 165} 166 167define i64 @sub1_mul_val3(i64 %a, i64 %b) { 168; CHECK-ISEL-LABEL: sub1_mul_val3: 169; CHECK-ISEL: ; %bb.0: 170; CHECK-ISEL-NEXT: msub x0, x0, x1, x0 171; CHECK-ISEL-NEXT: ret 172; 173; CHECK-FAST-LABEL: sub1_mul_val3: 174; CHECK-FAST: ; %bb.0: 175; CHECK-FAST-NEXT: mov x8, #1 ; =0x1 176; CHECK-FAST-NEXT: sub x8, x8, x1 177; CHECK-FAST-NEXT: mul x0, x0, x8 178; CHECK-FAST-NEXT: ret 179 %1 = sub i64 1, %b 180 %2 = mul i64 %a, %1 181 ret i64 %2 182} 183 184define i64 @sub1_mul_val4(i64 %a, i64 %b) { 185; CHECK-ISEL-LABEL: sub1_mul_val4: 186; CHECK-ISEL: ; %bb.0: 187; CHECK-ISEL-NEXT: sub x8, x0, #1 188; CHECK-ISEL-NEXT: msub x0, x8, x1, x8 189; CHECK-ISEL-NEXT: ret 190; 191; CHECK-FAST-LABEL: sub1_mul_val4: 192; CHECK-FAST: ; %bb.0: 193; CHECK-FAST-NEXT: mov x8, #1 ; =0x1 194; CHECK-FAST-NEXT: sub x9, x0, #1 195; CHECK-FAST-NEXT: sub x8, x8, x1 196; CHECK-FAST-NEXT: mul x0, x9, x8 197; CHECK-FAST-NEXT: ret 198 %1 = sub i64 %a, 1 199 %2 = sub i64 1, %b 200 %3 = mul i64 %1, %2 201 ret i64 %3 202} 203 204