1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s 3 4; When lowering the LLVM IR to MIR, transient COPY instructions are generated 5; to copy parameters from physical registers to virtual registers. Wrong 6; handling of transient instructions in MachineCombiner can fail the forllowing 7; transformation. 8; A - (B + C) ==> (A - B) - C 9 10; 32 bit version. 11define i32 @test1(i32 %a, i32 %b, i32 %c) { 12; CHECK-LABEL: test1: 13; CHECK: // %bb.0: // %entry 14; CHECK-NEXT: eor w8, w1, w0, lsl #8 15; CHECK-NEXT: sub w9, w2, w0 16; CHECK-NEXT: sub w9, w9, w8 17; CHECK-NEXT: eor w0, w9, w8, asr #13 18; CHECK-NEXT: ret 19entry: 20 %shl = shl i32 %a, 8 21 %xor = xor i32 %shl, %b 22 %add = add i32 %xor, %a 23 %sub = sub i32 %c, %add 24 %shr = ashr i32 %xor, 13 25 %xor2 = xor i32 %sub, %shr 26 ret i32 %xor2 27} 28 29; 64 bit version. 30define i64 @test2(i64 %a, i64 %b, i64 %c) { 31; CHECK-LABEL: test2: 32; CHECK: // %bb.0: // %entry 33; CHECK-NEXT: eor x8, x1, x0, lsl #8 34; CHECK-NEXT: sub x9, x2, x0 35; CHECK-NEXT: sub x9, x9, x8 36; CHECK-NEXT: eor x0, x9, x8, asr #13 37; CHECK-NEXT: ret 38entry: 39 %shl = shl i64 %a, 8 40 %xor = xor i64 %shl, %b 41 %add = add i64 %xor, %a 42 %sub = sub i64 %c, %add 43 %shr = ashr i64 %xor, 13 44 %xor2 = xor i64 %sub, %shr 45 ret i64 %xor2 46} 47