1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s 3 4; The test cases in this file check following transformation if the right form 5; can reduce latency. 6; A - (B + C) ==> (A - B) - C 7 8; 32 bit version. 9define i32 @test1(i32 %a, i32 %b, i32 %c) { 10; CHECK-LABEL: test1: 11; CHECK: // %bb.0: // %entry 12; CHECK-NEXT: add w8, w0, #100 13; CHECK-NEXT: orr w9, w2, #0x80 14; CHECK-NEXT: eor w10, w1, w8, lsl #8 15; CHECK-NEXT: sub w8, w9, w8 16; CHECK-NEXT: sub w8, w8, w10 17; CHECK-NEXT: eor w0, w8, w10, asr #13 18; CHECK-NEXT: ret 19entry: 20 %c1 = or i32 %c, 128 21 %a1 = add i32 %a, 100 22 %shl = shl i32 %a1, 8 23 %xor = xor i32 %shl, %b 24 %add = add i32 %xor, %a1 25 %sub = sub i32 %c1, %add 26 %shr = ashr i32 %xor, 13 27 %xor2 = xor i32 %sub, %shr 28 ret i32 %xor2 29} 30 31; 64 bit version. 32define i64 @test2(i64 %a, i64 %b, i64 %c) { 33; CHECK-LABEL: test2: 34; CHECK: // %bb.0: // %entry 35; CHECK-NEXT: add x8, x0, #100 36; CHECK-NEXT: orr x9, x2, #0x80 37; CHECK-NEXT: eor x10, x1, x8, lsl #8 38; CHECK-NEXT: sub x8, x9, x8 39; CHECK-NEXT: sub x8, x8, x10 40; CHECK-NEXT: eor x0, x8, x10, asr #13 41; CHECK-NEXT: ret 42entry: 43 %c1 = or i64 %c, 128 44 %a1 = add i64 %a, 100 45 %shl = shl i64 %a1, 8 46 %xor = xor i64 %shl, %b 47 %add = add i64 %xor, %a1 48 %sub = sub i64 %c1, %add 49 %shr = ashr i64 %xor, 13 50 %xor2 = xor i64 %sub, %shr 51 ret i64 %xor2 52} 53 54; Negative test. The right form can't reduce latency. 55define i32 @test3(i32 %a, i32 %b, i32 %c) { 56; CHECK-LABEL: test3: 57; CHECK: // %bb.0: // %entry 58; CHECK-NEXT: add w8, w0, #100 59; CHECK-NEXT: orr w9, w2, #0x80 60; CHECK-NEXT: eor w10, w1, w8, lsl #8 61; CHECK-NEXT: add w8, w9, w8 62; CHECK-NEXT: sub w8, w10, w8 63; CHECK-NEXT: eor w0, w8, w10, asr #13 64; CHECK-NEXT: ret 65entry: 66 %c1 = or i32 %c, 128 67 %a1 = add i32 %a, 100 68 %shl = shl i32 %a1, 8 69 %xor = xor i32 %shl, %b 70 %add = add i32 %c1, %a1 71 %sub = sub i32 %xor, %add 72 %shr = ashr i32 %xor, 13 73 %xor2 = xor i32 %sub, %shr 74 ret i32 %xor2 75} 76 77