1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -run-pass=machine-combiner -o - -simplify-mir -mtriple=aarch64-unknown-linux-gnu -mattr=+fullfp16 -verify-machineinstrs %s | FileCheck %s 3--- | 4 ; ModuleID = 'lit.ll' 5 source_filename = "lit.ll" 6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 7 target triple = "aarch64-unknown-linux-gnu" 8 9 define void @indexed_2s(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 { 10 entry: 11 %shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer 12 br label %for.cond 13 14 for.cond: ; preds = %for.cond, %entry 15 %mul = fmul <2 x float> %mu, %shuffle 16 %add = fadd <2 x float> %mul, %ad 17 store <2 x float> %add, ptr %ret, align 16 18 br label %for.cond 19 } 20 21 define void @indexed_2s_rev(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 { 22 entry: 23 %shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer 24 br label %for.cond 25 26 for.cond: ; preds = %for.cond, %entry 27 %mul = fmul <2 x float> %shuffle, %mu 28 %add = fadd <2 x float> %mul, %ad 29 store <2 x float> %add, ptr %ret, align 16 30 br label %for.cond 31 } 32 33 define void @indexed_2d(<2 x double> %shuf, <2 x double> %mu, <2 x double> %ad, ptr %ret) #0 { 34 entry: 35 %shuffle = shufflevector <2 x double> %shuf, <2 x double> undef, <2 x i32> zeroinitializer 36 br label %for.cond 37 38 for.cond: ; preds = %for.cond, %entry 39 %mul = fmul <2 x double> %mu, %shuffle 40 %add = fadd <2 x double> %mul, %ad 41 store <2 x double> %add, ptr %ret, align 16 42 br label %for.cond 43 } 44 45 define void @indexed_4s(<4 x float> %shuf, <4 x float> %mu, <4 x float> %ad, ptr %ret) #0 { 46 entry: 47 %shuffle = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> zeroinitializer 48 br label %for.cond 49 50 for.cond: ; preds = %for.cond, %entry 51 %mul = fmul <4 x float> %mu, %shuffle 52 %add = fadd <4 x float> %mul, %ad 53 store <4 x float> %add, ptr %ret, align 16 54 br label %for.cond 55 } 56 57 define void @indexed_4h(<4 x half> %shuf, <4 x half> %mu, <4 x half> %ad, ptr %ret) #0 { 58 entry: 59 %shuffle = shufflevector <4 x half> %shuf, <4 x half> undef, <4 x i32> zeroinitializer 60 br label %for.cond 61 62 for.cond: 63 %mul = fmul <4 x half> %mu, %shuffle 64 %add = fadd <4 x half> %mul, %ad 65 store <4 x half> %add, ptr %ret, align 16 66 br label %for.cond 67 } 68 69 define void @indexed_8h(<8 x half> %shuf, <8 x half> %mu, <8 x half> %ad, ptr %ret) #0 { 70 entry: 71 %shuffle = shufflevector <8 x half> %shuf, <8 x half> undef, <8 x i32> zeroinitializer 72 br label %for.cond 73 74 for.cond: 75 %mul = fmul <8 x half> %mu, %shuffle 76 %add = fadd <8 x half> %mul, %ad 77 store <8 x half> %add, ptr %ret, align 16 78 br label %for.cond 79 } 80 81 define void @kill_state(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, 82 ptr %ret, ptr %ret2, float %f) #0 { 83 entry: 84 %zero_elem = extractelement <2 x float> %shuf, i32 0 85 %ins = insertelement <2 x float> undef, float %zero_elem, i32 0 86 %shuffle = shufflevector <2 x float> %ins, <2 x float> undef, <2 x i32> zeroinitializer 87 %ins2 = insertelement <2 x float> %ins, float %f, i32 1 88 store <2 x float> %ins2, ptr %ret2, align 8 89 br label %for.cond 90 91 for.cond: ; preds = %for.cond, %entry 92 %mul = fmul <2 x float> %mu, %shuffle 93 %add = fadd <2 x float> %mul, %ad 94 store <2 x float> %add, ptr %ret, align 16 95 br label %for.cond 96 } 97 98 define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 { 99 unreachable 100 } 101 102 attributes #0 = { "target-cpu"="cortex-a57" } 103 104... 105--- 106name: indexed_2s 107alignment: 16 108tracksRegLiveness: true 109registers: 110 - { id: 0, class: fpr64 } 111 - { id: 1, class: fpr64 } 112 - { id: 2, class: fpr64 } 113 - { id: 3, class: fpr64 } 114 - { id: 4, class: gpr64common } 115 - { id: 5, class: fpr64 } 116 - { id: 6, class: fpr64 } 117 - { id: 7, class: fpr128 } 118 - { id: 8, class: fpr128 } 119 - { id: 9, class: fpr64 } 120 - { id: 10, class: fpr64 } 121liveins: 122 - { reg: '$d0', virtual-reg: '%1' } 123 - { reg: '$d1', virtual-reg: '%2' } 124 - { reg: '$d2', virtual-reg: '%3' } 125 - { reg: '$x0', virtual-reg: '%4' } 126frameInfo: 127 maxAlignment: 1 128 maxCallFrameSize: 0 129machineFunctionInfo: {} 130body: | 131 ; CHECK-LABEL: name: indexed_2s 132 ; CHECK: bb.0.entry: 133 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0 134 ; CHECK-NEXT: {{ $}} 135 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 136 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2 137 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 138 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0 139 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 140 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub 141 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]] 142 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]] 143 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0 144 ; CHECK-NEXT: {{ $}} 145 ; CHECK-NEXT: bb.1.for.cond: 146 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr 147 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr 148 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16) 149 ; CHECK-NEXT: B %bb.1 150 bb.0.entry: 151 liveins: $d0, $d1, $d2, $x0 152 153 %4:gpr64common = COPY $x0 154 %3:fpr64 = COPY $d2 155 %2:fpr64 = COPY $d1 156 %1:fpr64 = COPY $d0 157 %8:fpr128 = IMPLICIT_DEF 158 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub 159 %6:fpr64 = COPY %3 160 %5:fpr64 = COPY %2 161 %0:fpr64 = DUPv2i32lane killed %7, 0 162 163 bb.1.for.cond: 164 %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr 165 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr 166 STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16) 167 B %bb.1 168 169... 170--- 171name: indexed_2s_rev 172alignment: 16 173tracksRegLiveness: true 174registers: 175 - { id: 0, class: fpr64 } 176 - { id: 1, class: fpr64 } 177 - { id: 2, class: fpr64 } 178 - { id: 3, class: fpr64 } 179 - { id: 4, class: gpr64common } 180 - { id: 5, class: fpr64 } 181 - { id: 6, class: fpr64 } 182 - { id: 7, class: fpr128 } 183 - { id: 8, class: fpr128 } 184 - { id: 9, class: fpr64 } 185 - { id: 10, class: fpr64 } 186liveins: 187 - { reg: '$d0', virtual-reg: '%1' } 188 - { reg: '$d1', virtual-reg: '%2' } 189 - { reg: '$d2', virtual-reg: '%3' } 190 - { reg: '$x0', virtual-reg: '%4' } 191frameInfo: 192 maxAlignment: 1 193 maxCallFrameSize: 0 194machineFunctionInfo: {} 195body: | 196 ; CHECK-LABEL: name: indexed_2s_rev 197 ; CHECK: bb.0.entry: 198 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0 199 ; CHECK-NEXT: {{ $}} 200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 201 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2 202 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 203 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0 204 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 205 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub 206 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]] 207 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]] 208 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0 209 ; CHECK-NEXT: {{ $}} 210 ; CHECK-NEXT: bb.1.for.cond: 211 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr 212 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr 213 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16) 214 ; CHECK-NEXT: B %bb.1 215 bb.0.entry: 216 liveins: $d0, $d1, $d2, $x0 217 218 %4:gpr64common = COPY $x0 219 %3:fpr64 = COPY $d2 220 %2:fpr64 = COPY $d1 221 %1:fpr64 = COPY $d0 222 %8:fpr128 = IMPLICIT_DEF 223 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub 224 %6:fpr64 = COPY %3 225 %5:fpr64 = COPY %2 226 %0:fpr64 = DUPv2i32lane killed %7, 0 227 228 bb.1.for.cond: 229 %9:fpr64 = FMULv2f32 %0, %5, implicit $fpcr 230 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr 231 STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16) 232 B %bb.1 233 234... 235--- 236name: indexed_2d 237alignment: 16 238tracksRegLiveness: true 239registers: 240 - { id: 0, class: fpr128 } 241 - { id: 1, class: fpr128 } 242 - { id: 2, class: fpr128 } 243 - { id: 3, class: fpr128 } 244 - { id: 4, class: gpr64common } 245 - { id: 5, class: fpr128 } 246 - { id: 6, class: fpr128 } 247 - { id: 7, class: fpr128 } 248 - { id: 8, class: fpr128 } 249liveins: 250 - { reg: '$q0', virtual-reg: '%1' } 251 - { reg: '$q1', virtual-reg: '%2' } 252 - { reg: '$q2', virtual-reg: '%3' } 253 - { reg: '$x0', virtual-reg: '%4' } 254frameInfo: 255 maxAlignment: 1 256 maxCallFrameSize: 0 257machineFunctionInfo: {} 258body: | 259 ; CHECK-LABEL: name: indexed_2d 260 ; CHECK: bb.0.entry: 261 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0 262 ; CHECK-NEXT: {{ $}} 263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 264 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2 265 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1 266 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0 267 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]] 268 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]] 269 ; CHECK-NEXT: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY3]], 0 270 ; CHECK-NEXT: {{ $}} 271 ; CHECK-NEXT: bb.1.for.cond: 272 ; CHECK-NEXT: [[FMULv2i64_indexed:%[0-9]+]]:fpr128 = FMULv2i64_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr 273 ; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 killed [[FMULv2i64_indexed]], [[COPY4]], implicit $fpcr 274 ; CHECK-NEXT: STRQui killed [[FADDv2f64_]], [[COPY]], 0 :: (store (s128) into %ir.ret) 275 ; CHECK-NEXT: B %bb.1 276 bb.0.entry: 277 liveins: $q0, $q1, $q2, $x0 278 279 %4:gpr64common = COPY $x0 280 %3:fpr128 = COPY $q2 281 %2:fpr128 = COPY $q1 282 %1:fpr128 = COPY $q0 283 %6:fpr128 = COPY %3 284 %5:fpr128 = COPY %2 285 %0:fpr128 = DUPv2i64lane %1, 0 286 287 bb.1.for.cond: 288 %7:fpr128 = FMULv2f64 %5, %0, implicit $fpcr 289 %8:fpr128 = FADDv2f64 killed %7, %6, implicit $fpcr 290 STRQui killed %8, %4, 0 :: (store 16 into %ir.ret) 291 B %bb.1 292 293... 294--- 295name: indexed_4s 296alignment: 16 297tracksRegLiveness: true 298registers: 299 - { id: 0, class: fpr128 } 300 - { id: 1, class: fpr128 } 301 - { id: 2, class: fpr128 } 302 - { id: 3, class: fpr128 } 303 - { id: 4, class: gpr64common } 304 - { id: 5, class: fpr128 } 305 - { id: 6, class: fpr128 } 306 - { id: 7, class: fpr128 } 307 - { id: 8, class: fpr128 } 308liveins: 309 - { reg: '$q0', virtual-reg: '%1' } 310 - { reg: '$q1', virtual-reg: '%2' } 311 - { reg: '$q2', virtual-reg: '%3' } 312 - { reg: '$x0', virtual-reg: '%4' } 313frameInfo: 314 maxAlignment: 1 315 maxCallFrameSize: 0 316machineFunctionInfo: {} 317body: | 318 ; CHECK-LABEL: name: indexed_4s 319 ; CHECK: bb.0.entry: 320 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0 321 ; CHECK-NEXT: {{ $}} 322 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 323 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2 324 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1 325 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0 326 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]] 327 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]] 328 ; CHECK-NEXT: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY3]], 0 329 ; CHECK-NEXT: {{ $}} 330 ; CHECK-NEXT: bb.1.for.cond: 331 ; CHECK-NEXT: [[FMULv4i32_indexed:%[0-9]+]]:fpr128 = FMULv4i32_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr 332 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 killed [[FMULv4i32_indexed]], [[COPY4]], implicit $fpcr 333 ; CHECK-NEXT: STRQui killed [[FADDv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.ret) 334 ; CHECK-NEXT: B %bb.1 335 bb.0.entry: 336 liveins: $q0, $q1, $q2, $x0 337 338 %4:gpr64common = COPY $x0 339 %3:fpr128 = COPY $q2 340 %2:fpr128 = COPY $q1 341 %1:fpr128 = COPY $q0 342 %6:fpr128 = COPY %3 343 %5:fpr128 = COPY %2 344 %0:fpr128 = DUPv4i32lane %1, 0 345 346 bb.1.for.cond: 347 %7:fpr128 = FMULv4f32 %5, %0, implicit $fpcr 348 %8:fpr128 = FADDv4f32 killed %7, %6, implicit $fpcr 349 STRQui killed %8, %4, 0 :: (store 16 into %ir.ret) 350 B %bb.1 351 352... 353--- 354name: indexed_4h 355alignment: 16 356tracksRegLiveness: true 357registers: 358 - { id: 0, class: fpr64 } 359 - { id: 1, class: fpr64 } 360 - { id: 2, class: fpr64 } 361 - { id: 3, class: fpr64 } 362 - { id: 4, class: gpr64common } 363 - { id: 5, class: fpr128 } 364 - { id: 6, class: fpr128 } 365 - { id: 7, class: fpr64 } 366 - { id: 8, class: fpr64 } 367liveins: 368 - { reg: '$d0', virtual-reg: '%1' } 369 - { reg: '$d1', virtual-reg: '%2' } 370 - { reg: '$d2', virtual-reg: '%3' } 371 - { reg: '$x0', virtual-reg: '%4' } 372frameInfo: 373 maxAlignment: 1 374 maxCallFrameSize: 0 375machineFunctionInfo: {} 376body: | 377 ; CHECK-LABEL: name: indexed_4h 378 ; CHECK: bb.0.entry: 379 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0 380 ; CHECK-NEXT: {{ $}} 381 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 382 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2 383 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 384 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0 385 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 386 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128_lo = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub 387 ; CHECK-NEXT: [[DUPv4i16lane:%[0-9]+]]:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0 388 ; CHECK-NEXT: {{ $}} 389 ; CHECK-NEXT: bb.1.for.cond: 390 ; CHECK-NEXT: [[FMULv4i16_indexed:%[0-9]+]]:fpr64 = FMULv4i16_indexed [[COPY2]], [[INSERT_SUBREG]], 0, implicit $fpcr 391 ; CHECK-NEXT: [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 killed [[FMULv4i16_indexed]], [[COPY1]], implicit $fpcr 392 ; CHECK-NEXT: STRDui killed [[FADDv4f16_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16) 393 ; CHECK-NEXT: B %bb.1 394 bb.0.entry: 395 liveins: $d0, $d1, $d2, $x0 396 397 %4:gpr64common = COPY $x0 398 %3:fpr64 = COPY $d2 399 %2:fpr64 = COPY $d1 400 %1:fpr64 = COPY $d0 401 %6:fpr128 = IMPLICIT_DEF 402 %5:fpr128 = INSERT_SUBREG %6, %1, %subreg.dsub 403 %0:fpr64 = DUPv4i16lane killed %5, 0 404 405 bb.1.for.cond: 406 %7:fpr64 = FMULv4f16 %2, %0, implicit $fpcr 407 %8:fpr64 = FADDv4f16 killed %7, %3, implicit $fpcr 408 STRDui killed %8, %4, 0 :: (store 8 into %ir.ret, align 16) 409 B %bb.1 410 411... 412--- 413name: indexed_8h 414alignment: 16 415tracksRegLiveness: true 416registers: 417 - { id: 0, class: fpr128 } 418 - { id: 1, class: fpr128 } 419 - { id: 2, class: fpr128 } 420 - { id: 3, class: fpr128 } 421 - { id: 4, class: gpr64common } 422 - { id: 5, class: fpr128 } 423 - { id: 6, class: fpr128 } 424liveins: 425 - { reg: '$q0', virtual-reg: '%1' } 426 - { reg: '$q1', virtual-reg: '%2' } 427 - { reg: '$q2', virtual-reg: '%3' } 428 - { reg: '$x0', virtual-reg: '%4' } 429frameInfo: 430 maxAlignment: 1 431 maxCallFrameSize: 0 432machineFunctionInfo: {} 433body: | 434 ; CHECK-LABEL: name: indexed_8h 435 ; CHECK: bb.0.entry: 436 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0 437 ; CHECK-NEXT: {{ $}} 438 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 439 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2 440 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1 441 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128_lo = COPY $q0 442 ; CHECK-NEXT: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY3]], 0 443 ; CHECK-NEXT: {{ $}} 444 ; CHECK-NEXT: bb.1.for.cond: 445 ; CHECK-NEXT: [[FMULv8i16_indexed:%[0-9]+]]:fpr128 = FMULv8i16_indexed [[COPY2]], [[COPY3]], 0, implicit $fpcr 446 ; CHECK-NEXT: [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 killed [[FMULv8i16_indexed]], [[COPY1]], implicit $fpcr 447 ; CHECK-NEXT: STRQui killed [[FADDv8f16_]], [[COPY]], 0 :: (store (s128) into %ir.ret) 448 ; CHECK-NEXT: B %bb.1 449 bb.0.entry: 450 liveins: $q0, $q1, $q2, $x0 451 452 %4:gpr64common = COPY $x0 453 %3:fpr128 = COPY $q2 454 %2:fpr128 = COPY $q1 455 %1:fpr128 = COPY $q0 456 %0:fpr128 = DUPv8i16lane %1, 0 457 458 bb.1.for.cond: 459 %5:fpr128 = FMULv8f16 %2, %0, implicit $fpcr 460 %6:fpr128 = FADDv8f16 killed %5, %3, implicit $fpcr 461 STRQui killed %6, %4, 0 :: (store 16 into %ir.ret) 462 B %bb.1 463 464... 465--- 466name: kill_state 467alignment: 16 468tracksRegLiveness: true 469registers: 470 - { id: 0, class: fpr64 } 471 - { id: 1, class: fpr64 } 472 - { id: 2, class: fpr64 } 473 - { id: 3, class: fpr64 } 474 - { id: 4, class: gpr64common } 475 - { id: 5, class: gpr64common } 476 - { id: 6, class: fpr32 } 477 - { id: 7, class: fpr64 } 478 - { id: 8, class: fpr64 } 479 - { id: 9, class: fpr128 } 480 - { id: 10, class: fpr128 } 481 - { id: 11, class: fpr128 } 482 - { id: 12, class: fpr128 } 483 - { id: 13, class: fpr128 } 484 - { id: 14, class: fpr64 } 485 - { id: 15, class: fpr64 } 486 - { id: 16, class: fpr64 } 487liveins: 488 - { reg: '$d0', virtual-reg: '%1' } 489 - { reg: '$d1', virtual-reg: '%2' } 490 - { reg: '$d2', virtual-reg: '%3' } 491 - { reg: '$x0', virtual-reg: '%4' } 492 - { reg: '$x1', virtual-reg: '%5' } 493 - { reg: '$s3', virtual-reg: '%6' } 494frameInfo: 495 maxAlignment: 1 496 maxCallFrameSize: 0 497machineFunctionInfo: {} 498body: | 499 ; CHECK-LABEL: name: kill_state 500 ; CHECK: bb.0.entry: 501 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0, $x1, $s3 502 ; CHECK-NEXT: {{ $}} 503 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s3 504 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1 505 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0 506 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d2 507 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY $d1 508 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY $d0 509 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 510 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.dsub 511 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[COPY3]] 512 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr64 = COPY [[COPY4]] 513 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0 514 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 515 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub 516 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, killed [[INSERT_SUBREG1]], 0 517 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub 518 ; CHECK-NEXT: STRDui killed [[COPY8]], [[COPY1]], 0 :: (store (s64) into %ir.ret2) 519 ; CHECK-NEXT: {{ $}} 520 ; CHECK-NEXT: bb.1.for.cond: 521 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY7]], [[INSERT_SUBREG]], 0, implicit $fpcr 522 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY6]], implicit $fpcr 523 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY2]], 0 :: (store (s64) into %ir.ret, align 16) 524 ; CHECK-NEXT: B %bb.1 525 bb.0.entry: 526 liveins: $d0, $d1, $d2, $x0, $x1, $s3 527 528 %6:fpr32 = COPY $s3 529 %5:gpr64common = COPY $x1 530 %4:gpr64common = COPY $x0 531 %3:fpr64 = COPY $d2 532 %2:fpr64 = COPY $d1 533 %1:fpr64 = COPY $d0 534 %10:fpr128 = IMPLICIT_DEF 535 %9:fpr128 = INSERT_SUBREG %10, %1, %subreg.dsub 536 %8:fpr64 = COPY %3 537 %7:fpr64 = COPY %2 538 %0:fpr64 = DUPv2i32lane %9, 0 539 %12:fpr128 = IMPLICIT_DEF 540 %11:fpr128 = INSERT_SUBREG %12, %6, %subreg.ssub 541 %13:fpr128 = INSvi32lane killed %9, 1, killed %11, 0 542 %14:fpr64 = COPY %13.dsub 543 STRDui killed %14, %5, 0 :: (store (s64) into %ir.ret2) 544 545 bb.1.for.cond: 546 %15:fpr64 = FMULv2f32 %7, %0, implicit $fpcr 547 %16:fpr64 = FADDv2f32 killed %15, %8, implicit $fpcr 548 STRDui killed %16, %4, 0 :: (store (s64) into %ir.ret, align 16) 549 B %bb.1 550 551... 552--- 553name: extracopy 554alignment: 16 555tracksRegLiveness: true 556registers: 557 - { id: 0, class: fpr64 } 558 - { id: 1, class: fpr64 } 559 - { id: 2, class: fpr64 } 560 - { id: 3, class: fpr64 } 561 - { id: 4, class: gpr64common } 562 - { id: 5, class: fpr64 } 563 - { id: 6, class: fpr64 } 564 - { id: 7, class: fpr128 } 565 - { id: 8, class: fpr128 } 566 - { id: 9, class: fpr64 } 567 - { id: 10, class: fpr64 } 568 - { id: 11, class: fpr64 } 569liveins: 570 - { reg: '$d0', virtual-reg: '%1' } 571 - { reg: '$d1', virtual-reg: '%2' } 572 - { reg: '$d2', virtual-reg: '%3' } 573 - { reg: '$x0', virtual-reg: '%4' } 574frameInfo: 575 maxAlignment: 1 576 maxCallFrameSize: 0 577machineFunctionInfo: {} 578body: | 579 ; CHECK-LABEL: name: extracopy 580 ; CHECK: bb.0: 581 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0 582 ; CHECK-NEXT: {{ $}} 583 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 584 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2 585 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 586 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0 587 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 588 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub 589 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]] 590 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]] 591 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0 592 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]] 593 ; CHECK-NEXT: {{ $}} 594 ; CHECK-NEXT: bb.1: 595 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr 596 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr 597 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16) 598 ; CHECK-NEXT: B %bb.1 599 bb.0: 600 liveins: $d0, $d1, $d2, $x0 601 602 %4:gpr64common = COPY $x0 603 %3:fpr64 = COPY $d2 604 %2:fpr64 = COPY $d1 605 %1:fpr64 = COPY $d0 606 %8:fpr128 = IMPLICIT_DEF 607 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub 608 %6:fpr64 = COPY %3 609 %5:fpr64 = COPY %2 610 %11:fpr64 = DUPv2i32lane killed %7, 0 611 %0:fpr64 = COPY %11 612 613 bb.1: 614 %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr 615 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr 616 STRDui killed %10, %4, 0 :: (store 8, align 16) 617 B %bb.1 618 619... 620