xref: /llvm-project/llvm/test/CodeGen/AArch64/logical-op-with-not.ll (revision e121c3d3f019b2020592db6a34d3a82ab811729f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
3
4define i64 @and_bic(i64 %0, i64 %1) {
5; CHECK-LABEL: and_bic:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mvn w8, w0
8; CHECK-NEXT:    orr x8, x8, #0xffffffffffff00ff
9; CHECK-NEXT:    and x0, x8, x1
10; CHECK-NEXT:    ret
11  %3 = and i64 %0, 65280
12  %4 = xor i64 %3, -1
13  %5 = and i64 %4, %1
14  ret i64 %5
15}
16
17define i64 @and_bic2(i32 %0, i64 %1) {
18; CHECK-LABEL: and_bic2:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    mvn w8, w0
21; CHECK-NEXT:    orr w8, w8, #0xffff00ff
22; CHECK-NEXT:    and x0, x8, x1
23; CHECK-NEXT:    ret
24  %3 = and i32 %0, 65280
25  %4 = xor i32 %3, -1
26  %5 = zext i32 %4 to i64
27  %6 = and i64 %5, %1
28  ret i64 %6
29}
30
31define i32 @and_bic3(i32 %0, i32 %1) {
32; CHECK-LABEL: and_bic3:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    mvn w8, w0
35; CHECK-NEXT:    orr w8, w8, #0xffff00ff
36; CHECK-NEXT:    and w0, w8, w1
37; CHECK-NEXT:    ret
38  %3 = and i32 %0, 65280
39  %4 = xor i32 %3, -1
40  %5 = and i32 %4, %1
41  ret i32 %5
42}
43
44define i64 @and_eon(i64 %0, i64 %1) {
45; CHECK-LABEL: and_eon:
46; CHECK:       // %bb.0:
47; CHECK-NEXT:    and x8, x0, #0xff00
48; CHECK-NEXT:    eon x0, x8, x1
49; CHECK-NEXT:    ret
50  %3 = and i64 %0, 65280
51  %4 = xor i64 %3, %1
52  %5 = xor i64 %4, -1
53  ret i64 %5
54}
55
56define i64 @and_eon2(i32 %0, i64 %1) {
57; CHECK-LABEL: and_eon2:
58; CHECK:       // %bb.0:
59; CHECK-NEXT:    mvn w8, w0
60; CHECK-NEXT:    orr w8, w8, #0xffff00ff
61; CHECK-NEXT:    eor x0, x8, x1
62; CHECK-NEXT:    ret
63  %3 = and i32 %0, 65280
64  %4 = xor i32 %3, -1
65  %5 = zext i32 %4 to i64
66  %6 = xor i64 %5, %1
67  ret i64 %6
68}
69
70define i32 @and_eon3(i32 %0, i32 %1) {
71; CHECK-LABEL: and_eon3:
72; CHECK:       // %bb.0:
73; CHECK-NEXT:    and w8, w0, #0xff00
74; CHECK-NEXT:    eon w0, w8, w1
75; CHECK-NEXT:    ret
76  %3 = and i32 %0, 65280
77  %4 = xor i32 %3, %1
78  %5 = xor i32 %4, -1
79  ret i32 %5
80}
81
82define i64 @and_orn(i64 %0, i64 %1) {
83; CHECK-LABEL: and_orn:
84; CHECK:       // %bb.0:
85; CHECK-NEXT:    orn w8, w1, w0
86; CHECK-NEXT:    orr x0, x8, #0xffffffffffff00ff
87; CHECK-NEXT:    ret
88  %3 = and i64 %0, 65280
89  %4 = xor i64 %3, -1
90  %5 = or i64 %4, %1
91  ret i64 %5
92}
93
94define i64 @and_orn2(i32 %0, i64 %1) {
95; CHECK-LABEL: and_orn2:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    mvn w8, w0
98; CHECK-NEXT:    orr w8, w8, #0xffff00ff
99; CHECK-NEXT:    orr x0, x8, x1
100; CHECK-NEXT:    ret
101  %3 = and i32 %0, 65280
102  %4 = xor i32 %3, -1
103  %5 = zext i32 %4 to i64
104  %6 = or i64 %5, %1
105  ret i64 %6
106}
107
108define i32 @and_orn3(i32 %0, i32 %1) {
109; CHECK-LABEL: and_orn3:
110; CHECK:       // %bb.0:
111; CHECK-NEXT:    orn w8, w1, w0
112; CHECK-NEXT:    orr w0, w8, #0xffff00ff
113; CHECK-NEXT:    ret
114  %3 = and i32 %0, 65280
115  %4 = xor i32 %3, -1
116  %5 = or i32 %4, %1
117  ret i32 %5
118}
119
120define i64 @_Z6or_bic(i64 %0, i64 %1) {
121; CHECK-LABEL: _Z6or_bic:
122; CHECK:       // %bb.0:
123; CHECK-NEXT:    bic x8, x1, x0
124; CHECK-NEXT:    and x0, x8, #0xffffffffffff00ff
125; CHECK-NEXT:    ret
126  %3 = and i64 %0, -65281
127  %4 = xor i64 %3, -65281
128  %5 = and i64 %4, %1
129  ret i64 %5
130}
131
132define i64 @or_bic2(i32 %0, i64 %1) {
133; CHECK-LABEL: or_bic2:
134; CHECK:       // %bb.0:
135; CHECK-NEXT:    mov w8, #-65281
136; CHECK-NEXT:    bic w8, w8, w0
137; CHECK-NEXT:    and x0, x8, x1
138; CHECK-NEXT:    ret
139  %3 = and i32 %0, -65281
140  %4 = xor i32 %3, -65281
141  %5 = zext i32 %4 to i64
142  %6 = and i64 %5, %1
143  ret i64 %6
144}
145
146define i32 @or_bic3(i32 %0, i32 %1) {
147; CHECK-LABEL: or_bic3:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    bic w8, w1, w0
150; CHECK-NEXT:    and w0, w8, #0xfffff000
151; CHECK-NEXT:    ret
152  %3 = and i32 %0, -4096
153  %4 = xor i32 %3, -4096
154  %5 = and i32 %4, %1
155  ret i32 %5
156}
157
158define i64 @_Z6or_orn(i64 %0, i64 %1) {
159; CHECK-LABEL: _Z6or_orn:
160; CHECK:       // %bb.0:
161; CHECK-NEXT:    mov x8, #-4096
162; CHECK-NEXT:    bic x8, x8, x0
163; CHECK-NEXT:    orr x0, x8, x1
164; CHECK-NEXT:    ret
165  %3 = and i64 %0, -4096
166  %4 = xor i64 %3, -4096
167  %5 = or i64 %4, %1
168  ret i64 %5
169}
170
171define i64 @or_orn2(i32 %0, i64 %1) {
172; CHECK-LABEL: or_orn2:
173; CHECK:       // %bb.0:
174; CHECK-NEXT:    mov w8, #-4096
175; CHECK-NEXT:    bic w8, w8, w0
176; CHECK-NEXT:    orr x0, x8, x1
177; CHECK-NEXT:    ret
178  %3 = and i32 %0, -4096
179  %4 = xor i32 %3, -4096
180  %5 = zext i32 %4 to i64
181  %6 = or i64 %5, %1
182  ret i64 %6
183}
184
185define i64 @or_orn3(i32 %0, i64 %1) {
186; CHECK-LABEL: or_orn3:
187; CHECK:       // %bb.0:
188; CHECK-NEXT:    mov w8, #-4096
189; CHECK-NEXT:    bic w8, w8, w0
190; CHECK-NEXT:    orr x0, x8, x1
191; CHECK-NEXT:    ret
192  %3 = and i32 %0, -4096
193  %4 = xor i32 %3, -4096
194  %5 = zext i32 %4 to i64
195  %6 = or i64 %5, %1
196  ret i64 %6
197}
198
199define i64 @_Z6or_eon(i64 %0, i64 %1) {
200; CHECK-LABEL: _Z6or_eon:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    and x8, x0, #0xfffffffffffff000
203; CHECK-NEXT:    eor x8, x8, x1
204; CHECK-NEXT:    eor x0, x8, #0xfffffffffffff000
205; CHECK-NEXT:    ret
206  %3 = and i64 %0, -4096
207  %4 = xor i64 %3, %1
208  %5 = xor i64 %4, -4096
209  ret i64 %5
210}
211
212define i64 @or_eon2(i32 %0, i64 %1) {
213; CHECK-LABEL: or_eon2:
214; CHECK:       // %bb.0:
215; CHECK-NEXT:    mov w8, #-4096
216; CHECK-NEXT:    bic w8, w8, w0
217; CHECK-NEXT:    eor x0, x8, x1
218; CHECK-NEXT:    ret
219  %3 = and i32 %0, -4096
220  %4 = xor i32 %3, -4096
221  %5 = zext i32 %4 to i64
222  %6 = xor i64 %5, %1
223  ret i64 %6
224}
225
226define i64 @or_eon3(i32 %0, i64 %1) {
227; CHECK-LABEL: or_eon3:
228; CHECK:       // %bb.0:
229; CHECK-NEXT:    mov w8, #-4096
230; CHECK-NEXT:    bic w8, w8, w0
231; CHECK-NEXT:    eor x0, x8, x1
232; CHECK-NEXT:    ret
233  %3 = and i32 %0, -4096
234  %4 = xor i32 %3, -4096
235  %5 = zext i32 %4 to i64
236  %6 = xor i64 %5, %1
237  ret i64 %6
238}
239