1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16 3; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16 4; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK-NOFP16 5; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK-FP16 6 7define i16 @testmhhs(half %x) { 8; CHECK-NOFP16-LABEL: testmhhs: 9; CHECK-NOFP16: // %bb.0: // %entry 10; CHECK-NOFP16-NEXT: fcvt s0, h0 11; CHECK-NOFP16-NEXT: frintx s0, s0 12; CHECK-NOFP16-NEXT: fcvtzs x0, s0 13; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x0 14; CHECK-NOFP16-NEXT: ret 15; 16; CHECK-FP16-LABEL: testmhhs: 17; CHECK-FP16: // %bb.0: // %entry 18; CHECK-FP16-NEXT: frintx h0, h0 19; CHECK-FP16-NEXT: fcvtzs x0, h0 20; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x0 21; CHECK-FP16-NEXT: ret 22entry: 23 %0 = tail call i64 @llvm.llrint.i64.f16(half %x) 24 %conv = trunc i64 %0 to i16 25 ret i16 %conv 26} 27 28define i32 @testmhws(half %x) { 29; CHECK-NOFP16-LABEL: testmhws: 30; CHECK-NOFP16: // %bb.0: // %entry 31; CHECK-NOFP16-NEXT: fcvt s0, h0 32; CHECK-NOFP16-NEXT: frintx s0, s0 33; CHECK-NOFP16-NEXT: fcvtzs x0, s0 34; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x0 35; CHECK-NOFP16-NEXT: ret 36; 37; CHECK-FP16-LABEL: testmhws: 38; CHECK-FP16: // %bb.0: // %entry 39; CHECK-FP16-NEXT: frintx h0, h0 40; CHECK-FP16-NEXT: fcvtzs x0, h0 41; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x0 42; CHECK-FP16-NEXT: ret 43entry: 44 %0 = tail call i64 @llvm.llrint.i64.f16(half %x) 45 %conv = trunc i64 %0 to i32 46 ret i32 %conv 47} 48 49define i64 @testmhxs(half %x) { 50; CHECK-NOFP16-LABEL: testmhxs: 51; CHECK-NOFP16: // %bb.0: // %entry 52; CHECK-NOFP16-NEXT: fcvt s0, h0 53; CHECK-NOFP16-NEXT: frintx s0, s0 54; CHECK-NOFP16-NEXT: fcvtzs x0, s0 55; CHECK-NOFP16-NEXT: ret 56; 57; CHECK-FP16-LABEL: testmhxs: 58; CHECK-FP16: // %bb.0: // %entry 59; CHECK-FP16-NEXT: frintx h0, h0 60; CHECK-FP16-NEXT: fcvtzs x0, h0 61; CHECK-FP16-NEXT: ret 62entry: 63 %0 = tail call i64 @llvm.llrint.i64.f16(half %x) 64 ret i64 %0 65} 66 67declare i64 @llvm.llrint.i64.f16(half) nounwind readnone 68