1; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s 2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s 3 4@var_8bit = dso_local global i8 0 5@var_16bit = dso_local global i16 0 6@var_32bit = dso_local global i32 0 7@var_64bit = dso_local global i64 0 8 9@var_float = dso_local global float 0.0 10@var_double = dso_local global double 0.0 11 12@varptr = dso_local global ptr null 13 14define dso_local void @ldst_8bit() { 15; CHECK-LABEL: ldst_8bit: 16 17; No architectural support for loads to 16-bit or 8-bit since we 18; promote i8 during lowering. 19 %addr_8bit = load ptr, ptr @varptr 20 21; match a sign-extending load 8-bit -> 32-bit 22 %addr_sext32 = getelementptr i8, ptr %addr_8bit, i64 -256 23 %val8_sext32 = load volatile i8, ptr %addr_sext32 24 %val32_signed = sext i8 %val8_sext32 to i32 25 store volatile i32 %val32_signed, ptr @var_32bit 26; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 27 28; match a zero-extending load volatile 8-bit -> 32-bit 29 %addr_zext32 = getelementptr i8, ptr %addr_8bit, i64 -12 30 %val8_zext32 = load volatile i8, ptr %addr_zext32 31 %val32_unsigned = zext i8 %val8_zext32 to i32 32 store volatile i32 %val32_unsigned, ptr @var_32bit 33; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12] 34 35; match an any-extending load volatile 8-bit -> 32-bit 36 %addr_anyext = getelementptr i8, ptr %addr_8bit, i64 -1 37 %val8_anyext = load volatile i8, ptr %addr_anyext 38 %newval8 = add i8 %val8_anyext, 1 39 store volatile i8 %newval8, ptr @var_8bit 40; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] 41 42; match a sign-extending load volatile 8-bit -> 64-bit 43 %addr_sext64 = getelementptr i8, ptr %addr_8bit, i64 -5 44 %val8_sext64 = load volatile i8, ptr %addr_sext64 45 %val64_signed = sext i8 %val8_sext64 to i64 46 store volatile i64 %val64_signed, ptr @var_64bit 47; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5] 48 49; match a zero-extending load volatile 8-bit -> 64-bit. 50; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits 51; of x0 so it's identical to load volatileing to 32-bits. 52 %addr_zext64 = getelementptr i8, ptr %addr_8bit, i64 -9 53 %val8_zext64 = load volatile i8, ptr %addr_zext64 54 %val64_unsigned = zext i8 %val8_zext64 to i64 55 store volatile i64 %val64_unsigned, ptr @var_64bit 56; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9] 57 58; truncating store volatile 32-bits to 8-bits 59 %addr_trunc32 = getelementptr i8, ptr %addr_8bit, i64 -256 60 %val32 = load volatile i32, ptr @var_32bit 61 %val8_trunc32 = trunc i32 %val32 to i8 62 store volatile i8 %val8_trunc32, ptr %addr_trunc32 63; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 64 65; truncating store volatile 64-bits to 8-bits 66 %addr_trunc64 = getelementptr i8, ptr %addr_8bit, i64 -1 67 %val64 = load volatile i64, ptr @var_64bit 68 %val8_trunc64 = trunc i64 %val64 to i8 69 store volatile i8 %val8_trunc64, ptr %addr_trunc64 70; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] 71 72 ret void 73} 74 75define dso_local void @ldst_16bit() { 76; CHECK-LABEL: ldst_16bit: 77 78; No architectural support for loads to 16-bit or 16-bit since we 79; promote i16 during lowering. 80 %addr_8bit = load ptr, ptr @varptr 81 82; match a sign-extending load 16-bit -> 32-bit 83 %addr8_sext32 = getelementptr i8, ptr %addr_8bit, i64 -256 84 %val16_sext32 = load volatile i16, ptr %addr8_sext32 85 %val32_signed = sext i16 %val16_sext32 to i32 86 store volatile i32 %val32_signed, ptr @var_32bit 87; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 88 89; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned. 90 %addr8_zext32 = getelementptr i8, ptr %addr_8bit, i64 15 91 %val16_zext32 = load volatile i16, ptr %addr8_zext32 92 %val32_unsigned = zext i16 %val16_zext32 to i32 93 store volatile i32 %val32_unsigned, ptr @var_32bit 94; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15] 95 96; match an any-extending load volatile 16-bit -> 32-bit 97 %addr8_anyext = getelementptr i8, ptr %addr_8bit, i64 -1 98 %val16_anyext = load volatile i16, ptr %addr8_anyext 99 %newval16 = add i16 %val16_anyext, 1 100 store volatile i16 %newval16, ptr @var_16bit 101; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] 102 103; match a sign-extending load volatile 16-bit -> 64-bit 104 %addr8_sext64 = getelementptr i8, ptr %addr_8bit, i64 -5 105 %val16_sext64 = load volatile i16, ptr %addr8_sext64 106 %val64_signed = sext i16 %val16_sext64 to i64 107 store volatile i64 %val64_signed, ptr @var_64bit 108; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5] 109 110; match a zero-extending load volatile 16-bit -> 64-bit. 111; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits 112; of x0 so it's identical to load volatileing to 32-bits. 113 %addr8_zext64 = getelementptr i8, ptr %addr_8bit, i64 9 114 %val16_zext64 = load volatile i16, ptr %addr8_zext64 115 %val64_unsigned = zext i16 %val16_zext64 to i64 116 store volatile i64 %val64_unsigned, ptr @var_64bit 117; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9] 118 119; truncating store volatile 32-bits to 16-bits 120 %addr8_trunc32 = getelementptr i8, ptr %addr_8bit, i64 -256 121 %val32 = load volatile i32, ptr @var_32bit 122 %val16_trunc32 = trunc i32 %val32 to i16 123 store volatile i16 %val16_trunc32, ptr %addr8_trunc32 124; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 125 126; truncating store volatile 64-bits to 16-bits 127 %addr8_trunc64 = getelementptr i8, ptr %addr_8bit, i64 -1 128 %val64 = load volatile i64, ptr @var_64bit 129 %val16_trunc64 = trunc i64 %val64 to i16 130 store volatile i16 %val16_trunc64, ptr %addr8_trunc64 131; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] 132 133 ret void 134} 135 136define dso_local void @ldst_32bit() { 137; CHECK-LABEL: ldst_32bit: 138 139 %addr_8bit = load ptr, ptr @varptr 140 141; Straight 32-bit load/store 142 %addr32_8_noext = getelementptr i8, ptr %addr_8bit, i64 1 143 %val32_noext = load volatile i32, ptr %addr32_8_noext 144 store volatile i32 %val32_noext, ptr %addr32_8_noext 145; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1] 146; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1] 147 148; Zero-extension to 64-bits 149 %addr32_8_zext = getelementptr i8, ptr %addr_8bit, i64 -256 150 %val32_zext = load volatile i32, ptr %addr32_8_zext 151 %val64_unsigned = zext i32 %val32_zext to i64 152 store volatile i64 %val64_unsigned, ptr @var_64bit 153; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256] 154; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] 155 156; Sign-extension to 64-bits 157 %addr32_8_sext = getelementptr i8, ptr %addr_8bit, i64 -12 158 %val32_sext = load volatile i32, ptr %addr32_8_sext 159 %val64_signed = sext i32 %val32_sext to i64 160 store volatile i64 %val64_signed, ptr @var_64bit 161; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12] 162; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] 163 164; Truncation from 64-bits 165 %addr64_8_trunc = getelementptr i8, ptr %addr_8bit, i64 255 166 %addr32_8_trunc = getelementptr i8, ptr %addr_8bit, i64 -20 167 168 %val64_trunc = load volatile i64, ptr %addr64_8_trunc 169 %val32_trunc = trunc i64 %val64_trunc to i32 170 store volatile i32 %val32_trunc, ptr %addr32_8_trunc 171; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255] 172; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20] 173 174 ret void 175} 176 177define dso_local void @ldst_float() { 178; CHECK-LABEL: ldst_float: 179 180 %addr_8bit = load ptr, ptr @varptr 181 %addrfp_8 = getelementptr i8, ptr %addr_8bit, i64 -5 182 183 %valfp = load volatile float, ptr %addrfp_8 184; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5] 185; CHECK-NOFP-NOT: ldur {{s[0-9]+}}, 186 187 store volatile float %valfp, ptr %addrfp_8 188; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5] 189; CHECK-NOFP-NOT: stur {{s[0-9]+}}, 190 191 ret void 192} 193 194define dso_local void @ldst_double() { 195; CHECK-LABEL: ldst_double: 196 197 %addr_8bit = load ptr, ptr @varptr 198 %addrfp_8 = getelementptr i8, ptr %addr_8bit, i64 4 199 200 %valfp = load volatile double, ptr %addrfp_8 201; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4] 202; CHECK-NOFP-NOT: ldur {{d[0-9]+}}, 203 204 store volatile double %valfp, ptr %addrfp_8 205; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4] 206; CHECK-NOFP-NOT: stur {{d[0-9]+}}, 207 208 ret void 209} 210