1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s 3define i32 @test_cchi(i64 %a) { 4; CHECK-LABEL: test_cchi: 5; CHECK: // %bb.0: // %entry 6; CHECK-NEXT: //APP 7; CHECK-NEXT: subs x0, x0, #3 8; CHECK-NEXT: //NO_APP 9; CHECK-NEXT: cset w0, hi 10; CHECK-NEXT: ret 11entry: 12 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cchi},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 13 %asmresult1 = extractvalue { i64, i32 } %0, 1 14 %1 = icmp ult i32 %asmresult1, 2 15 tail call void @llvm.assume(i1 %1) 16 ret i32 %asmresult1 17} 18 19define i32 @test_cccs(i64 %a) { 20; CHECK-LABEL: test_cccs: 21; CHECK: // %bb.0: // %entry 22; CHECK-NEXT: //APP 23; CHECK-NEXT: subs x0, x0, #3 24; CHECK-NEXT: //NO_APP 25; CHECK-NEXT: cset w0, hs 26; CHECK-NEXT: ret 27entry: 28 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cccs},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 29 %asmresult1 = extractvalue { i64, i32 } %0, 1 30 %1 = icmp ult i32 %asmresult1, 2 31 tail call void @llvm.assume(i1 %1) 32 ret i32 %asmresult1 33} 34 35define i32 @test_cclo(i64 %a) { 36; CHECK-LABEL: test_cclo: 37; CHECK: // %bb.0: // %entry 38; CHECK-NEXT: //APP 39; CHECK-NEXT: subs x0, x0, #3 40; CHECK-NEXT: //NO_APP 41; CHECK-NEXT: cset w0, lo 42; CHECK-NEXT: ret 43entry: 44 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cclo},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 45 %asmresult1 = extractvalue { i64, i32 } %0, 1 46 %1 = icmp ult i32 %asmresult1, 2 47 tail call void @llvm.assume(i1 %1) 48 ret i32 %asmresult1 49} 50 51define i32 @test_ccls(i64 %a) { 52; CHECK-LABEL: test_ccls: 53; CHECK: // %bb.0: // %entry 54; CHECK-NEXT: //APP 55; CHECK-NEXT: subs x0, x0, #3 56; CHECK-NEXT: //NO_APP 57; CHECK-NEXT: cset w0, ls 58; CHECK-NEXT: ret 59entry: 60 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccls},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 61 %asmresult1 = extractvalue { i64, i32 } %0, 1 62 %1 = icmp ult i32 %asmresult1, 2 63 tail call void @llvm.assume(i1 %1) 64 ret i32 %asmresult1 65} 66 67define i32 @test_cccc(i64 %a) { 68; CHECK-LABEL: test_cccc: 69; CHECK: // %bb.0: // %entry 70; CHECK-NEXT: //APP 71; CHECK-NEXT: subs x0, x0, #3 72; CHECK-NEXT: //NO_APP 73; CHECK-NEXT: cset w0, lo 74; CHECK-NEXT: ret 75entry: 76 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cccc},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 77 %asmresult1 = extractvalue { i64, i32 } %0, 1 78 %1 = icmp ult i32 %asmresult1, 2 79 tail call void @llvm.assume(i1 %1) 80 ret i32 %asmresult1 81} 82 83define i32 @test_cceq(i64 %a) { 84; CHECK-LABEL: test_cceq: 85; CHECK: // %bb.0: // %entry 86; CHECK-NEXT: //APP 87; CHECK-NEXT: subs x0, x0, #3 88; CHECK-NEXT: //NO_APP 89; CHECK-NEXT: cset w0, eq 90; CHECK-NEXT: ret 91entry: 92 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cceq},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 93 %asmresult1 = extractvalue { i64, i32 } %0, 1 94 %1 = icmp ult i32 %asmresult1, 2 95 tail call void @llvm.assume(i1 %1) 96 ret i32 %asmresult1 97} 98 99define i32 @test_ccgt(i64 %a) { 100; CHECK-LABEL: test_ccgt: 101; CHECK: // %bb.0: // %entry 102; CHECK-NEXT: //APP 103; CHECK-NEXT: subs x0, x0, #3 104; CHECK-NEXT: //NO_APP 105; CHECK-NEXT: cset w0, gt 106; CHECK-NEXT: ret 107entry: 108 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccgt},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 109 %asmresult1 = extractvalue { i64, i32 } %0, 1 110 %1 = icmp ult i32 %asmresult1, 2 111 tail call void @llvm.assume(i1 %1) 112 ret i32 %asmresult1 113} 114 115define i32 @test_ccge(i64 %a) { 116; CHECK-LABEL: test_ccge: 117; CHECK: // %bb.0: // %entry 118; CHECK-NEXT: //APP 119; CHECK-NEXT: subs x0, x0, #3 120; CHECK-NEXT: //NO_APP 121; CHECK-NEXT: cset w0, ge 122; CHECK-NEXT: ret 123entry: 124 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccge},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 125 %asmresult1 = extractvalue { i64, i32 } %0, 1 126 %1 = icmp ult i32 %asmresult1, 2 127 tail call void @llvm.assume(i1 %1) 128 ret i32 %asmresult1 129} 130 131define i32 @test_cclt(i64 %a) { 132; CHECK-LABEL: test_cclt: 133; CHECK: // %bb.0: // %entry 134; CHECK-NEXT: //APP 135; CHECK-NEXT: subs x0, x0, #3 136; CHECK-NEXT: //NO_APP 137; CHECK-NEXT: cset w0, lt 138; CHECK-NEXT: ret 139entry: 140 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cclt},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 141 %asmresult1 = extractvalue { i64, i32 } %0, 1 142 %1 = icmp ult i32 %asmresult1, 2 143 tail call void @llvm.assume(i1 %1) 144 ret i32 %asmresult1 145} 146 147define i32 @test_ccle(i64 %a) { 148; CHECK-LABEL: test_ccle: 149; CHECK: // %bb.0: // %entry 150; CHECK-NEXT: //APP 151; CHECK-NEXT: subs x0, x0, #3 152; CHECK-NEXT: //NO_APP 153; CHECK-NEXT: cset w0, le 154; CHECK-NEXT: ret 155entry: 156 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccle},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 157 %asmresult1 = extractvalue { i64, i32 } %0, 1 158 %1 = icmp ult i32 %asmresult1, 2 159 tail call void @llvm.assume(i1 %1) 160 ret i32 %asmresult1 161} 162 163define i32 @test_cchs(i64 %a) { 164; CHECK-LABEL: test_cchs: 165; CHECK: // %bb.0: // %entry 166; CHECK-NEXT: //APP 167; CHECK-NEXT: subs x0, x0, #3 168; CHECK-NEXT: //NO_APP 169; CHECK-NEXT: cset w0, hs 170; CHECK-NEXT: ret 171entry: 172 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@cchs},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 173 %asmresult1 = extractvalue { i64, i32 } %0, 1 174 %1 = icmp ult i32 %asmresult1, 2 175 tail call void @llvm.assume(i1 %1) 176 ret i32 %asmresult1 177} 178 179define i32 @test_ccne(i64 %a) { 180; CHECK-LABEL: test_ccne: 181; CHECK: // %bb.0: // %entry 182; CHECK-NEXT: //APP 183; CHECK-NEXT: subs x0, x0, #3 184; CHECK-NEXT: //NO_APP 185; CHECK-NEXT: cset w0, ne 186; CHECK-NEXT: ret 187entry: 188 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccne},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 189 %asmresult1 = extractvalue { i64, i32 } %0, 1 190 %1 = icmp ult i32 %asmresult1, 2 191 tail call void @llvm.assume(i1 %1) 192 ret i32 %asmresult1 193} 194 195define i32 @test_ccvc(i64 %a) { 196; CHECK-LABEL: test_ccvc: 197; CHECK: // %bb.0: // %entry 198; CHECK-NEXT: //APP 199; CHECK-NEXT: subs x0, x0, #3 200; CHECK-NEXT: //NO_APP 201; CHECK-NEXT: cset w0, vc 202; CHECK-NEXT: ret 203entry: 204 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccvc},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 205 %asmresult1 = extractvalue { i64, i32 } %0, 1 206 %1 = icmp ult i32 %asmresult1, 2 207 tail call void @llvm.assume(i1 %1) 208 ret i32 %asmresult1 209} 210 211define i32 @test_ccpl(i64 %a) { 212; CHECK-LABEL: test_ccpl: 213; CHECK: // %bb.0: // %entry 214; CHECK-NEXT: //APP 215; CHECK-NEXT: subs x0, x0, #3 216; CHECK-NEXT: //NO_APP 217; CHECK-NEXT: cset w0, pl 218; CHECK-NEXT: ret 219entry: 220 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccpl},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 221 %asmresult1 = extractvalue { i64, i32 } %0, 1 222 %1 = icmp ult i32 %asmresult1, 2 223 tail call void @llvm.assume(i1 %1) 224 ret i32 %asmresult1 225} 226 227define i32 @test_ccvs(i64 %a) { 228; CHECK-LABEL: test_ccvs: 229; CHECK: // %bb.0: // %entry 230; CHECK-NEXT: //APP 231; CHECK-NEXT: subs x0, x0, #3 232; CHECK-NEXT: //NO_APP 233; CHECK-NEXT: cset w0, vs 234; CHECK-NEXT: ret 235entry: 236 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccvs},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 237 %asmresult1 = extractvalue { i64, i32 } %0, 1 238 %1 = icmp ult i32 %asmresult1, 2 239 tail call void @llvm.assume(i1 %1) 240 ret i32 %asmresult1 241} 242 243define i32 @test_ccmi(i64 %a) { 244; CHECK-LABEL: test_ccmi: 245; CHECK: // %bb.0: // %entry 246; CHECK-NEXT: //APP 247; CHECK-NEXT: subs x0, x0, #3 248; CHECK-NEXT: //NO_APP 249; CHECK-NEXT: cset w0, mi 250; CHECK-NEXT: ret 251entry: 252 %0 = tail call { i64, i32 } asm "subs $0, $0, #3", "=r,={@ccmi},0,~{dirflag},~{fpsr},~{flags}"(i64 %a) 253 %asmresult1 = extractvalue { i64, i32 } %0, 1 254 %1 = icmp ult i32 %asmresult1, 2 255 tail call void @llvm.assume(i1 %1) 256 ret i32 %asmresult1 257} 258 259declare void @llvm.assume(i1) 260