1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s 3 4; Optimize expanded SRL/SHL used as an input of 5; SETCC comparing it with zero by removing rotation. 6; 7; See https://bugs.llvm.org/show_bug.cgi?id=50197 8define i128 @opt_setcc_lt_power_of_2(i128 %a) nounwind { 9; CHECK-LABEL: opt_setcc_lt_power_of_2: 10; CHECK: // %bb.0: 11; CHECK-NEXT: .LBB0_1: // %loop 12; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 13; CHECK-NEXT: adds x0, x0, #1 14; CHECK-NEXT: cinc x1, x1, hs 15; CHECK-NEXT: orr x8, x1, x0, lsr #60 16; CHECK-NEXT: cbnz x8, .LBB0_1 17; CHECK-NEXT: // %bb.2: // %exit 18; CHECK-NEXT: ret 19 br label %loop 20 21loop: 22 %phi.a = phi i128 [ %a, %0 ], [ %inc, %loop ] 23 %inc = add i128 %phi.a, 1 24 %cmp = icmp ult i128 %inc, 1152921504606846976 25 br i1 %cmp, label %exit, label %loop 26 27exit: 28 ret i128 %inc 29} 30 31define i1 @opt_setcc_srl_eq_zero(i128 %a) nounwind { 32; CHECK-LABEL: opt_setcc_srl_eq_zero: 33; CHECK: // %bb.0: 34; CHECK-NEXT: orr x8, x1, x0, lsr #17 35; CHECK-NEXT: cmp x8, #0 36; CHECK-NEXT: cset w0, eq 37; CHECK-NEXT: ret 38 %srl = lshr i128 %a, 17 39 %cmp = icmp eq i128 %srl, 0 40 ret i1 %cmp 41} 42 43define i1 @opt_setcc_srl_ne_zero(i128 %a) nounwind { 44; CHECK-LABEL: opt_setcc_srl_ne_zero: 45; CHECK: // %bb.0: 46; CHECK-NEXT: orr x8, x1, x0, lsr #17 47; CHECK-NEXT: cmp x8, #0 48; CHECK-NEXT: cset w0, ne 49; CHECK-NEXT: ret 50 %srl = lshr i128 %a, 17 51 %cmp = icmp ne i128 %srl, 0 52 ret i1 %cmp 53} 54 55define i1 @opt_setcc_shl_eq_zero(i128 %a) nounwind { 56; CHECK-LABEL: opt_setcc_shl_eq_zero: 57; CHECK: // %bb.0: 58; CHECK-NEXT: orr x8, x0, x1, lsl #17 59; CHECK-NEXT: cmp x8, #0 60; CHECK-NEXT: cset w0, eq 61; CHECK-NEXT: ret 62 %shl = shl i128 %a, 17 63 %cmp = icmp eq i128 %shl, 0 64 ret i1 %cmp 65} 66 67define i1 @opt_setcc_shl_ne_zero(i128 %a) nounwind { 68; CHECK-LABEL: opt_setcc_shl_ne_zero: 69; CHECK: // %bb.0: 70; CHECK-NEXT: orr x8, x0, x1, lsl #17 71; CHECK-NEXT: cmp x8, #0 72; CHECK-NEXT: cset w0, ne 73; CHECK-NEXT: ret 74 %shl = shl i128 %a, 17 75 %cmp = icmp ne i128 %shl, 0 76 ret i1 %cmp 77} 78 79; Negative test: optimization should not be applied if shift has multiple users. 80define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i128 %a) nounwind { 81; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users: 82; CHECK: // %bb.0: 83; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill 84; CHECK-NEXT: extr x1, x1, x0, #47 85; CHECK-NEXT: lsl x0, x0, #17 86; CHECK-NEXT: orr x8, x0, x1 87; CHECK-NEXT: cmp x8, #0 88; CHECK-NEXT: cset w19, eq 89; CHECK-NEXT: bl use 90; CHECK-NEXT: mov w0, w19 91; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload 92; CHECK-NEXT: ret 93 %shl = shl i128 %a, 17 94 %cmp = icmp eq i128 %shl, 0 95 call void @use(i128 %shl) 96 ret i1 %cmp 97} 98 99; Check that optimization is applied to DAG having appropriate shape 100; even if there were no actual shift's expansion. 101define i1 @opt_setcc_expanded_shl_correct_shifts(i64 %a, i64 %b) nounwind { 102; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts: 103; CHECK: // %bb.0: 104; CHECK-NEXT: orr x8, x1, x0, lsl #17 105; CHECK-NEXT: cmp x8, #0 106; CHECK-NEXT: cset w0, eq 107; CHECK-NEXT: ret 108 %shl.a = shl i64 %a, 17 109 %srl.b = lshr i64 %b, 47 110 %or.0 = or i64 %shl.a, %srl.b 111 %shl.b = shl i64 %b, 17 112 %or.1 = or i64 %or.0, %shl.b 113 %cmp = icmp eq i64 %or.1, 0 114 ret i1 %cmp 115} 116 117; Negative test: optimization should not be applied as 118; constants used in shifts do not match. 119define i1 @opt_setcc_expanded_shl_wrong_shifts(i64 %a, i64 %b) nounwind { 120; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts: 121; CHECK: // %bb.0: 122; CHECK-NEXT: extr x8, x0, x1, #47 123; CHECK-NEXT: orr x8, x8, x1, lsl #18 124; CHECK-NEXT: cmp x8, #0 125; CHECK-NEXT: cset w0, eq 126; CHECK-NEXT: ret 127 %shl.a = shl i64 %a, 17 128 %srl.b = lshr i64 %b, 47 129 %or.0 = or i64 %shl.a, %srl.b 130 %shl.b = shl i64 %b, 18 131 %or.1 = or i64 %or.0, %shl.b 132 %cmp = icmp eq i64 %or.1, 0 133 ret i1 %cmp 134} 135 136define i1 @opt_setcc_shl_ne_zero_i256(i256 %a) nounwind { 137; CHECK-LABEL: opt_setcc_shl_ne_zero_i256: 138; CHECK: // %bb.0: 139; CHECK-NEXT: orr x8, x2, x0 140; CHECK-NEXT: orr x8, x1, x8 141; CHECK-NEXT: orr x8, x8, x3, lsl #17 142; CHECK-NEXT: cmp x8, #0 143; CHECK-NEXT: cset w0, ne 144; CHECK-NEXT: ret 145 %shl = shl i256 %a, 17 146 %cmp = icmp ne i256 %shl, 0 147 ret i1 %cmp 148} 149 150declare void @use(i128 %a) 151