1; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-post-ra | FileCheck %s 2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -disable-post-ra | FileCheck --check-prefix=CHECK-NOFP %s 3 4%myStruct = type { i64 , i8, i32 } 5 6@var8 = dso_local global i8 0 7@var32 = dso_local global i32 0 8@var64 = dso_local global i64 0 9@var128 = dso_local global i128 0 10@varfloat = dso_local global float 0.0 11@vardouble = dso_local global double 0.0 12@varstruct = dso_local global %myStruct zeroinitializer 13 14define dso_local void @take_i8s(i8 %val1, i8 %val2) { 15; CHECK-LABEL: take_i8s: 16 store i8 %val2, ptr @var8 17 ; Not using w1 may be technically allowed, but it would indicate a 18 ; problem in itself. 19; CHECK: strb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8] 20 ret void 21} 22 23define dso_local void @add_floats(float %val1, float %val2) { 24; CHECK-LABEL: add_floats: 25 %newval = fadd float %val1, %val2 26; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1 27; CHECK-NOFP-NOT: fadd 28 store float %newval, ptr @varfloat 29; CHECK: str [[ADDRES]], [{{x[0-9]+}}, {{#?}}:lo12:varfloat] 30 ret void 31} 32 33; byval pointers should be allocated to the stack and copied as if 34; with memcpy. 35define dso_local void @take_struct(ptr byval(%myStruct) %structval) { 36; CHECK-LABEL: take_struct: 37 %addr0 = getelementptr %myStruct, ptr %structval, i64 0, i32 2 38 39 %val0 = load volatile i32, ptr %addr0 40 ; Some weird move means x0 is used for one access 41; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] 42 store volatile i32 %val0, ptr @var32 43; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32] 44 45 %val1 = load volatile i64, ptr %structval 46; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] 47 store volatile i64 %val1, ptr @var64 48; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64] 49 50 ret void 51} 52 53; %structval should be at sp + 16 54define dso_local void @check_byval_align(ptr byval(i32) %ignore, ptr byval(%myStruct) align 16 %structval) { 55; CHECK-LABEL: check_byval_align: 56 57 %addr0 = getelementptr %myStruct, ptr %structval, i64 0, i32 2 58 59 %val0 = load volatile i32, ptr %addr0 60 ; Some weird move means x0 is used for one access 61; CHECK: ldr [[REG32:w[0-9]+]], [sp, #28] 62 store i32 %val0, ptr @var32 63; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32] 64 65 %val1 = load volatile i64, ptr %structval 66; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] 67 store i64 %val1, ptr @var64 68; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64] 69 70 ret void 71} 72 73define dso_local i32 @return_int() { 74; CHECK-LABEL: return_int: 75 %val = load i32, ptr @var32 76 ret i32 %val 77; CHECK: ldr w0, [{{x[0-9]+}}, {{#?}}:lo12:var32] 78 ; Make sure epilogue follows 79; CHECK-NEXT: ret 80} 81 82define dso_local double @return_double() { 83; CHECK-LABEL: return_double: 84 ret double 3.14 85; CHECK: ldr d0, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI 86; CHECK-NOFP-NOT: ldr d0, 87} 88 89; This is the kind of IR clang will produce for returning a struct 90; small enough to go into registers. Not all that pretty, but it 91; works. 92define [2 x i64] @return_struct() { 93; CHECK-LABEL: return_struct: 94 %val = load [2 x i64], ptr @varstruct 95 ret [2 x i64] %val 96; CHECK: add x[[VARSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varstruct 97; CHECK: ldp x0, x1, [x[[VARSTRUCT]]] 98 ; Make sure epilogue immediately follows 99; CHECK-NEXT: ret 100} 101 102; Large structs are passed by reference (storage allocated by caller 103; to preserve value semantics) in x8. Strictly this only applies to 104; structs larger than 16 bytes, but C semantics can still be provided 105; if LLVM does it to %myStruct too. So this is the simplest check 106define dso_local void @return_large_struct(ptr sret(%myStruct) %retval) { 107; CHECK-LABEL: return_large_struct: 108 %addr1 = getelementptr %myStruct, ptr %retval, i64 0, i32 1 109 %addr2 = getelementptr %myStruct, ptr %retval, i64 0, i32 2 110 111 store i64 42, ptr %retval 112 store i8 2, ptr %addr1 113 store i32 9, ptr %addr2 114; CHECK: str {{x[0-9]+}}, [x8] 115; CHECK: strb {{w[0-9]+}}, [x8, #8] 116; CHECK: str {{w[0-9]+}}, [x8, #12] 117 118 ret void 119} 120 121; This struct is just too far along to go into registers: (only x7 is 122; available, but it needs two). Also make sure that %stacked doesn't 123; sneak into x7 behind. 124define dso_local i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, 125 ptr %var6, ptr byval(%myStruct) %struct, ptr byval(i32) %stacked, 126 double %notstacked) { 127; CHECK-LABEL: struct_on_stack: 128 %val64 = load volatile i64, ptr %struct 129 store volatile i64 %val64, ptr @var64 130 ; Currently nothing on local stack, so struct should be at sp 131; CHECK: ldr [[VAL64:x[0-9]+]], [sp] 132; CHECK: str [[VAL64]], [{{x[0-9]+}}, {{#?}}:lo12:var64] 133 134 store volatile double %notstacked, ptr @vardouble 135; CHECK-NOT: ldr d0 136; CHECK: str d0, [{{x[0-9]+}}, {{#?}}:lo12:vardouble 137; CHECK-NOFP-NOT: str d0, 138 139 %retval = load volatile i32, ptr %stacked 140 ret i32 %retval 141; CHECK-LE: ldr w0, [sp, #16] 142} 143 144define dso_local void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, 145 float %var4, float %var5, float %var6, float %var7, 146 float %var8) { 147; CHECK-LABEL: stacked_fpu: 148 store float %var8, ptr @varfloat 149 ; Beware as above: the offset would be different on big-endian 150 ; machines if the first ldr were changed to use s-registers. 151; CHECK: ldr {{[ds]}}[[VALFLOAT:[0-9]+]], [sp] 152; CHECK: str s[[VALFLOAT]], [{{x[0-9]+}}, {{#?}}:lo12:varfloat] 153 154 ret void 155} 156 157; 128-bit integer types should be passed in xEVEN, xODD rather than 158; the reverse. In this case x2 and x3. Nothing should use x1. 159define dso_local i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) { 160; CHECK-LABEL: check_i128_regalign 161 store i128 %val1, ptr @var128 162; CHECK-DAG: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 163; CHECK-DAG: stp x2, x3, [x[[VAR128]]] 164 165 ret i64 %val2 166; CHECK-DAG: mov x0, x4 167} 168 169define dso_local void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, 170 i32 %val4, i32 %val5, i32 %val6, i32 %val7, 171 i32 %stack1, i128 %stack2) { 172; CHECK-LABEL: check_i128_stackalign 173 store i128 %stack2, ptr @var128 174 ; Nothing local on stack in current codegen, so first stack is 16 away 175; CHECK-LE: add x[[REG:[0-9]+]], sp, #16 176; CHECK-LE: ldr {{x[0-9]+}}, [x[[REG]], #8] 177 178 ; Important point is that we address sp+24 for second dword 179 180; CHECK: ldp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] 181 ret void 182} 183 184declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) 185 186define dso_local i32 @test_extern() { 187; CHECK-LABEL: test_extern: 188 call void @llvm.memcpy.p0.p0.i32(ptr align 4 undef, ptr align 4 undef, i32 undef, i1 0) 189; CHECK: bl memcpy 190 ret i32 0 191} 192 193 194; A sub-i32 stack argument must be loaded on big endian with ldr{h,b}, not just 195; implicitly extended to a 32-bit load. 196define dso_local i16 @stacked_i16(i32 %val0, i32 %val1, i32 %val2, i32 %val3, 197 i32 %val4, i32 %val5, i32 %val6, i32 %val7, 198 i16 %stack1) { 199; CHECK-LABEL: stacked_i16 200 ret i16 %stack1 201} 202