xref: /llvm-project/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (revision 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
3; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
4; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
5; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
6
7; CHECK-GI:       warning: Instruction selection used fallback path for test_unsigned_v4f32_v4i50
8; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_unsigned_v4f16_v4i50
9; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_unsigned_v8f16_v8i19
10; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for test_unsigned_v8f16_v8i50
11
12;
13; Float to unsigned 32-bit -- Vector size variation
14;
15
16declare <1 x i32> @llvm.fptoui.sat.v1f32.v1i32 (<1 x float>)
17declare <2 x i32> @llvm.fptoui.sat.v2f32.v2i32 (<2 x float>)
18declare <3 x i32> @llvm.fptoui.sat.v3f32.v3i32 (<3 x float>)
19declare <4 x i32> @llvm.fptoui.sat.v4f32.v4i32 (<4 x float>)
20declare <5 x i32> @llvm.fptoui.sat.v5f32.v5i32 (<5 x float>)
21declare <6 x i32> @llvm.fptoui.sat.v6f32.v6i32 (<6 x float>)
22declare <7 x i32> @llvm.fptoui.sat.v7f32.v7i32 (<7 x float>)
23declare <8 x i32> @llvm.fptoui.sat.v8f32.v8i32 (<8 x float>)
24
25define <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) {
26; CHECK-SD-LABEL: test_unsigned_v1f32_v1i32:
27; CHECK-SD:       // %bb.0:
28; CHECK-SD-NEXT:    fcvtzu v0.2s, v0.2s
29; CHECK-SD-NEXT:    ret
30;
31; CHECK-GI-LABEL: test_unsigned_v1f32_v1i32:
32; CHECK-GI:       // %bb.0:
33; CHECK-GI-NEXT:    fcvtzu w8, s0
34; CHECK-GI-NEXT:    mov v0.s[0], w8
35; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
36; CHECK-GI-NEXT:    ret
37    %x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f)
38    ret <1 x i32> %x
39}
40
41define <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
42; CHECK-LABEL: test_unsigned_v2f32_v2i32:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
45; CHECK-NEXT:    ret
46    %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
47    ret <2 x i32> %x
48}
49
50define <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
51; CHECK-LABEL: test_unsigned_v3f32_v3i32:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
54; CHECK-NEXT:    ret
55    %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
56    ret <3 x i32> %x
57}
58
59define <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
60; CHECK-LABEL: test_unsigned_v4f32_v4i32:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
63; CHECK-NEXT:    ret
64    %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
65    ret <4 x i32> %x
66}
67
68define <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
69; CHECK-SD-LABEL: test_unsigned_v5f32_v5i32:
70; CHECK-SD:       // %bb.0:
71; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 def $q0
72; CHECK-SD-NEXT:    // kill: def $s1 killed $s1 def $q1
73; CHECK-SD-NEXT:    // kill: def $s2 killed $s2 def $q2
74; CHECK-SD-NEXT:    // kill: def $s3 killed $s3 def $q3
75; CHECK-SD-NEXT:    // kill: def $s4 killed $s4 def $q4
76; CHECK-SD-NEXT:    mov v0.s[1], v1.s[0]
77; CHECK-SD-NEXT:    fcvtzu v4.4s, v4.4s
78; CHECK-SD-NEXT:    mov v0.s[2], v2.s[0]
79; CHECK-SD-NEXT:    fmov w4, s4
80; CHECK-SD-NEXT:    mov v0.s[3], v3.s[0]
81; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
82; CHECK-SD-NEXT:    mov w1, v0.s[1]
83; CHECK-SD-NEXT:    mov w2, v0.s[2]
84; CHECK-SD-NEXT:    mov w3, v0.s[3]
85; CHECK-SD-NEXT:    fmov w0, s0
86; CHECK-SD-NEXT:    ret
87;
88; CHECK-GI-LABEL: test_unsigned_v5f32_v5i32:
89; CHECK-GI:       // %bb.0:
90; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 def $q0
91; CHECK-GI-NEXT:    // kill: def $s1 killed $s1 def $q1
92; CHECK-GI-NEXT:    // kill: def $s2 killed $s2 def $q2
93; CHECK-GI-NEXT:    // kill: def $s3 killed $s3 def $q3
94; CHECK-GI-NEXT:    // kill: def $s4 killed $s4 def $q4
95; CHECK-GI-NEXT:    mov v0.s[1], v1.s[0]
96; CHECK-GI-NEXT:    fcvtzu v1.4s, v4.4s
97; CHECK-GI-NEXT:    mov v0.s[2], v2.s[0]
98; CHECK-GI-NEXT:    fmov w4, s1
99; CHECK-GI-NEXT:    mov v0.s[3], v3.s[0]
100; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
101; CHECK-GI-NEXT:    mov s2, v0.s[1]
102; CHECK-GI-NEXT:    mov s3, v0.s[2]
103; CHECK-GI-NEXT:    mov s4, v0.s[3]
104; CHECK-GI-NEXT:    fmov w0, s0
105; CHECK-GI-NEXT:    fmov w1, s2
106; CHECK-GI-NEXT:    fmov w2, s3
107; CHECK-GI-NEXT:    fmov w3, s4
108; CHECK-GI-NEXT:    ret
109    %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
110    ret <5 x i32> %x
111}
112
113define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
114; CHECK-SD-LABEL: test_unsigned_v6f32_v6i32:
115; CHECK-SD:       // %bb.0:
116; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 def $q0
117; CHECK-SD-NEXT:    // kill: def $s1 killed $s1 def $q1
118; CHECK-SD-NEXT:    // kill: def $s2 killed $s2 def $q2
119; CHECK-SD-NEXT:    // kill: def $s4 killed $s4 def $q4
120; CHECK-SD-NEXT:    // kill: def $s5 killed $s5 def $q5
121; CHECK-SD-NEXT:    // kill: def $s3 killed $s3 def $q3
122; CHECK-SD-NEXT:    mov v0.s[1], v1.s[0]
123; CHECK-SD-NEXT:    mov v4.s[1], v5.s[0]
124; CHECK-SD-NEXT:    mov v0.s[2], v2.s[0]
125; CHECK-SD-NEXT:    fcvtzu v1.4s, v4.4s
126; CHECK-SD-NEXT:    mov v0.s[3], v3.s[0]
127; CHECK-SD-NEXT:    mov w5, v1.s[1]
128; CHECK-SD-NEXT:    fmov w4, s1
129; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
130; CHECK-SD-NEXT:    mov w1, v0.s[1]
131; CHECK-SD-NEXT:    mov w2, v0.s[2]
132; CHECK-SD-NEXT:    mov w3, v0.s[3]
133; CHECK-SD-NEXT:    fmov w0, s0
134; CHECK-SD-NEXT:    ret
135;
136; CHECK-GI-LABEL: test_unsigned_v6f32_v6i32:
137; CHECK-GI:       // %bb.0:
138; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 def $q0
139; CHECK-GI-NEXT:    // kill: def $s1 killed $s1 def $q1
140; CHECK-GI-NEXT:    // kill: def $s2 killed $s2 def $q2
141; CHECK-GI-NEXT:    // kill: def $s4 killed $s4 def $q4
142; CHECK-GI-NEXT:    // kill: def $s3 killed $s3 def $q3
143; CHECK-GI-NEXT:    // kill: def $s5 killed $s5 def $q5
144; CHECK-GI-NEXT:    mov v0.s[1], v1.s[0]
145; CHECK-GI-NEXT:    mov v4.s[1], v5.s[0]
146; CHECK-GI-NEXT:    mov v0.s[2], v2.s[0]
147; CHECK-GI-NEXT:    fcvtzu v1.4s, v4.4s
148; CHECK-GI-NEXT:    mov v0.s[3], v3.s[0]
149; CHECK-GI-NEXT:    mov s4, v1.s[1]
150; CHECK-GI-NEXT:    fmov w4, s1
151; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
152; CHECK-GI-NEXT:    fmov w5, s4
153; CHECK-GI-NEXT:    mov s2, v0.s[1]
154; CHECK-GI-NEXT:    mov s3, v0.s[2]
155; CHECK-GI-NEXT:    mov s5, v0.s[3]
156; CHECK-GI-NEXT:    fmov w0, s0
157; CHECK-GI-NEXT:    fmov w1, s2
158; CHECK-GI-NEXT:    fmov w2, s3
159; CHECK-GI-NEXT:    fmov w3, s5
160; CHECK-GI-NEXT:    ret
161    %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
162    ret <6 x i32> %x
163}
164
165define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
166; CHECK-SD-LABEL: test_unsigned_v7f32_v7i32:
167; CHECK-SD:       // %bb.0:
168; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 def $q0
169; CHECK-SD-NEXT:    // kill: def $s1 killed $s1 def $q1
170; CHECK-SD-NEXT:    // kill: def $s4 killed $s4 def $q4
171; CHECK-SD-NEXT:    // kill: def $s5 killed $s5 def $q5
172; CHECK-SD-NEXT:    // kill: def $s2 killed $s2 def $q2
173; CHECK-SD-NEXT:    // kill: def $s6 killed $s6 def $q6
174; CHECK-SD-NEXT:    // kill: def $s3 killed $s3 def $q3
175; CHECK-SD-NEXT:    mov v0.s[1], v1.s[0]
176; CHECK-SD-NEXT:    mov v4.s[1], v5.s[0]
177; CHECK-SD-NEXT:    mov v0.s[2], v2.s[0]
178; CHECK-SD-NEXT:    mov v4.s[2], v6.s[0]
179; CHECK-SD-NEXT:    mov v0.s[3], v3.s[0]
180; CHECK-SD-NEXT:    fcvtzu v1.4s, v4.4s
181; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
182; CHECK-SD-NEXT:    mov w5, v1.s[1]
183; CHECK-SD-NEXT:    mov w6, v1.s[2]
184; CHECK-SD-NEXT:    fmov w4, s1
185; CHECK-SD-NEXT:    mov w1, v0.s[1]
186; CHECK-SD-NEXT:    mov w2, v0.s[2]
187; CHECK-SD-NEXT:    mov w3, v0.s[3]
188; CHECK-SD-NEXT:    fmov w0, s0
189; CHECK-SD-NEXT:    ret
190;
191; CHECK-GI-LABEL: test_unsigned_v7f32_v7i32:
192; CHECK-GI:       // %bb.0:
193; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 def $q0
194; CHECK-GI-NEXT:    // kill: def $s1 killed $s1 def $q1
195; CHECK-GI-NEXT:    // kill: def $s4 killed $s4 def $q4
196; CHECK-GI-NEXT:    // kill: def $s2 killed $s2 def $q2
197; CHECK-GI-NEXT:    // kill: def $s5 killed $s5 def $q5
198; CHECK-GI-NEXT:    // kill: def $s3 killed $s3 def $q3
199; CHECK-GI-NEXT:    // kill: def $s6 killed $s6 def $q6
200; CHECK-GI-NEXT:    mov v0.s[1], v1.s[0]
201; CHECK-GI-NEXT:    mov v4.s[1], v5.s[0]
202; CHECK-GI-NEXT:    mov v0.s[2], v2.s[0]
203; CHECK-GI-NEXT:    mov v4.s[2], v6.s[0]
204; CHECK-GI-NEXT:    mov v0.s[3], v3.s[0]
205; CHECK-GI-NEXT:    fcvtzu v1.4s, v4.4s
206; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
207; CHECK-GI-NEXT:    mov s5, v1.s[1]
208; CHECK-GI-NEXT:    mov s6, v1.s[2]
209; CHECK-GI-NEXT:    fmov w4, s1
210; CHECK-GI-NEXT:    mov s2, v0.s[1]
211; CHECK-GI-NEXT:    mov s3, v0.s[2]
212; CHECK-GI-NEXT:    mov s4, v0.s[3]
213; CHECK-GI-NEXT:    fmov w0, s0
214; CHECK-GI-NEXT:    fmov w5, s5
215; CHECK-GI-NEXT:    fmov w6, s6
216; CHECK-GI-NEXT:    fmov w1, s2
217; CHECK-GI-NEXT:    fmov w2, s3
218; CHECK-GI-NEXT:    fmov w3, s4
219; CHECK-GI-NEXT:    ret
220    %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
221    ret <7 x i32> %x
222}
223
224define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
225; CHECK-LABEL: test_unsigned_v8f32_v8i32:
226; CHECK:       // %bb.0:
227; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
228; CHECK-NEXT:    fcvtzu v1.4s, v1.4s
229; CHECK-NEXT:    ret
230    %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
231    ret <8 x i32> %x
232}
233
234;
235; Double to unsigned 32-bit -- Vector size variation
236;
237
238declare <1 x i32> @llvm.fptoui.sat.v1f64.v1i32 (<1 x double>)
239declare <2 x i32> @llvm.fptoui.sat.v2f64.v2i32 (<2 x double>)
240declare <3 x i32> @llvm.fptoui.sat.v3f64.v3i32 (<3 x double>)
241declare <4 x i32> @llvm.fptoui.sat.v4f64.v4i32 (<4 x double>)
242declare <5 x i32> @llvm.fptoui.sat.v5f64.v5i32 (<5 x double>)
243declare <6 x i32> @llvm.fptoui.sat.v6f64.v6i32 (<6 x double>)
244
245define <1 x i32> @test_unsigned_v1f64_v1i32(<1 x double> %f) {
246; CHECK-SD-LABEL: test_unsigned_v1f64_v1i32:
247; CHECK-SD:       // %bb.0:
248; CHECK-SD-NEXT:    fcvtzu w8, d0
249; CHECK-SD-NEXT:    fmov s0, w8
250; CHECK-SD-NEXT:    ret
251;
252; CHECK-GI-LABEL: test_unsigned_v1f64_v1i32:
253; CHECK-GI:       // %bb.0:
254; CHECK-GI-NEXT:    fcvtzu w8, d0
255; CHECK-GI-NEXT:    mov v0.s[0], w8
256; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
257; CHECK-GI-NEXT:    ret
258    %x = call <1 x i32> @llvm.fptoui.sat.v1f64.v1i32(<1 x double> %f)
259    ret <1 x i32> %x
260}
261
262define <2 x i32> @test_unsigned_v2f64_v2i32(<2 x double> %f) {
263; CHECK-SD-LABEL: test_unsigned_v2f64_v2i32:
264; CHECK-SD:       // %bb.0:
265; CHECK-SD-NEXT:    mov d1, v0.d[1]
266; CHECK-SD-NEXT:    fcvtzu w8, d0
267; CHECK-SD-NEXT:    fcvtzu w9, d1
268; CHECK-SD-NEXT:    fmov s0, w8
269; CHECK-SD-NEXT:    mov v0.s[1], w9
270; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
271; CHECK-SD-NEXT:    ret
272;
273; CHECK-GI-LABEL: test_unsigned_v2f64_v2i32:
274; CHECK-GI:       // %bb.0:
275; CHECK-GI-NEXT:    movi v1.2d, #0x000000ffffffff
276; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
277; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
278; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
279; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
280; CHECK-GI-NEXT:    ret
281    %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
282    ret <2 x i32> %x
283}
284
285define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
286; CHECK-SD-LABEL: test_unsigned_v3f64_v3i32:
287; CHECK-SD:       // %bb.0:
288; CHECK-SD-NEXT:    fcvtzu w8, d0
289; CHECK-SD-NEXT:    fcvtzu w9, d1
290; CHECK-SD-NEXT:    fmov s0, w8
291; CHECK-SD-NEXT:    fcvtzu w8, d2
292; CHECK-SD-NEXT:    mov v0.s[1], w9
293; CHECK-SD-NEXT:    mov v0.s[2], w8
294; CHECK-SD-NEXT:    fcvtzu w8, d0
295; CHECK-SD-NEXT:    mov v0.s[3], w8
296; CHECK-SD-NEXT:    ret
297;
298; CHECK-GI-LABEL: test_unsigned_v3f64_v3i32:
299; CHECK-GI:       // %bb.0:
300; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
301; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
302; CHECK-GI-NEXT:    // kill: def $d2 killed $d2 def $q2
303; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
304; CHECK-GI-NEXT:    fcvtzu v1.2d, v2.2d
305; CHECK-GI-NEXT:    movi v2.2d, #0x000000ffffffff
306; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
307; CHECK-GI-NEXT:    cmhi v4.2d, v2.2d, v1.2d
308; CHECK-GI-NEXT:    bif v1.16b, v2.16b, v4.16b
309; CHECK-GI-NEXT:    cmhi v3.2d, v2.2d, v0.2d
310; CHECK-GI-NEXT:    bif v0.16b, v2.16b, v3.16b
311; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
312; CHECK-GI-NEXT:    ret
313    %x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f)
314    ret <3 x i32> %x
315}
316
317define <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) {
318; CHECK-SD-LABEL: test_unsigned_v4f64_v4i32:
319; CHECK-SD:       // %bb.0:
320; CHECK-SD-NEXT:    mov d2, v0.d[1]
321; CHECK-SD-NEXT:    fcvtzu w8, d0
322; CHECK-SD-NEXT:    fcvtzu w9, d2
323; CHECK-SD-NEXT:    fmov s0, w8
324; CHECK-SD-NEXT:    fcvtzu w8, d1
325; CHECK-SD-NEXT:    mov d1, v1.d[1]
326; CHECK-SD-NEXT:    mov v0.s[1], w9
327; CHECK-SD-NEXT:    mov v0.s[2], w8
328; CHECK-SD-NEXT:    fcvtzu w8, d1
329; CHECK-SD-NEXT:    mov v0.s[3], w8
330; CHECK-SD-NEXT:    ret
331;
332; CHECK-GI-LABEL: test_unsigned_v4f64_v4i32:
333; CHECK-GI:       // %bb.0:
334; CHECK-GI-NEXT:    movi v2.2d, #0x000000ffffffff
335; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
336; CHECK-GI-NEXT:    fcvtzu v1.2d, v1.2d
337; CHECK-GI-NEXT:    cmhi v3.2d, v2.2d, v0.2d
338; CHECK-GI-NEXT:    cmhi v4.2d, v2.2d, v1.2d
339; CHECK-GI-NEXT:    bif v0.16b, v2.16b, v3.16b
340; CHECK-GI-NEXT:    bif v1.16b, v2.16b, v4.16b
341; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
342; CHECK-GI-NEXT:    ret
343    %x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f)
344    ret <4 x i32> %x
345}
346
347define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
348; CHECK-SD-LABEL: test_unsigned_v5f64_v5i32:
349; CHECK-SD:       // %bb.0:
350; CHECK-SD-NEXT:    fcvtzu w0, d0
351; CHECK-SD-NEXT:    fcvtzu w1, d1
352; CHECK-SD-NEXT:    fcvtzu w2, d2
353; CHECK-SD-NEXT:    fcvtzu w3, d3
354; CHECK-SD-NEXT:    fcvtzu w4, d4
355; CHECK-SD-NEXT:    ret
356;
357; CHECK-GI-LABEL: test_unsigned_v5f64_v5i32:
358; CHECK-GI:       // %bb.0:
359; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
360; CHECK-GI-NEXT:    // kill: def $d2 killed $d2 def $q2
361; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
362; CHECK-GI-NEXT:    // kill: def $d3 killed $d3 def $q3
363; CHECK-GI-NEXT:    // kill: def $d4 killed $d4 def $q4
364; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
365; CHECK-GI-NEXT:    mov v2.d[1], v3.d[0]
366; CHECK-GI-NEXT:    movi v1.2d, #0x000000ffffffff
367; CHECK-GI-NEXT:    fcvtzu v3.2d, v4.2d
368; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
369; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
370; CHECK-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
371; CHECK-GI-NEXT:    cmhi v5.2d, v1.2d, v2.2d
372; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
373; CHECK-GI-NEXT:    bif v2.16b, v1.16b, v5.16b
374; CHECK-GI-NEXT:    cmhi v4.2d, v1.2d, v3.2d
375; CHECK-GI-NEXT:    bit v1.16b, v3.16b, v4.16b
376; CHECK-GI-NEXT:    mov d3, v0.d[1]
377; CHECK-GI-NEXT:    mov d4, v2.d[1]
378; CHECK-GI-NEXT:    fmov x0, d0
379; CHECK-GI-NEXT:    fmov x2, d2
380; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 killed $x0
381; CHECK-GI-NEXT:    // kill: def $w2 killed $w2 killed $x2
382; CHECK-GI-NEXT:    fmov x4, d1
383; CHECK-GI-NEXT:    fmov x1, d3
384; CHECK-GI-NEXT:    fmov x3, d4
385; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
386; CHECK-GI-NEXT:    // kill: def $w1 killed $w1 killed $x1
387; CHECK-GI-NEXT:    // kill: def $w3 killed $w3 killed $x3
388; CHECK-GI-NEXT:    ret
389    %x = call <5 x i32> @llvm.fptoui.sat.v5f64.v5i32(<5 x double> %f)
390    ret <5 x i32> %x
391}
392
393define <6 x i32> @test_unsigned_v6f64_v6i32(<6 x double> %f) {
394; CHECK-SD-LABEL: test_unsigned_v6f64_v6i32:
395; CHECK-SD:       // %bb.0:
396; CHECK-SD-NEXT:    fcvtzu w0, d0
397; CHECK-SD-NEXT:    fcvtzu w1, d1
398; CHECK-SD-NEXT:    fcvtzu w2, d2
399; CHECK-SD-NEXT:    fcvtzu w3, d3
400; CHECK-SD-NEXT:    fcvtzu w4, d4
401; CHECK-SD-NEXT:    fcvtzu w5, d5
402; CHECK-SD-NEXT:    ret
403;
404; CHECK-GI-LABEL: test_unsigned_v6f64_v6i32:
405; CHECK-GI:       // %bb.0:
406; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
407; CHECK-GI-NEXT:    // kill: def $d2 killed $d2 def $q2
408; CHECK-GI-NEXT:    // kill: def $d4 killed $d4 def $q4
409; CHECK-GI-NEXT:    // kill: def $d1 killed $d1 def $q1
410; CHECK-GI-NEXT:    // kill: def $d3 killed $d3 def $q3
411; CHECK-GI-NEXT:    // kill: def $d5 killed $d5 def $q5
412; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
413; CHECK-GI-NEXT:    mov v2.d[1], v3.d[0]
414; CHECK-GI-NEXT:    mov v4.d[1], v5.d[0]
415; CHECK-GI-NEXT:    movi v1.2d, #0x000000ffffffff
416; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
417; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
418; CHECK-GI-NEXT:    fcvtzu v3.2d, v4.2d
419; CHECK-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
420; CHECK-GI-NEXT:    cmhi v5.2d, v1.2d, v2.2d
421; CHECK-GI-NEXT:    cmhi v6.2d, v1.2d, v3.2d
422; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
423; CHECK-GI-NEXT:    bif v2.16b, v1.16b, v5.16b
424; CHECK-GI-NEXT:    bit v1.16b, v3.16b, v6.16b
425; CHECK-GI-NEXT:    mov d3, v0.d[1]
426; CHECK-GI-NEXT:    mov d4, v2.d[1]
427; CHECK-GI-NEXT:    mov d5, v1.d[1]
428; CHECK-GI-NEXT:    fmov x0, d0
429; CHECK-GI-NEXT:    fmov x2, d2
430; CHECK-GI-NEXT:    fmov x4, d1
431; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 killed $x0
432; CHECK-GI-NEXT:    // kill: def $w2 killed $w2 killed $x2
433; CHECK-GI-NEXT:    // kill: def $w4 killed $w4 killed $x4
434; CHECK-GI-NEXT:    fmov x1, d3
435; CHECK-GI-NEXT:    fmov x3, d4
436; CHECK-GI-NEXT:    fmov x5, d5
437; CHECK-GI-NEXT:    // kill: def $w1 killed $w1 killed $x1
438; CHECK-GI-NEXT:    // kill: def $w3 killed $w3 killed $x3
439; CHECK-GI-NEXT:    // kill: def $w5 killed $w5 killed $x5
440; CHECK-GI-NEXT:    ret
441    %x = call <6 x i32> @llvm.fptoui.sat.v6f64.v6i32(<6 x double> %f)
442    ret <6 x i32> %x
443}
444
445;
446; FP128 to unsigned 32-bit -- Vector size variation
447;
448
449declare <1 x i32> @llvm.fptoui.sat.v1f128.v1i32 (<1 x fp128>)
450declare <2 x i32> @llvm.fptoui.sat.v2f128.v2i32 (<2 x fp128>)
451declare <3 x i32> @llvm.fptoui.sat.v3f128.v3i32 (<3 x fp128>)
452declare <4 x i32> @llvm.fptoui.sat.v4f128.v4i32 (<4 x fp128>)
453
454define <1 x i32> @test_unsigned_v1f128_v1i32(<1 x fp128> %f) {
455; CHECK-SD-LABEL: test_unsigned_v1f128_v1i32:
456; CHECK-SD:       // %bb.0:
457; CHECK-SD-NEXT:    sub sp, sp, #32
458; CHECK-SD-NEXT:    stp x30, x19, [sp, #16] // 16-byte Folded Spill
459; CHECK-SD-NEXT:    .cfi_def_cfa_offset 32
460; CHECK-SD-NEXT:    .cfi_offset w19, -8
461; CHECK-SD-NEXT:    .cfi_offset w30, -16
462; CHECK-SD-NEXT:    adrp x8, .LCPI14_0
463; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
464; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
465; CHECK-SD-NEXT:    bl __getf2
466; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
467; CHECK-SD-NEXT:    mov w19, w0
468; CHECK-SD-NEXT:    bl __fixunstfsi
469; CHECK-SD-NEXT:    adrp x8, .LCPI14_1
470; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
471; CHECK-SD-NEXT:    cmp w19, #0
472; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI14_1]
473; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
474; CHECK-SD-NEXT:    bl __gttf2
475; CHECK-SD-NEXT:    cmp w0, #0
476; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
477; CHECK-SD-NEXT:    ldp x30, x19, [sp, #16] // 16-byte Folded Reload
478; CHECK-SD-NEXT:    fmov s0, w8
479; CHECK-SD-NEXT:    add sp, sp, #32
480; CHECK-SD-NEXT:    ret
481;
482; CHECK-GI-LABEL: test_unsigned_v1f128_v1i32:
483; CHECK-GI:       // %bb.0:
484; CHECK-GI-NEXT:    sub sp, sp, #48
485; CHECK-GI-NEXT:    str x30, [sp, #16] // 8-byte Folded Spill
486; CHECK-GI-NEXT:    stp x20, x19, [sp, #32] // 16-byte Folded Spill
487; CHECK-GI-NEXT:    .cfi_def_cfa_offset 48
488; CHECK-GI-NEXT:    .cfi_offset w19, -8
489; CHECK-GI-NEXT:    .cfi_offset w20, -16
490; CHECK-GI-NEXT:    .cfi_offset w30, -32
491; CHECK-GI-NEXT:    adrp x8, .LCPI14_1
492; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
493; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI14_1]
494; CHECK-GI-NEXT:    bl __getf2
495; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
496; CHECK-GI-NEXT:    cmp w0, #0
497; CHECK-GI-NEXT:    fmov x8, d0
498; CHECK-GI-NEXT:    csel x19, x8, xzr, lt
499; CHECK-GI-NEXT:    mov x8, v0.d[1]
500; CHECK-GI-NEXT:    mov v0.d[0], x19
501; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
502; CHECK-GI-NEXT:    adrp x8, .LCPI14_0
503; CHECK-GI-NEXT:    mov v0.d[1], x20
504; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
505; CHECK-GI-NEXT:    bl __gttf2
506; CHECK-GI-NEXT:    cmp w0, #0
507; CHECK-GI-NEXT:    csel x8, x19, xzr, gt
508; CHECK-GI-NEXT:    mov v0.d[0], x8
509; CHECK-GI-NEXT:    mov x8, #281474976579584 // =0xfffffffe0000
510; CHECK-GI-NEXT:    movk x8, #16414, lsl #48
511; CHECK-GI-NEXT:    csel x8, x20, x8, gt
512; CHECK-GI-NEXT:    mov v0.d[1], x8
513; CHECK-GI-NEXT:    bl __fixunstfsi
514; CHECK-GI-NEXT:    ldp x20, x19, [sp, #32] // 16-byte Folded Reload
515; CHECK-GI-NEXT:    mov v0.s[0], w0
516; CHECK-GI-NEXT:    ldr x30, [sp, #16] // 8-byte Folded Reload
517; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
518; CHECK-GI-NEXT:    add sp, sp, #48
519; CHECK-GI-NEXT:    ret
520    %x = call <1 x i32> @llvm.fptoui.sat.v1f128.v1i32(<1 x fp128> %f)
521    ret <1 x i32> %x
522}
523
524define <2 x i32> @test_unsigned_v2f128_v2i32(<2 x fp128> %f) {
525; CHECK-SD-LABEL: test_unsigned_v2f128_v2i32:
526; CHECK-SD:       // %bb.0:
527; CHECK-SD-NEXT:    sub sp, sp, #96
528; CHECK-SD-NEXT:    str x30, [sp, #64] // 8-byte Folded Spill
529; CHECK-SD-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
530; CHECK-SD-NEXT:    .cfi_def_cfa_offset 96
531; CHECK-SD-NEXT:    .cfi_offset w19, -8
532; CHECK-SD-NEXT:    .cfi_offset w20, -16
533; CHECK-SD-NEXT:    .cfi_offset w30, -32
534; CHECK-SD-NEXT:    mov v2.16b, v1.16b
535; CHECK-SD-NEXT:    stp q1, q0, [sp, #32] // 32-byte Folded Spill
536; CHECK-SD-NEXT:    adrp x8, .LCPI15_0
537; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
538; CHECK-SD-NEXT:    mov v0.16b, v2.16b
539; CHECK-SD-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
540; CHECK-SD-NEXT:    bl __getf2
541; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
542; CHECK-SD-NEXT:    mov w19, w0
543; CHECK-SD-NEXT:    bl __fixunstfsi
544; CHECK-SD-NEXT:    adrp x8, .LCPI15_1
545; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
546; CHECK-SD-NEXT:    cmp w19, #0
547; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI15_1]
548; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
549; CHECK-SD-NEXT:    str q1, [sp] // 16-byte Folded Spill
550; CHECK-SD-NEXT:    bl __gttf2
551; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
552; CHECK-SD-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
553; CHECK-SD-NEXT:    cmp w0, #0
554; CHECK-SD-NEXT:    csinv w20, w19, wzr, le
555; CHECK-SD-NEXT:    bl __getf2
556; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
557; CHECK-SD-NEXT:    mov w19, w0
558; CHECK-SD-NEXT:    bl __fixunstfsi
559; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
560; CHECK-SD-NEXT:    ldr q1, [sp] // 16-byte Folded Reload
561; CHECK-SD-NEXT:    cmp w19, #0
562; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
563; CHECK-SD-NEXT:    bl __gttf2
564; CHECK-SD-NEXT:    cmp w0, #0
565; CHECK-SD-NEXT:    ldr x30, [sp, #64] // 8-byte Folded Reload
566; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
567; CHECK-SD-NEXT:    fmov s0, w8
568; CHECK-SD-NEXT:    mov v0.s[1], w20
569; CHECK-SD-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
570; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
571; CHECK-SD-NEXT:    add sp, sp, #96
572; CHECK-SD-NEXT:    ret
573;
574; CHECK-GI-LABEL: test_unsigned_v2f128_v2i32:
575; CHECK-GI:       // %bb.0:
576; CHECK-GI-NEXT:    sub sp, sp, #96
577; CHECK-GI-NEXT:    str x30, [sp, #48] // 8-byte Folded Spill
578; CHECK-GI-NEXT:    stp x22, x21, [sp, #64] // 16-byte Folded Spill
579; CHECK-GI-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
580; CHECK-GI-NEXT:    .cfi_def_cfa_offset 96
581; CHECK-GI-NEXT:    .cfi_offset w19, -8
582; CHECK-GI-NEXT:    .cfi_offset w20, -16
583; CHECK-GI-NEXT:    .cfi_offset w21, -24
584; CHECK-GI-NEXT:    .cfi_offset w22, -32
585; CHECK-GI-NEXT:    .cfi_offset w30, -48
586; CHECK-GI-NEXT:    adrp x8, .LCPI15_1
587; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
588; CHECK-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI15_1]
589; CHECK-GI-NEXT:    stp q2, q1, [sp, #16] // 32-byte Folded Spill
590; CHECK-GI-NEXT:    mov v1.16b, v2.16b
591; CHECK-GI-NEXT:    bl __getf2
592; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
593; CHECK-GI-NEXT:    cmp w0, #0
594; CHECK-GI-NEXT:    fmov x8, d0
595; CHECK-GI-NEXT:    csel x19, x8, xzr, lt
596; CHECK-GI-NEXT:    mov x8, v0.d[1]
597; CHECK-GI-NEXT:    mov v0.d[0], x19
598; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
599; CHECK-GI-NEXT:    adrp x8, .LCPI15_0
600; CHECK-GI-NEXT:    mov v0.d[1], x20
601; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
602; CHECK-GI-NEXT:    str q1, [sp] // 16-byte Folded Spill
603; CHECK-GI-NEXT:    bl __gttf2
604; CHECK-GI-NEXT:    cmp w0, #0
605; CHECK-GI-NEXT:    mov x21, #281474976579584 // =0xfffffffe0000
606; CHECK-GI-NEXT:    csel x8, x19, xzr, gt
607; CHECK-GI-NEXT:    movk x21, #16414, lsl #48
608; CHECK-GI-NEXT:    mov v0.d[0], x8
609; CHECK-GI-NEXT:    csel x8, x20, x21, gt
610; CHECK-GI-NEXT:    mov v0.d[1], x8
611; CHECK-GI-NEXT:    bl __fixunstfsi
612; CHECK-GI-NEXT:    ldp q1, q0, [sp, #16] // 32-byte Folded Reload
613; CHECK-GI-NEXT:    mov w19, w0
614; CHECK-GI-NEXT:    bl __getf2
615; CHECK-GI-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
616; CHECK-GI-NEXT:    cmp w0, #0
617; CHECK-GI-NEXT:    ldr q1, [sp] // 16-byte Folded Reload
618; CHECK-GI-NEXT:    fmov x8, d0
619; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
620; CHECK-GI-NEXT:    mov x8, v0.d[1]
621; CHECK-GI-NEXT:    mov v0.d[0], x20
622; CHECK-GI-NEXT:    csel x22, x8, xzr, lt
623; CHECK-GI-NEXT:    mov v0.d[1], x22
624; CHECK-GI-NEXT:    bl __gttf2
625; CHECK-GI-NEXT:    cmp w0, #0
626; CHECK-GI-NEXT:    csel x8, x20, xzr, gt
627; CHECK-GI-NEXT:    mov v0.d[0], x8
628; CHECK-GI-NEXT:    csel x8, x22, x21, gt
629; CHECK-GI-NEXT:    mov v0.d[1], x8
630; CHECK-GI-NEXT:    bl __fixunstfsi
631; CHECK-GI-NEXT:    mov v0.s[0], w19
632; CHECK-GI-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
633; CHECK-GI-NEXT:    ldp x22, x21, [sp, #64] // 16-byte Folded Reload
634; CHECK-GI-NEXT:    ldr x30, [sp, #48] // 8-byte Folded Reload
635; CHECK-GI-NEXT:    mov v0.s[1], w0
636; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
637; CHECK-GI-NEXT:    add sp, sp, #96
638; CHECK-GI-NEXT:    ret
639    %x = call <2 x i32> @llvm.fptoui.sat.v2f128.v2i32(<2 x fp128> %f)
640    ret <2 x i32> %x
641}
642
643define <3 x i32> @test_unsigned_v3f128_v3i32(<3 x fp128> %f) {
644; CHECK-SD-LABEL: test_unsigned_v3f128_v3i32:
645; CHECK-SD:       // %bb.0:
646; CHECK-SD-NEXT:    sub sp, sp, #112
647; CHECK-SD-NEXT:    str x30, [sp, #80] // 8-byte Folded Spill
648; CHECK-SD-NEXT:    stp x20, x19, [sp, #96] // 16-byte Folded Spill
649; CHECK-SD-NEXT:    .cfi_def_cfa_offset 112
650; CHECK-SD-NEXT:    .cfi_offset w19, -8
651; CHECK-SD-NEXT:    .cfi_offset w20, -16
652; CHECK-SD-NEXT:    .cfi_offset w30, -32
653; CHECK-SD-NEXT:    stp q0, q2, [sp, #48] // 32-byte Folded Spill
654; CHECK-SD-NEXT:    mov v2.16b, v1.16b
655; CHECK-SD-NEXT:    adrp x8, .LCPI16_0
656; CHECK-SD-NEXT:    str q1, [sp] // 16-byte Folded Spill
657; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
658; CHECK-SD-NEXT:    mov v0.16b, v2.16b
659; CHECK-SD-NEXT:    str q1, [sp, #32] // 16-byte Folded Spill
660; CHECK-SD-NEXT:    bl __getf2
661; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
662; CHECK-SD-NEXT:    mov w19, w0
663; CHECK-SD-NEXT:    bl __fixunstfsi
664; CHECK-SD-NEXT:    adrp x8, .LCPI16_1
665; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
666; CHECK-SD-NEXT:    cmp w19, #0
667; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI16_1]
668; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
669; CHECK-SD-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
670; CHECK-SD-NEXT:    bl __gttf2
671; CHECK-SD-NEXT:    ldp q1, q0, [sp, #32] // 32-byte Folded Reload
672; CHECK-SD-NEXT:    cmp w0, #0
673; CHECK-SD-NEXT:    csinv w20, w19, wzr, le
674; CHECK-SD-NEXT:    bl __getf2
675; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
676; CHECK-SD-NEXT:    mov w19, w0
677; CHECK-SD-NEXT:    bl __fixunstfsi
678; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
679; CHECK-SD-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
680; CHECK-SD-NEXT:    cmp w19, #0
681; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
682; CHECK-SD-NEXT:    bl __gttf2
683; CHECK-SD-NEXT:    cmp w0, #0
684; CHECK-SD-NEXT:    ldr q1, [sp, #32] // 16-byte Folded Reload
685; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
686; CHECK-SD-NEXT:    fmov s0, w8
687; CHECK-SD-NEXT:    mov v0.s[1], w20
688; CHECK-SD-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
689; CHECK-SD-NEXT:    ldr q0, [sp, #64] // 16-byte Folded Reload
690; CHECK-SD-NEXT:    bl __getf2
691; CHECK-SD-NEXT:    ldr q0, [sp, #64] // 16-byte Folded Reload
692; CHECK-SD-NEXT:    mov w19, w0
693; CHECK-SD-NEXT:    bl __fixunstfsi
694; CHECK-SD-NEXT:    ldr q0, [sp, #64] // 16-byte Folded Reload
695; CHECK-SD-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
696; CHECK-SD-NEXT:    cmp w19, #0
697; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
698; CHECK-SD-NEXT:    bl __gttf2
699; CHECK-SD-NEXT:    cmp w0, #0
700; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
701; CHECK-SD-NEXT:    ldr x30, [sp, #80] // 8-byte Folded Reload
702; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
703; CHECK-SD-NEXT:    ldp x20, x19, [sp, #96] // 16-byte Folded Reload
704; CHECK-SD-NEXT:    mov v0.s[2], w8
705; CHECK-SD-NEXT:    add sp, sp, #112
706; CHECK-SD-NEXT:    ret
707;
708; CHECK-GI-LABEL: test_unsigned_v3f128_v3i32:
709; CHECK-GI:       // %bb.0:
710; CHECK-GI-NEXT:    sub sp, sp, #112
711; CHECK-GI-NEXT:    stp x30, x23, [sp, #64] // 16-byte Folded Spill
712; CHECK-GI-NEXT:    stp x22, x21, [sp, #80] // 16-byte Folded Spill
713; CHECK-GI-NEXT:    stp x20, x19, [sp, #96] // 16-byte Folded Spill
714; CHECK-GI-NEXT:    .cfi_def_cfa_offset 112
715; CHECK-GI-NEXT:    .cfi_offset w19, -8
716; CHECK-GI-NEXT:    .cfi_offset w20, -16
717; CHECK-GI-NEXT:    .cfi_offset w21, -24
718; CHECK-GI-NEXT:    .cfi_offset w22, -32
719; CHECK-GI-NEXT:    .cfi_offset w23, -40
720; CHECK-GI-NEXT:    .cfi_offset w30, -48
721; CHECK-GI-NEXT:    adrp x8, .LCPI16_1
722; CHECK-GI-NEXT:    stp q1, q0, [sp] // 32-byte Folded Spill
723; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI16_1]
724; CHECK-GI-NEXT:    stp q1, q2, [sp, #32] // 32-byte Folded Spill
725; CHECK-GI-NEXT:    bl __getf2
726; CHECK-GI-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
727; CHECK-GI-NEXT:    cmp w0, #0
728; CHECK-GI-NEXT:    fmov x8, d0
729; CHECK-GI-NEXT:    csel x19, x8, xzr, lt
730; CHECK-GI-NEXT:    mov x8, v0.d[1]
731; CHECK-GI-NEXT:    mov v0.d[0], x19
732; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
733; CHECK-GI-NEXT:    adrp x8, .LCPI16_0
734; CHECK-GI-NEXT:    mov v0.d[1], x20
735; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
736; CHECK-GI-NEXT:    str q1, [sp, #16] // 16-byte Folded Spill
737; CHECK-GI-NEXT:    bl __gttf2
738; CHECK-GI-NEXT:    cmp w0, #0
739; CHECK-GI-NEXT:    mov x21, #281474976579584 // =0xfffffffe0000
740; CHECK-GI-NEXT:    csel x8, x19, xzr, gt
741; CHECK-GI-NEXT:    movk x21, #16414, lsl #48
742; CHECK-GI-NEXT:    mov v0.d[0], x8
743; CHECK-GI-NEXT:    csel x8, x20, x21, gt
744; CHECK-GI-NEXT:    mov v0.d[1], x8
745; CHECK-GI-NEXT:    bl __fixunstfsi
746; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
747; CHECK-GI-NEXT:    ldr q1, [sp, #32] // 16-byte Folded Reload
748; CHECK-GI-NEXT:    mov w19, w0
749; CHECK-GI-NEXT:    bl __getf2
750; CHECK-GI-NEXT:    ldp q0, q1, [sp] // 32-byte Folded Reload
751; CHECK-GI-NEXT:    cmp w0, #0
752; CHECK-GI-NEXT:    fmov x8, d0
753; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
754; CHECK-GI-NEXT:    mov x8, v0.d[1]
755; CHECK-GI-NEXT:    mov v0.d[0], x20
756; CHECK-GI-NEXT:    csel x22, x8, xzr, lt
757; CHECK-GI-NEXT:    mov v0.d[1], x22
758; CHECK-GI-NEXT:    bl __gttf2
759; CHECK-GI-NEXT:    cmp w0, #0
760; CHECK-GI-NEXT:    csel x8, x20, xzr, gt
761; CHECK-GI-NEXT:    mov v0.d[0], x8
762; CHECK-GI-NEXT:    csel x8, x22, x21, gt
763; CHECK-GI-NEXT:    mov v0.d[1], x8
764; CHECK-GI-NEXT:    bl __fixunstfsi
765; CHECK-GI-NEXT:    ldp q1, q0, [sp, #32] // 32-byte Folded Reload
766; CHECK-GI-NEXT:    mov w20, w0
767; CHECK-GI-NEXT:    bl __getf2
768; CHECK-GI-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
769; CHECK-GI-NEXT:    cmp w0, #0
770; CHECK-GI-NEXT:    ldr q1, [sp, #16] // 16-byte Folded Reload
771; CHECK-GI-NEXT:    fmov x8, d0
772; CHECK-GI-NEXT:    csel x22, x8, xzr, lt
773; CHECK-GI-NEXT:    mov x8, v0.d[1]
774; CHECK-GI-NEXT:    mov v0.d[0], x22
775; CHECK-GI-NEXT:    csel x23, x8, xzr, lt
776; CHECK-GI-NEXT:    mov v0.d[1], x23
777; CHECK-GI-NEXT:    bl __gttf2
778; CHECK-GI-NEXT:    cmp w0, #0
779; CHECK-GI-NEXT:    csel x8, x22, xzr, gt
780; CHECK-GI-NEXT:    mov v0.d[0], x8
781; CHECK-GI-NEXT:    csel x8, x23, x21, gt
782; CHECK-GI-NEXT:    mov v0.d[1], x8
783; CHECK-GI-NEXT:    bl __fixunstfsi
784; CHECK-GI-NEXT:    mov v0.s[0], w19
785; CHECK-GI-NEXT:    ldp x22, x21, [sp, #80] // 16-byte Folded Reload
786; CHECK-GI-NEXT:    ldp x30, x23, [sp, #64] // 16-byte Folded Reload
787; CHECK-GI-NEXT:    mov v0.s[1], w20
788; CHECK-GI-NEXT:    ldp x20, x19, [sp, #96] // 16-byte Folded Reload
789; CHECK-GI-NEXT:    mov v0.s[2], w0
790; CHECK-GI-NEXT:    add sp, sp, #112
791; CHECK-GI-NEXT:    ret
792    %x = call <3 x i32> @llvm.fptoui.sat.v3f128.v3i32(<3 x fp128> %f)
793    ret <3 x i32> %x
794}
795
796define <4 x i32> @test_unsigned_v4f128_v4i32(<4 x fp128> %f) {
797; CHECK-SD-LABEL: test_unsigned_v4f128_v4i32:
798; CHECK-SD:       // %bb.0:
799; CHECK-SD-NEXT:    sub sp, sp, #128
800; CHECK-SD-NEXT:    str x30, [sp, #96] // 8-byte Folded Spill
801; CHECK-SD-NEXT:    stp x20, x19, [sp, #112] // 16-byte Folded Spill
802; CHECK-SD-NEXT:    .cfi_def_cfa_offset 128
803; CHECK-SD-NEXT:    .cfi_offset w19, -8
804; CHECK-SD-NEXT:    .cfi_offset w20, -16
805; CHECK-SD-NEXT:    .cfi_offset w30, -32
806; CHECK-SD-NEXT:    stp q0, q2, [sp, #16] // 32-byte Folded Spill
807; CHECK-SD-NEXT:    mov v2.16b, v1.16b
808; CHECK-SD-NEXT:    adrp x8, .LCPI17_0
809; CHECK-SD-NEXT:    str q1, [sp] // 16-byte Folded Spill
810; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
811; CHECK-SD-NEXT:    str q3, [sp, #80] // 16-byte Folded Spill
812; CHECK-SD-NEXT:    mov v0.16b, v2.16b
813; CHECK-SD-NEXT:    str q1, [sp, #64] // 16-byte Folded Spill
814; CHECK-SD-NEXT:    bl __getf2
815; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
816; CHECK-SD-NEXT:    mov w19, w0
817; CHECK-SD-NEXT:    bl __fixunstfsi
818; CHECK-SD-NEXT:    adrp x8, .LCPI17_1
819; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
820; CHECK-SD-NEXT:    cmp w19, #0
821; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI17_1]
822; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
823; CHECK-SD-NEXT:    str q1, [sp, #48] // 16-byte Folded Spill
824; CHECK-SD-NEXT:    bl __gttf2
825; CHECK-SD-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
826; CHECK-SD-NEXT:    ldr q1, [sp, #64] // 16-byte Folded Reload
827; CHECK-SD-NEXT:    cmp w0, #0
828; CHECK-SD-NEXT:    csinv w20, w19, wzr, le
829; CHECK-SD-NEXT:    bl __getf2
830; CHECK-SD-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
831; CHECK-SD-NEXT:    mov w19, w0
832; CHECK-SD-NEXT:    bl __fixunstfsi
833; CHECK-SD-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
834; CHECK-SD-NEXT:    ldr q1, [sp, #48] // 16-byte Folded Reload
835; CHECK-SD-NEXT:    cmp w19, #0
836; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
837; CHECK-SD-NEXT:    bl __gttf2
838; CHECK-SD-NEXT:    cmp w0, #0
839; CHECK-SD-NEXT:    ldr q1, [sp, #64] // 16-byte Folded Reload
840; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
841; CHECK-SD-NEXT:    fmov s0, w8
842; CHECK-SD-NEXT:    mov v0.s[1], w20
843; CHECK-SD-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
844; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
845; CHECK-SD-NEXT:    bl __getf2
846; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
847; CHECK-SD-NEXT:    mov w19, w0
848; CHECK-SD-NEXT:    bl __fixunstfsi
849; CHECK-SD-NEXT:    ldp q0, q1, [sp, #32] // 32-byte Folded Reload
850; CHECK-SD-NEXT:    cmp w19, #0
851; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
852; CHECK-SD-NEXT:    bl __gttf2
853; CHECK-SD-NEXT:    cmp w0, #0
854; CHECK-SD-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
855; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
856; CHECK-SD-NEXT:    mov v0.s[2], w8
857; CHECK-SD-NEXT:    str q0, [sp, #16] // 16-byte Folded Spill
858; CHECK-SD-NEXT:    ldp q1, q0, [sp, #64] // 32-byte Folded Reload
859; CHECK-SD-NEXT:    bl __getf2
860; CHECK-SD-NEXT:    ldr q0, [sp, #80] // 16-byte Folded Reload
861; CHECK-SD-NEXT:    mov w19, w0
862; CHECK-SD-NEXT:    bl __fixunstfsi
863; CHECK-SD-NEXT:    ldr q0, [sp, #80] // 16-byte Folded Reload
864; CHECK-SD-NEXT:    ldr q1, [sp, #48] // 16-byte Folded Reload
865; CHECK-SD-NEXT:    cmp w19, #0
866; CHECK-SD-NEXT:    csel w19, wzr, w0, lt
867; CHECK-SD-NEXT:    bl __gttf2
868; CHECK-SD-NEXT:    cmp w0, #0
869; CHECK-SD-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
870; CHECK-SD-NEXT:    ldr x30, [sp, #96] // 8-byte Folded Reload
871; CHECK-SD-NEXT:    csinv w8, w19, wzr, le
872; CHECK-SD-NEXT:    ldp x20, x19, [sp, #112] // 16-byte Folded Reload
873; CHECK-SD-NEXT:    mov v0.s[3], w8
874; CHECK-SD-NEXT:    add sp, sp, #128
875; CHECK-SD-NEXT:    ret
876;
877; CHECK-GI-LABEL: test_unsigned_v4f128_v4i32:
878; CHECK-GI:       // %bb.0:
879; CHECK-GI-NEXT:    sub sp, sp, #144
880; CHECK-GI-NEXT:    str x30, [sp, #80] // 8-byte Folded Spill
881; CHECK-GI-NEXT:    stp x24, x23, [sp, #96] // 16-byte Folded Spill
882; CHECK-GI-NEXT:    stp x22, x21, [sp, #112] // 16-byte Folded Spill
883; CHECK-GI-NEXT:    stp x20, x19, [sp, #128] // 16-byte Folded Spill
884; CHECK-GI-NEXT:    .cfi_def_cfa_offset 144
885; CHECK-GI-NEXT:    .cfi_offset w19, -8
886; CHECK-GI-NEXT:    .cfi_offset w20, -16
887; CHECK-GI-NEXT:    .cfi_offset w21, -24
888; CHECK-GI-NEXT:    .cfi_offset w22, -32
889; CHECK-GI-NEXT:    .cfi_offset w23, -40
890; CHECK-GI-NEXT:    .cfi_offset w24, -48
891; CHECK-GI-NEXT:    .cfi_offset w30, -64
892; CHECK-GI-NEXT:    adrp x8, .LCPI17_1
893; CHECK-GI-NEXT:    stp q1, q2, [sp] // 32-byte Folded Spill
894; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI17_1]
895; CHECK-GI-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
896; CHECK-GI-NEXT:    str q3, [sp, #32] // 16-byte Folded Spill
897; CHECK-GI-NEXT:    str q1, [sp, #64] // 16-byte Folded Spill
898; CHECK-GI-NEXT:    bl __getf2
899; CHECK-GI-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
900; CHECK-GI-NEXT:    cmp w0, #0
901; CHECK-GI-NEXT:    fmov x8, d0
902; CHECK-GI-NEXT:    csel x19, x8, xzr, lt
903; CHECK-GI-NEXT:    mov x8, v0.d[1]
904; CHECK-GI-NEXT:    mov v0.d[0], x19
905; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
906; CHECK-GI-NEXT:    adrp x8, .LCPI17_0
907; CHECK-GI-NEXT:    mov v0.d[1], x20
908; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
909; CHECK-GI-NEXT:    str q1, [sp, #48] // 16-byte Folded Spill
910; CHECK-GI-NEXT:    bl __gttf2
911; CHECK-GI-NEXT:    cmp w0, #0
912; CHECK-GI-NEXT:    mov x22, #281474976579584 // =0xfffffffe0000
913; CHECK-GI-NEXT:    csel x8, x19, xzr, gt
914; CHECK-GI-NEXT:    movk x22, #16414, lsl #48
915; CHECK-GI-NEXT:    mov v0.d[0], x8
916; CHECK-GI-NEXT:    csel x8, x20, x22, gt
917; CHECK-GI-NEXT:    mov v0.d[1], x8
918; CHECK-GI-NEXT:    bl __fixunstfsi
919; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
920; CHECK-GI-NEXT:    ldr q1, [sp, #64] // 16-byte Folded Reload
921; CHECK-GI-NEXT:    mov w19, w0
922; CHECK-GI-NEXT:    bl __getf2
923; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
924; CHECK-GI-NEXT:    cmp w0, #0
925; CHECK-GI-NEXT:    ldr q1, [sp, #48] // 16-byte Folded Reload
926; CHECK-GI-NEXT:    fmov x8, d0
927; CHECK-GI-NEXT:    csel x20, x8, xzr, lt
928; CHECK-GI-NEXT:    mov x8, v0.d[1]
929; CHECK-GI-NEXT:    mov v0.d[0], x20
930; CHECK-GI-NEXT:    csel x21, x8, xzr, lt
931; CHECK-GI-NEXT:    mov v0.d[1], x21
932; CHECK-GI-NEXT:    bl __gttf2
933; CHECK-GI-NEXT:    cmp w0, #0
934; CHECK-GI-NEXT:    csel x8, x20, xzr, gt
935; CHECK-GI-NEXT:    mov v0.d[0], x8
936; CHECK-GI-NEXT:    csel x8, x21, x22, gt
937; CHECK-GI-NEXT:    mov v0.d[1], x8
938; CHECK-GI-NEXT:    bl __fixunstfsi
939; CHECK-GI-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
940; CHECK-GI-NEXT:    ldr q1, [sp, #64] // 16-byte Folded Reload
941; CHECK-GI-NEXT:    mov w20, w0
942; CHECK-GI-NEXT:    bl __getf2
943; CHECK-GI-NEXT:    ldr q0, [sp, #16] // 16-byte Folded Reload
944; CHECK-GI-NEXT:    cmp w0, #0
945; CHECK-GI-NEXT:    ldr q1, [sp, #48] // 16-byte Folded Reload
946; CHECK-GI-NEXT:    fmov x8, d0
947; CHECK-GI-NEXT:    csel x21, x8, xzr, lt
948; CHECK-GI-NEXT:    mov x8, v0.d[1]
949; CHECK-GI-NEXT:    mov v0.d[0], x21
950; CHECK-GI-NEXT:    csel x23, x8, xzr, lt
951; CHECK-GI-NEXT:    mov v0.d[1], x23
952; CHECK-GI-NEXT:    bl __gttf2
953; CHECK-GI-NEXT:    cmp w0, #0
954; CHECK-GI-NEXT:    csel x8, x21, xzr, gt
955; CHECK-GI-NEXT:    mov v0.d[0], x8
956; CHECK-GI-NEXT:    csel x8, x23, x22, gt
957; CHECK-GI-NEXT:    mov v0.d[1], x8
958; CHECK-GI-NEXT:    bl __fixunstfsi
959; CHECK-GI-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
960; CHECK-GI-NEXT:    ldr q1, [sp, #64] // 16-byte Folded Reload
961; CHECK-GI-NEXT:    mov w21, w0
962; CHECK-GI-NEXT:    bl __getf2
963; CHECK-GI-NEXT:    ldp q0, q1, [sp, #32] // 32-byte Folded Reload
964; CHECK-GI-NEXT:    cmp w0, #0
965; CHECK-GI-NEXT:    fmov x8, d0
966; CHECK-GI-NEXT:    csel x23, x8, xzr, lt
967; CHECK-GI-NEXT:    mov x8, v0.d[1]
968; CHECK-GI-NEXT:    mov v0.d[0], x23
969; CHECK-GI-NEXT:    csel x24, x8, xzr, lt
970; CHECK-GI-NEXT:    mov v0.d[1], x24
971; CHECK-GI-NEXT:    bl __gttf2
972; CHECK-GI-NEXT:    cmp w0, #0
973; CHECK-GI-NEXT:    csel x8, x23, xzr, gt
974; CHECK-GI-NEXT:    mov v0.d[0], x8
975; CHECK-GI-NEXT:    csel x8, x24, x22, gt
976; CHECK-GI-NEXT:    mov v0.d[1], x8
977; CHECK-GI-NEXT:    bl __fixunstfsi
978; CHECK-GI-NEXT:    mov v0.s[0], w19
979; CHECK-GI-NEXT:    ldp x24, x23, [sp, #96] // 16-byte Folded Reload
980; CHECK-GI-NEXT:    ldr x30, [sp, #80] // 8-byte Folded Reload
981; CHECK-GI-NEXT:    mov v0.s[1], w20
982; CHECK-GI-NEXT:    ldp x20, x19, [sp, #128] // 16-byte Folded Reload
983; CHECK-GI-NEXT:    mov v0.s[2], w21
984; CHECK-GI-NEXT:    ldp x22, x21, [sp, #112] // 16-byte Folded Reload
985; CHECK-GI-NEXT:    mov v0.s[3], w0
986; CHECK-GI-NEXT:    add sp, sp, #144
987; CHECK-GI-NEXT:    ret
988    %x = call <4 x i32> @llvm.fptoui.sat.v4f128.v4i32(<4 x fp128> %f)
989    ret <4 x i32> %x
990}
991
992;
993; FP16 to unsigned 32-bit -- Vector size variation
994;
995
996declare <1 x i32> @llvm.fptoui.sat.v1f16.v1i32 (<1 x half>)
997declare <2 x i32> @llvm.fptoui.sat.v2f16.v2i32 (<2 x half>)
998declare <3 x i32> @llvm.fptoui.sat.v3f16.v3i32 (<3 x half>)
999declare <4 x i32> @llvm.fptoui.sat.v4f16.v4i32 (<4 x half>)
1000declare <5 x i32> @llvm.fptoui.sat.v5f16.v5i32 (<5 x half>)
1001declare <6 x i32> @llvm.fptoui.sat.v6f16.v6i32 (<6 x half>)
1002declare <7 x i32> @llvm.fptoui.sat.v7f16.v7i32 (<7 x half>)
1003declare <8 x i32> @llvm.fptoui.sat.v8f16.v8i32 (<8 x half>)
1004
1005define <1 x i32> @test_unsigned_v1f16_v1i32(<1 x half> %f) {
1006; CHECK-SD-CVT-LABEL: test_unsigned_v1f16_v1i32:
1007; CHECK-SD-CVT:       // %bb.0:
1008; CHECK-SD-CVT-NEXT:    fcvt s0, h0
1009; CHECK-SD-CVT-NEXT:    fcvtzu w8, s0
1010; CHECK-SD-CVT-NEXT:    fmov s0, w8
1011; CHECK-SD-CVT-NEXT:    ret
1012;
1013; CHECK-SD-FP16-LABEL: test_unsigned_v1f16_v1i32:
1014; CHECK-SD-FP16:       // %bb.0:
1015; CHECK-SD-FP16-NEXT:    fcvtzu w8, h0
1016; CHECK-SD-FP16-NEXT:    fmov s0, w8
1017; CHECK-SD-FP16-NEXT:    ret
1018;
1019; CHECK-GI-CVT-LABEL: test_unsigned_v1f16_v1i32:
1020; CHECK-GI-CVT:       // %bb.0:
1021; CHECK-GI-CVT-NEXT:    fcvt s0, h0
1022; CHECK-GI-CVT-NEXT:    fcvtzu w8, s0
1023; CHECK-GI-CVT-NEXT:    mov v0.s[0], w8
1024; CHECK-GI-CVT-NEXT:    // kill: def $d0 killed $d0 killed $q0
1025; CHECK-GI-CVT-NEXT:    ret
1026;
1027; CHECK-GI-FP16-LABEL: test_unsigned_v1f16_v1i32:
1028; CHECK-GI-FP16:       // %bb.0:
1029; CHECK-GI-FP16-NEXT:    fcvtzu w8, h0
1030; CHECK-GI-FP16-NEXT:    mov v0.s[0], w8
1031; CHECK-GI-FP16-NEXT:    // kill: def $d0 killed $d0 killed $q0
1032; CHECK-GI-FP16-NEXT:    ret
1033    %x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
1034    ret <1 x i32> %x
1035}
1036
1037define <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
1038; CHECK-SD-LABEL: test_unsigned_v2f16_v2i32:
1039; CHECK-SD:       // %bb.0:
1040; CHECK-SD-NEXT:    fcvtl v0.4s, v0.4h
1041; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1042; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
1043; CHECK-SD-NEXT:    ret
1044;
1045; CHECK-GI-LABEL: test_unsigned_v2f16_v2i32:
1046; CHECK-GI:       // %bb.0:
1047; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
1048; CHECK-GI-NEXT:    fcvtzu v0.2s, v0.2s
1049; CHECK-GI-NEXT:    ret
1050    %x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f)
1051    ret <2 x i32> %x
1052}
1053
1054define <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) {
1055; CHECK-LABEL: test_unsigned_v3f16_v3i32:
1056; CHECK:       // %bb.0:
1057; CHECK-NEXT:    fcvtl v0.4s, v0.4h
1058; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1059; CHECK-NEXT:    ret
1060    %x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f)
1061    ret <3 x i32> %x
1062}
1063
1064define <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) {
1065; CHECK-LABEL: test_unsigned_v4f16_v4i32:
1066; CHECK:       // %bb.0:
1067; CHECK-NEXT:    fcvtl v0.4s, v0.4h
1068; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1069; CHECK-NEXT:    ret
1070    %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
1071    ret <4 x i32> %x
1072}
1073
1074define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
1075; CHECK-SD-LABEL: test_unsigned_v5f16_v5i32:
1076; CHECK-SD:       // %bb.0:
1077; CHECK-SD-NEXT:    fcvtl v1.4s, v0.4h
1078; CHECK-SD-NEXT:    fcvtl2 v0.4s, v0.8h
1079; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
1080; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1081; CHECK-SD-NEXT:    mov w1, v1.s[1]
1082; CHECK-SD-NEXT:    mov w2, v1.s[2]
1083; CHECK-SD-NEXT:    mov w3, v1.s[3]
1084; CHECK-SD-NEXT:    fmov w0, s1
1085; CHECK-SD-NEXT:    fmov w4, s0
1086; CHECK-SD-NEXT:    ret
1087;
1088; CHECK-GI-LABEL: test_unsigned_v5f16_v5i32:
1089; CHECK-GI:       // %bb.0:
1090; CHECK-GI-NEXT:    fcvtl v1.4s, v0.4h
1091; CHECK-GI-NEXT:    mov v0.h[0], v0.h[4]
1092; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
1093; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
1094; CHECK-GI-NEXT:    mov s2, v1.s[1]
1095; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
1096; CHECK-GI-NEXT:    mov s3, v1.s[2]
1097; CHECK-GI-NEXT:    mov s4, v1.s[3]
1098; CHECK-GI-NEXT:    fmov w0, s1
1099; CHECK-GI-NEXT:    fmov w1, s2
1100; CHECK-GI-NEXT:    fmov w2, s3
1101; CHECK-GI-NEXT:    fmov w4, s0
1102; CHECK-GI-NEXT:    fmov w3, s4
1103; CHECK-GI-NEXT:    ret
1104    %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
1105    ret <5 x i32> %x
1106}
1107
1108define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
1109; CHECK-SD-LABEL: test_unsigned_v6f16_v6i32:
1110; CHECK-SD:       // %bb.0:
1111; CHECK-SD-NEXT:    fcvtl v1.4s, v0.4h
1112; CHECK-SD-NEXT:    fcvtl2 v0.4s, v0.8h
1113; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
1114; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1115; CHECK-SD-NEXT:    mov w1, v1.s[1]
1116; CHECK-SD-NEXT:    mov w2, v1.s[2]
1117; CHECK-SD-NEXT:    mov w5, v0.s[1]
1118; CHECK-SD-NEXT:    mov w3, v1.s[3]
1119; CHECK-SD-NEXT:    fmov w4, s0
1120; CHECK-SD-NEXT:    fmov w0, s1
1121; CHECK-SD-NEXT:    ret
1122;
1123; CHECK-GI-LABEL: test_unsigned_v6f16_v6i32:
1124; CHECK-GI:       // %bb.0:
1125; CHECK-GI-NEXT:    mov v1.h[0], v0.h[4]
1126; CHECK-GI-NEXT:    mov v1.h[1], v0.h[5]
1127; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
1128; CHECK-GI-NEXT:    fcvtl v1.4s, v1.4h
1129; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
1130; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
1131; CHECK-GI-NEXT:    mov s2, v0.s[1]
1132; CHECK-GI-NEXT:    mov s3, v0.s[2]
1133; CHECK-GI-NEXT:    mov s4, v0.s[3]
1134; CHECK-GI-NEXT:    fmov w0, s0
1135; CHECK-GI-NEXT:    mov s5, v1.s[1]
1136; CHECK-GI-NEXT:    fmov w1, s2
1137; CHECK-GI-NEXT:    fmov w2, s3
1138; CHECK-GI-NEXT:    fmov w3, s4
1139; CHECK-GI-NEXT:    fmov w4, s1
1140; CHECK-GI-NEXT:    fmov w5, s5
1141; CHECK-GI-NEXT:    ret
1142    %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
1143    ret <6 x i32> %x
1144}
1145
1146define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
1147; CHECK-SD-LABEL: test_unsigned_v7f16_v7i32:
1148; CHECK-SD:       // %bb.0:
1149; CHECK-SD-NEXT:    fcvtl v1.4s, v0.4h
1150; CHECK-SD-NEXT:    fcvtl2 v0.4s, v0.8h
1151; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
1152; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1153; CHECK-SD-NEXT:    mov w1, v1.s[1]
1154; CHECK-SD-NEXT:    mov w2, v1.s[2]
1155; CHECK-SD-NEXT:    mov w3, v1.s[3]
1156; CHECK-SD-NEXT:    mov w5, v0.s[1]
1157; CHECK-SD-NEXT:    mov w6, v0.s[2]
1158; CHECK-SD-NEXT:    fmov w0, s1
1159; CHECK-SD-NEXT:    fmov w4, s0
1160; CHECK-SD-NEXT:    ret
1161;
1162; CHECK-GI-LABEL: test_unsigned_v7f16_v7i32:
1163; CHECK-GI:       // %bb.0:
1164; CHECK-GI-NEXT:    mov v1.h[0], v0.h[4]
1165; CHECK-GI-NEXT:    mov v1.h[1], v0.h[5]
1166; CHECK-GI-NEXT:    mov v1.h[2], v0.h[6]
1167; CHECK-GI-NEXT:    fcvtl v0.4s, v0.4h
1168; CHECK-GI-NEXT:    fcvtl v1.4s, v1.4h
1169; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
1170; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
1171; CHECK-GI-NEXT:    mov s2, v0.s[1]
1172; CHECK-GI-NEXT:    mov s3, v0.s[2]
1173; CHECK-GI-NEXT:    mov s4, v0.s[3]
1174; CHECK-GI-NEXT:    fmov w0, s0
1175; CHECK-GI-NEXT:    mov s5, v1.s[1]
1176; CHECK-GI-NEXT:    mov s6, v1.s[2]
1177; CHECK-GI-NEXT:    fmov w1, s2
1178; CHECK-GI-NEXT:    fmov w2, s3
1179; CHECK-GI-NEXT:    fmov w3, s4
1180; CHECK-GI-NEXT:    fmov w4, s1
1181; CHECK-GI-NEXT:    fmov w5, s5
1182; CHECK-GI-NEXT:    fmov w6, s6
1183; CHECK-GI-NEXT:    ret
1184    %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
1185    ret <7 x i32> %x
1186}
1187
1188define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
1189; CHECK-SD-LABEL: test_unsigned_v8f16_v8i32:
1190; CHECK-SD:       // %bb.0:
1191; CHECK-SD-NEXT:    fcvtl2 v1.4s, v0.8h
1192; CHECK-SD-NEXT:    fcvtl v0.4s, v0.4h
1193; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
1194; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1195; CHECK-SD-NEXT:    ret
1196;
1197; CHECK-GI-LABEL: test_unsigned_v8f16_v8i32:
1198; CHECK-GI:       // %bb.0:
1199; CHECK-GI-NEXT:    fcvtl v1.4s, v0.4h
1200; CHECK-GI-NEXT:    fcvtl2 v2.4s, v0.8h
1201; CHECK-GI-NEXT:    fcvtzu v0.4s, v1.4s
1202; CHECK-GI-NEXT:    fcvtzu v1.4s, v2.4s
1203; CHECK-GI-NEXT:    ret
1204    %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
1205    ret <8 x i32> %x
1206}
1207
1208;
1209; 2-Vector float to unsigned integer -- result size variation
1210;
1211
1212declare <2 x   i1> @llvm.fptoui.sat.v2f32.v2i1  (<2 x float>)
1213declare <2 x   i8> @llvm.fptoui.sat.v2f32.v2i8  (<2 x float>)
1214declare <2 x  i13> @llvm.fptoui.sat.v2f32.v2i13 (<2 x float>)
1215declare <2 x  i16> @llvm.fptoui.sat.v2f32.v2i16 (<2 x float>)
1216declare <2 x  i19> @llvm.fptoui.sat.v2f32.v2i19 (<2 x float>)
1217declare <2 x  i50> @llvm.fptoui.sat.v2f32.v2i50 (<2 x float>)
1218declare <2 x  i64> @llvm.fptoui.sat.v2f32.v2i64 (<2 x float>)
1219declare <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float>)
1220declare <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float>)
1221
1222define <2 x i1> @test_unsigned_v2f32_v2i1(<2 x float> %f) {
1223; CHECK-LABEL: test_unsigned_v2f32_v2i1:
1224; CHECK:       // %bb.0:
1225; CHECK-NEXT:    movi v1.2s, #1
1226; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1227; CHECK-NEXT:    umin v0.2s, v0.2s, v1.2s
1228; CHECK-NEXT:    ret
1229    %x = call <2 x i1> @llvm.fptoui.sat.v2f32.v2i1(<2 x float> %f)
1230    ret <2 x i1> %x
1231}
1232
1233define <2 x i8> @test_unsigned_v2f32_v2i8(<2 x float> %f) {
1234; CHECK-LABEL: test_unsigned_v2f32_v2i8:
1235; CHECK:       // %bb.0:
1236; CHECK-NEXT:    movi d1, #0x0000ff000000ff
1237; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1238; CHECK-NEXT:    umin v0.2s, v0.2s, v1.2s
1239; CHECK-NEXT:    ret
1240    %x = call <2 x i8> @llvm.fptoui.sat.v2f32.v2i8(<2 x float> %f)
1241    ret <2 x i8> %x
1242}
1243
1244define <2 x i13> @test_unsigned_v2f32_v2i13(<2 x float> %f) {
1245; CHECK-LABEL: test_unsigned_v2f32_v2i13:
1246; CHECK:       // %bb.0:
1247; CHECK-NEXT:    movi v1.2s, #31, msl #8
1248; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1249; CHECK-NEXT:    umin v0.2s, v0.2s, v1.2s
1250; CHECK-NEXT:    ret
1251    %x = call <2 x i13> @llvm.fptoui.sat.v2f32.v2i13(<2 x float> %f)
1252    ret <2 x i13> %x
1253}
1254
1255define <2 x i16> @test_unsigned_v2f32_v2i16(<2 x float> %f) {
1256; CHECK-LABEL: test_unsigned_v2f32_v2i16:
1257; CHECK:       // %bb.0:
1258; CHECK-NEXT:    movi d1, #0x00ffff0000ffff
1259; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1260; CHECK-NEXT:    umin v0.2s, v0.2s, v1.2s
1261; CHECK-NEXT:    ret
1262    %x = call <2 x i16> @llvm.fptoui.sat.v2f32.v2i16(<2 x float> %f)
1263    ret <2 x i16> %x
1264}
1265
1266define <2 x i19> @test_unsigned_v2f32_v2i19(<2 x float> %f) {
1267; CHECK-LABEL: test_unsigned_v2f32_v2i19:
1268; CHECK:       // %bb.0:
1269; CHECK-NEXT:    movi v1.2s, #7, msl #16
1270; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1271; CHECK-NEXT:    umin v0.2s, v0.2s, v1.2s
1272; CHECK-NEXT:    ret
1273    %x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
1274    ret <2 x i19> %x
1275}
1276
1277define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
1278; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
1279; CHECK:       // %bb.0:
1280; CHECK-NEXT:    fcvtzu v0.2s, v0.2s
1281; CHECK-NEXT:    ret
1282    %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
1283    ret <2 x i32> %x
1284}
1285
1286define <2 x i50> @test_unsigned_v2f32_v2i50(<2 x float> %f) {
1287; CHECK-SD-LABEL: test_unsigned_v2f32_v2i50:
1288; CHECK-SD:       // %bb.0:
1289; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
1290; CHECK-SD-NEXT:    mov s1, v0.s[1]
1291; CHECK-SD-NEXT:    fcvtzu x9, s0
1292; CHECK-SD-NEXT:    mov x10, #1125899906842623 // =0x3ffffffffffff
1293; CHECK-SD-NEXT:    fcvtzu x8, s1
1294; CHECK-SD-NEXT:    cmp x8, x10
1295; CHECK-SD-NEXT:    csel x8, x8, x10, lo
1296; CHECK-SD-NEXT:    cmp x9, x10
1297; CHECK-SD-NEXT:    csel x9, x9, x10, lo
1298; CHECK-SD-NEXT:    fmov d0, x9
1299; CHECK-SD-NEXT:    mov v0.d[1], x8
1300; CHECK-SD-NEXT:    ret
1301;
1302; CHECK-GI-LABEL: test_unsigned_v2f32_v2i50:
1303; CHECK-GI:       // %bb.0:
1304; CHECK-GI-NEXT:    fcvtl v0.2d, v0.2s
1305; CHECK-GI-NEXT:    adrp x8, .LCPI32_0
1306; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI32_0]
1307; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
1308; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
1309; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
1310; CHECK-GI-NEXT:    ret
1311    %x = call <2 x i50> @llvm.fptoui.sat.v2f32.v2i50(<2 x float> %f)
1312    ret <2 x i50> %x
1313}
1314
1315define <2 x i64> @test_unsigned_v2f32_v2i64(<2 x float> %f) {
1316; CHECK-LABEL: test_unsigned_v2f32_v2i64:
1317; CHECK:       // %bb.0:
1318; CHECK-NEXT:    fcvtl v0.2d, v0.2s
1319; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
1320; CHECK-NEXT:    ret
1321    %x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
1322    ret <2 x i64> %x
1323}
1324
1325define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
1326; CHECK-SD-LABEL: test_unsigned_v2f32_v2i100:
1327; CHECK-SD:       // %bb.0:
1328; CHECK-SD-NEXT:    sub sp, sp, #64
1329; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1330; CHECK-SD-NEXT:    stp x30, x21, [sp, #32] // 16-byte Folded Spill
1331; CHECK-SD-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
1332; CHECK-SD-NEXT:    .cfi_def_cfa_offset 64
1333; CHECK-SD-NEXT:    .cfi_offset w19, -8
1334; CHECK-SD-NEXT:    .cfi_offset w20, -16
1335; CHECK-SD-NEXT:    .cfi_offset w21, -24
1336; CHECK-SD-NEXT:    .cfi_offset w30, -32
1337; CHECK-SD-NEXT:    .cfi_offset b8, -40
1338; CHECK-SD-NEXT:    .cfi_offset b9, -48
1339; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
1340; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1341; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1342; CHECK-SD-NEXT:    bl __fixunssfti
1343; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1344; CHECK-SD-NEXT:    mov w8, #1904214015 // =0x717fffff
1345; CHECK-SD-NEXT:    mov x21, #68719476735 // =0xfffffffff
1346; CHECK-SD-NEXT:    fmov s9, w8
1347; CHECK-SD-NEXT:    mov s8, v0.s[1]
1348; CHECK-SD-NEXT:    fcmp s0, #0.0
1349; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1350; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1351; CHECK-SD-NEXT:    fcmp s0, s9
1352; CHECK-SD-NEXT:    fmov s0, s8
1353; CHECK-SD-NEXT:    csel x19, x21, x9, gt
1354; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
1355; CHECK-SD-NEXT:    bl __fixunssfti
1356; CHECK-SD-NEXT:    fcmp s8, #0.0
1357; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1358; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1359; CHECK-SD-NEXT:    fcmp s8, s9
1360; CHECK-SD-NEXT:    mov x0, x20
1361; CHECK-SD-NEXT:    mov x1, x19
1362; CHECK-SD-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
1363; CHECK-SD-NEXT:    csel x3, x21, x9, gt
1364; CHECK-SD-NEXT:    ldp x30, x21, [sp, #32] // 16-byte Folded Reload
1365; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1366; CHECK-SD-NEXT:    csinv x2, x8, xzr, le
1367; CHECK-SD-NEXT:    add sp, sp, #64
1368; CHECK-SD-NEXT:    ret
1369;
1370; CHECK-GI-LABEL: test_unsigned_v2f32_v2i100:
1371; CHECK-GI:       // %bb.0:
1372; CHECK-GI-NEXT:    sub sp, sp, #64
1373; CHECK-GI-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1374; CHECK-GI-NEXT:    stp x30, x21, [sp, #32] // 16-byte Folded Spill
1375; CHECK-GI-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
1376; CHECK-GI-NEXT:    .cfi_def_cfa_offset 64
1377; CHECK-GI-NEXT:    .cfi_offset w19, -8
1378; CHECK-GI-NEXT:    .cfi_offset w20, -16
1379; CHECK-GI-NEXT:    .cfi_offset w21, -24
1380; CHECK-GI-NEXT:    .cfi_offset w30, -32
1381; CHECK-GI-NEXT:    .cfi_offset b8, -40
1382; CHECK-GI-NEXT:    .cfi_offset b9, -48
1383; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
1384; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
1385; CHECK-GI-NEXT:    mov s8, v0.s[1]
1386; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 killed $q0
1387; CHECK-GI-NEXT:    bl __fixunssfti
1388; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1389; CHECK-GI-NEXT:    mov w8, #1904214015 // =0x717fffff
1390; CHECK-GI-NEXT:    mov x21, #68719476735 // =0xfffffffff
1391; CHECK-GI-NEXT:    fmov s9, w8
1392; CHECK-GI-NEXT:    fcmp s0, #0.0
1393; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1394; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1395; CHECK-GI-NEXT:    fcmp s0, s9
1396; CHECK-GI-NEXT:    fmov s0, s8
1397; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
1398; CHECK-GI-NEXT:    csel x20, x21, x9, gt
1399; CHECK-GI-NEXT:    bl __fixunssfti
1400; CHECK-GI-NEXT:    fcmp s8, #0.0
1401; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1402; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1403; CHECK-GI-NEXT:    fcmp s8, s9
1404; CHECK-GI-NEXT:    mov x0, x19
1405; CHECK-GI-NEXT:    mov x1, x20
1406; CHECK-GI-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
1407; CHECK-GI-NEXT:    csel x3, x21, x9, gt
1408; CHECK-GI-NEXT:    ldp x30, x21, [sp, #32] // 16-byte Folded Reload
1409; CHECK-GI-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1410; CHECK-GI-NEXT:    csinv x2, x8, xzr, le
1411; CHECK-GI-NEXT:    add sp, sp, #64
1412; CHECK-GI-NEXT:    ret
1413    %x = call <2 x i100> @llvm.fptoui.sat.v2f32.v2i100(<2 x float> %f)
1414    ret <2 x i100> %x
1415}
1416
1417define <2 x i128> @test_unsigned_v2f32_v2i128(<2 x float> %f) {
1418; CHECK-SD-LABEL: test_unsigned_v2f32_v2i128:
1419; CHECK-SD:       // %bb.0:
1420; CHECK-SD-NEXT:    sub sp, sp, #64
1421; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1422; CHECK-SD-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
1423; CHECK-SD-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
1424; CHECK-SD-NEXT:    .cfi_def_cfa_offset 64
1425; CHECK-SD-NEXT:    .cfi_offset w19, -8
1426; CHECK-SD-NEXT:    .cfi_offset w20, -16
1427; CHECK-SD-NEXT:    .cfi_offset w30, -32
1428; CHECK-SD-NEXT:    .cfi_offset b8, -40
1429; CHECK-SD-NEXT:    .cfi_offset b9, -48
1430; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
1431; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1432; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1433; CHECK-SD-NEXT:    bl __fixunssfti
1434; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1435; CHECK-SD-NEXT:    mov w8, #2139095039 // =0x7f7fffff
1436; CHECK-SD-NEXT:    fmov s9, w8
1437; CHECK-SD-NEXT:    mov s8, v0.s[1]
1438; CHECK-SD-NEXT:    fcmp s0, #0.0
1439; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1440; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1441; CHECK-SD-NEXT:    fcmp s0, s9
1442; CHECK-SD-NEXT:    fmov s0, s8
1443; CHECK-SD-NEXT:    csinv x19, x9, xzr, le
1444; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
1445; CHECK-SD-NEXT:    bl __fixunssfti
1446; CHECK-SD-NEXT:    fcmp s8, #0.0
1447; CHECK-SD-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
1448; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1449; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1450; CHECK-SD-NEXT:    fcmp s8, s9
1451; CHECK-SD-NEXT:    mov x0, x19
1452; CHECK-SD-NEXT:    mov x1, x20
1453; CHECK-SD-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
1454; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1455; CHECK-SD-NEXT:    csinv x2, x9, xzr, le
1456; CHECK-SD-NEXT:    csinv x3, x8, xzr, le
1457; CHECK-SD-NEXT:    add sp, sp, #64
1458; CHECK-SD-NEXT:    ret
1459;
1460; CHECK-GI-LABEL: test_unsigned_v2f32_v2i128:
1461; CHECK-GI:       // %bb.0:
1462; CHECK-GI-NEXT:    sub sp, sp, #64
1463; CHECK-GI-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1464; CHECK-GI-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
1465; CHECK-GI-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
1466; CHECK-GI-NEXT:    .cfi_def_cfa_offset 64
1467; CHECK-GI-NEXT:    .cfi_offset w19, -8
1468; CHECK-GI-NEXT:    .cfi_offset w20, -16
1469; CHECK-GI-NEXT:    .cfi_offset w30, -32
1470; CHECK-GI-NEXT:    .cfi_offset b8, -40
1471; CHECK-GI-NEXT:    .cfi_offset b9, -48
1472; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
1473; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
1474; CHECK-GI-NEXT:    mov s8, v0.s[1]
1475; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 killed $q0
1476; CHECK-GI-NEXT:    bl __fixunssfti
1477; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1478; CHECK-GI-NEXT:    mov w8, #2139095039 // =0x7f7fffff
1479; CHECK-GI-NEXT:    fmov s9, w8
1480; CHECK-GI-NEXT:    fcmp s0, #0.0
1481; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1482; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1483; CHECK-GI-NEXT:    fcmp s0, s9
1484; CHECK-GI-NEXT:    fmov s0, s8
1485; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
1486; CHECK-GI-NEXT:    csinv x20, x9, xzr, le
1487; CHECK-GI-NEXT:    bl __fixunssfti
1488; CHECK-GI-NEXT:    fcmp s8, #0.0
1489; CHECK-GI-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
1490; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1491; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1492; CHECK-GI-NEXT:    fcmp s8, s9
1493; CHECK-GI-NEXT:    mov x0, x19
1494; CHECK-GI-NEXT:    mov x1, x20
1495; CHECK-GI-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
1496; CHECK-GI-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1497; CHECK-GI-NEXT:    csinv x2, x8, xzr, le
1498; CHECK-GI-NEXT:    csinv x3, x9, xzr, le
1499; CHECK-GI-NEXT:    add sp, sp, #64
1500; CHECK-GI-NEXT:    ret
1501    %x = call <2 x i128> @llvm.fptoui.sat.v2f32.v2i128(<2 x float> %f)
1502    ret <2 x i128> %x
1503}
1504
1505;
1506; 4-Vector float to unsigned integer -- result size variation
1507;
1508
1509declare <4 x   i1> @llvm.fptoui.sat.v4f32.v4i1  (<4 x float>)
1510declare <4 x   i8> @llvm.fptoui.sat.v4f32.v4i8  (<4 x float>)
1511declare <4 x  i13> @llvm.fptoui.sat.v4f32.v4i13 (<4 x float>)
1512declare <4 x  i16> @llvm.fptoui.sat.v4f32.v4i16 (<4 x float>)
1513declare <4 x  i19> @llvm.fptoui.sat.v4f32.v4i19 (<4 x float>)
1514declare <4 x  i50> @llvm.fptoui.sat.v4f32.v4i50 (<4 x float>)
1515declare <4 x  i64> @llvm.fptoui.sat.v4f32.v4i64 (<4 x float>)
1516declare <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float>)
1517declare <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float>)
1518
1519define <4 x i1> @test_unsigned_v4f32_v4i1(<4 x float> %f) {
1520; CHECK-LABEL: test_unsigned_v4f32_v4i1:
1521; CHECK:       // %bb.0:
1522; CHECK-NEXT:    movi v1.4s, #1
1523; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1524; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
1525; CHECK-NEXT:    xtn v0.4h, v0.4s
1526; CHECK-NEXT:    ret
1527    %x = call <4 x i1> @llvm.fptoui.sat.v4f32.v4i1(<4 x float> %f)
1528    ret <4 x i1> %x
1529}
1530
1531define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
1532; CHECK-LABEL: test_unsigned_v4f32_v4i8:
1533; CHECK:       // %bb.0:
1534; CHECK-NEXT:    movi v1.2d, #0x0000ff000000ff
1535; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1536; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
1537; CHECK-NEXT:    xtn v0.4h, v0.4s
1538; CHECK-NEXT:    ret
1539    %x = call <4 x i8> @llvm.fptoui.sat.v4f32.v4i8(<4 x float> %f)
1540    ret <4 x i8> %x
1541}
1542
1543define <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) {
1544; CHECK-LABEL: test_unsigned_v4f32_v4i13:
1545; CHECK:       // %bb.0:
1546; CHECK-NEXT:    movi v1.4s, #31, msl #8
1547; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1548; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
1549; CHECK-NEXT:    xtn v0.4h, v0.4s
1550; CHECK-NEXT:    ret
1551    %x = call <4 x i13> @llvm.fptoui.sat.v4f32.v4i13(<4 x float> %f)
1552    ret <4 x i13> %x
1553}
1554
1555define <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) {
1556; CHECK-SD-LABEL: test_unsigned_v4f32_v4i16:
1557; CHECK-SD:       // %bb.0:
1558; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
1559; CHECK-SD-NEXT:    uqxtn v0.4h, v0.4s
1560; CHECK-SD-NEXT:    ret
1561;
1562; CHECK-GI-LABEL: test_unsigned_v4f32_v4i16:
1563; CHECK-GI:       // %bb.0:
1564; CHECK-GI-NEXT:    movi v1.2d, #0x00ffff0000ffff
1565; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
1566; CHECK-GI-NEXT:    umin v0.4s, v0.4s, v1.4s
1567; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
1568; CHECK-GI-NEXT:    ret
1569    %x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f)
1570    ret <4 x i16> %x
1571}
1572
1573define <4 x i19> @test_unsigned_v4f32_v4i19(<4 x float> %f) {
1574; CHECK-LABEL: test_unsigned_v4f32_v4i19:
1575; CHECK:       // %bb.0:
1576; CHECK-NEXT:    movi v1.4s, #7, msl #16
1577; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1578; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
1579; CHECK-NEXT:    ret
1580    %x = call <4 x i19> @llvm.fptoui.sat.v4f32.v4i19(<4 x float> %f)
1581    ret <4 x i19> %x
1582}
1583
1584define <4 x i32> @test_unsigned_v4f32_v4i32_duplicate(<4 x float> %f) {
1585; CHECK-LABEL: test_unsigned_v4f32_v4i32_duplicate:
1586; CHECK:       // %bb.0:
1587; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
1588; CHECK-NEXT:    ret
1589    %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
1590    ret <4 x i32> %x
1591}
1592
1593define <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) {
1594; CHECK-LABEL: test_unsigned_v4f32_v4i50:
1595; CHECK:       // %bb.0:
1596; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
1597; CHECK-NEXT:    mov s3, v0.s[1]
1598; CHECK-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
1599; CHECK-NEXT:    fcvtzu x11, s0
1600; CHECK-NEXT:    mov s2, v1.s[1]
1601; CHECK-NEXT:    fcvtzu x9, s1
1602; CHECK-NEXT:    fcvtzu x12, s3
1603; CHECK-NEXT:    fcvtzu x10, s2
1604; CHECK-NEXT:    cmp x9, x8
1605; CHECK-NEXT:    csel x2, x9, x8, lo
1606; CHECK-NEXT:    cmp x10, x8
1607; CHECK-NEXT:    csel x3, x10, x8, lo
1608; CHECK-NEXT:    cmp x11, x8
1609; CHECK-NEXT:    csel x0, x11, x8, lo
1610; CHECK-NEXT:    cmp x12, x8
1611; CHECK-NEXT:    csel x1, x12, x8, lo
1612; CHECK-NEXT:    ret
1613    %x = call <4 x i50> @llvm.fptoui.sat.v4f32.v4i50(<4 x float> %f)
1614    ret <4 x i50> %x
1615}
1616
1617define <4 x i64> @test_unsigned_v4f32_v4i64(<4 x float> %f) {
1618; CHECK-SD-LABEL: test_unsigned_v4f32_v4i64:
1619; CHECK-SD:       // %bb.0:
1620; CHECK-SD-NEXT:    fcvtl2 v1.2d, v0.4s
1621; CHECK-SD-NEXT:    fcvtl v0.2d, v0.2s
1622; CHECK-SD-NEXT:    fcvtzu v1.2d, v1.2d
1623; CHECK-SD-NEXT:    fcvtzu v0.2d, v0.2d
1624; CHECK-SD-NEXT:    ret
1625;
1626; CHECK-GI-LABEL: test_unsigned_v4f32_v4i64:
1627; CHECK-GI:       // %bb.0:
1628; CHECK-GI-NEXT:    fcvtl v1.2d, v0.2s
1629; CHECK-GI-NEXT:    fcvtl2 v2.2d, v0.4s
1630; CHECK-GI-NEXT:    fcvtzu v0.2d, v1.2d
1631; CHECK-GI-NEXT:    fcvtzu v1.2d, v2.2d
1632; CHECK-GI-NEXT:    ret
1633    %x = call <4 x i64> @llvm.fptoui.sat.v4f32.v4i64(<4 x float> %f)
1634    ret <4 x i64> %x
1635}
1636
1637define <4 x i100> @test_unsigned_v4f32_v4i100(<4 x float> %f) {
1638; CHECK-SD-LABEL: test_unsigned_v4f32_v4i100:
1639; CHECK-SD:       // %bb.0:
1640; CHECK-SD-NEXT:    sub sp, sp, #96
1641; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1642; CHECK-SD-NEXT:    stp x30, x25, [sp, #32] // 16-byte Folded Spill
1643; CHECK-SD-NEXT:    stp x24, x23, [sp, #48] // 16-byte Folded Spill
1644; CHECK-SD-NEXT:    stp x22, x21, [sp, #64] // 16-byte Folded Spill
1645; CHECK-SD-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
1646; CHECK-SD-NEXT:    .cfi_def_cfa_offset 96
1647; CHECK-SD-NEXT:    .cfi_offset w19, -8
1648; CHECK-SD-NEXT:    .cfi_offset w20, -16
1649; CHECK-SD-NEXT:    .cfi_offset w21, -24
1650; CHECK-SD-NEXT:    .cfi_offset w22, -32
1651; CHECK-SD-NEXT:    .cfi_offset w23, -40
1652; CHECK-SD-NEXT:    .cfi_offset w24, -48
1653; CHECK-SD-NEXT:    .cfi_offset w25, -56
1654; CHECK-SD-NEXT:    .cfi_offset w30, -64
1655; CHECK-SD-NEXT:    .cfi_offset b8, -72
1656; CHECK-SD-NEXT:    .cfi_offset b9, -80
1657; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1658; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1659; CHECK-SD-NEXT:    bl __fixunssfti
1660; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1661; CHECK-SD-NEXT:    mov w8, #1904214015 // =0x717fffff
1662; CHECK-SD-NEXT:    mov x25, #68719476735 // =0xfffffffff
1663; CHECK-SD-NEXT:    fmov s9, w8
1664; CHECK-SD-NEXT:    mov s8, v0.s[1]
1665; CHECK-SD-NEXT:    fcmp s0, #0.0
1666; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1667; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1668; CHECK-SD-NEXT:    fcmp s0, s9
1669; CHECK-SD-NEXT:    fmov s0, s8
1670; CHECK-SD-NEXT:    csel x19, x25, x9, gt
1671; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
1672; CHECK-SD-NEXT:    bl __fixunssfti
1673; CHECK-SD-NEXT:    fcmp s8, #0.0
1674; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1675; CHECK-SD-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
1676; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1677; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1678; CHECK-SD-NEXT:    fcmp s8, s9
1679; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1680; CHECK-SD-NEXT:    csel x21, x25, x9, gt
1681; CHECK-SD-NEXT:    csinv x22, x8, xzr, le
1682; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1683; CHECK-SD-NEXT:    bl __fixunssfti
1684; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1685; CHECK-SD-NEXT:    mov s8, v0.s[1]
1686; CHECK-SD-NEXT:    fcmp s0, #0.0
1687; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1688; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1689; CHECK-SD-NEXT:    fcmp s0, s9
1690; CHECK-SD-NEXT:    fmov s0, s8
1691; CHECK-SD-NEXT:    csel x23, x25, x9, gt
1692; CHECK-SD-NEXT:    csinv x24, x8, xzr, le
1693; CHECK-SD-NEXT:    bl __fixunssfti
1694; CHECK-SD-NEXT:    fcmp s8, #0.0
1695; CHECK-SD-NEXT:    mov x2, x22
1696; CHECK-SD-NEXT:    mov x3, x21
1697; CHECK-SD-NEXT:    mov x4, x24
1698; CHECK-SD-NEXT:    mov x5, x23
1699; CHECK-SD-NEXT:    ldp x22, x21, [sp, #64] // 16-byte Folded Reload
1700; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
1701; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
1702; CHECK-SD-NEXT:    fcmp s8, s9
1703; CHECK-SD-NEXT:    mov x0, x20
1704; CHECK-SD-NEXT:    mov x1, x19
1705; CHECK-SD-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
1706; CHECK-SD-NEXT:    csel x7, x25, x9, gt
1707; CHECK-SD-NEXT:    ldp x24, x23, [sp, #48] // 16-byte Folded Reload
1708; CHECK-SD-NEXT:    ldp x30, x25, [sp, #32] // 16-byte Folded Reload
1709; CHECK-SD-NEXT:    csinv x6, x8, xzr, le
1710; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1711; CHECK-SD-NEXT:    add sp, sp, #96
1712; CHECK-SD-NEXT:    ret
1713;
1714; CHECK-GI-LABEL: test_unsigned_v4f32_v4i100:
1715; CHECK-GI:       // %bb.0:
1716; CHECK-GI-NEXT:    sub sp, sp, #112
1717; CHECK-GI-NEXT:    stp d11, d10, [sp, #16] // 16-byte Folded Spill
1718; CHECK-GI-NEXT:    stp d9, d8, [sp, #32] // 16-byte Folded Spill
1719; CHECK-GI-NEXT:    stp x30, x25, [sp, #48] // 16-byte Folded Spill
1720; CHECK-GI-NEXT:    stp x24, x23, [sp, #64] // 16-byte Folded Spill
1721; CHECK-GI-NEXT:    stp x22, x21, [sp, #80] // 16-byte Folded Spill
1722; CHECK-GI-NEXT:    stp x20, x19, [sp, #96] // 16-byte Folded Spill
1723; CHECK-GI-NEXT:    .cfi_def_cfa_offset 112
1724; CHECK-GI-NEXT:    .cfi_offset w19, -8
1725; CHECK-GI-NEXT:    .cfi_offset w20, -16
1726; CHECK-GI-NEXT:    .cfi_offset w21, -24
1727; CHECK-GI-NEXT:    .cfi_offset w22, -32
1728; CHECK-GI-NEXT:    .cfi_offset w23, -40
1729; CHECK-GI-NEXT:    .cfi_offset w24, -48
1730; CHECK-GI-NEXT:    .cfi_offset w25, -56
1731; CHECK-GI-NEXT:    .cfi_offset w30, -64
1732; CHECK-GI-NEXT:    .cfi_offset b8, -72
1733; CHECK-GI-NEXT:    .cfi_offset b9, -80
1734; CHECK-GI-NEXT:    .cfi_offset b10, -88
1735; CHECK-GI-NEXT:    .cfi_offset b11, -96
1736; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
1737; CHECK-GI-NEXT:    mov s8, v0.s[1]
1738; CHECK-GI-NEXT:    mov s9, v0.s[2]
1739; CHECK-GI-NEXT:    mov s10, v0.s[3]
1740; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 killed $q0
1741; CHECK-GI-NEXT:    bl __fixunssfti
1742; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1743; CHECK-GI-NEXT:    mov w8, #1904214015 // =0x717fffff
1744; CHECK-GI-NEXT:    mov x25, #68719476735 // =0xfffffffff
1745; CHECK-GI-NEXT:    fmov s11, w8
1746; CHECK-GI-NEXT:    fcmp s0, #0.0
1747; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1748; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1749; CHECK-GI-NEXT:    fcmp s0, s11
1750; CHECK-GI-NEXT:    fmov s0, s8
1751; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
1752; CHECK-GI-NEXT:    csel x20, x25, x9, gt
1753; CHECK-GI-NEXT:    bl __fixunssfti
1754; CHECK-GI-NEXT:    fcmp s8, #0.0
1755; CHECK-GI-NEXT:    fmov s0, s9
1756; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1757; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1758; CHECK-GI-NEXT:    fcmp s8, s11
1759; CHECK-GI-NEXT:    csinv x21, x8, xzr, le
1760; CHECK-GI-NEXT:    csel x22, x25, x9, gt
1761; CHECK-GI-NEXT:    bl __fixunssfti
1762; CHECK-GI-NEXT:    fcmp s9, #0.0
1763; CHECK-GI-NEXT:    fmov s0, s10
1764; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1765; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1766; CHECK-GI-NEXT:    fcmp s9, s11
1767; CHECK-GI-NEXT:    csinv x23, x8, xzr, le
1768; CHECK-GI-NEXT:    csel x24, x25, x9, gt
1769; CHECK-GI-NEXT:    bl __fixunssfti
1770; CHECK-GI-NEXT:    fcmp s10, #0.0
1771; CHECK-GI-NEXT:    mov x2, x21
1772; CHECK-GI-NEXT:    mov x3, x22
1773; CHECK-GI-NEXT:    mov x4, x23
1774; CHECK-GI-NEXT:    mov x5, x24
1775; CHECK-GI-NEXT:    ldp x22, x21, [sp, #80] // 16-byte Folded Reload
1776; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1777; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1778; CHECK-GI-NEXT:    fcmp s10, s11
1779; CHECK-GI-NEXT:    mov x0, x19
1780; CHECK-GI-NEXT:    mov x1, x20
1781; CHECK-GI-NEXT:    ldp x20, x19, [sp, #96] // 16-byte Folded Reload
1782; CHECK-GI-NEXT:    csel x7, x25, x9, gt
1783; CHECK-GI-NEXT:    ldp x24, x23, [sp, #64] // 16-byte Folded Reload
1784; CHECK-GI-NEXT:    ldp x30, x25, [sp, #48] // 16-byte Folded Reload
1785; CHECK-GI-NEXT:    csinv x6, x8, xzr, le
1786; CHECK-GI-NEXT:    ldp d9, d8, [sp, #32] // 16-byte Folded Reload
1787; CHECK-GI-NEXT:    ldp d11, d10, [sp, #16] // 16-byte Folded Reload
1788; CHECK-GI-NEXT:    add sp, sp, #112
1789; CHECK-GI-NEXT:    ret
1790    %x = call <4 x i100> @llvm.fptoui.sat.v4f32.v4i100(<4 x float> %f)
1791    ret <4 x i100> %x
1792}
1793
1794define <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) {
1795; CHECK-SD-LABEL: test_unsigned_v4f32_v4i128:
1796; CHECK-SD:       // %bb.0:
1797; CHECK-SD-NEXT:    sub sp, sp, #96
1798; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
1799; CHECK-SD-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
1800; CHECK-SD-NEXT:    stp x24, x23, [sp, #48] // 16-byte Folded Spill
1801; CHECK-SD-NEXT:    stp x22, x21, [sp, #64] // 16-byte Folded Spill
1802; CHECK-SD-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
1803; CHECK-SD-NEXT:    .cfi_def_cfa_offset 96
1804; CHECK-SD-NEXT:    .cfi_offset w19, -8
1805; CHECK-SD-NEXT:    .cfi_offset w20, -16
1806; CHECK-SD-NEXT:    .cfi_offset w21, -24
1807; CHECK-SD-NEXT:    .cfi_offset w22, -32
1808; CHECK-SD-NEXT:    .cfi_offset w23, -40
1809; CHECK-SD-NEXT:    .cfi_offset w24, -48
1810; CHECK-SD-NEXT:    .cfi_offset w30, -64
1811; CHECK-SD-NEXT:    .cfi_offset b8, -72
1812; CHECK-SD-NEXT:    .cfi_offset b9, -80
1813; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1814; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1815; CHECK-SD-NEXT:    bl __fixunssfti
1816; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1817; CHECK-SD-NEXT:    mov w8, #2139095039 // =0x7f7fffff
1818; CHECK-SD-NEXT:    fmov s9, w8
1819; CHECK-SD-NEXT:    mov s8, v0.s[1]
1820; CHECK-SD-NEXT:    fcmp s0, #0.0
1821; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1822; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1823; CHECK-SD-NEXT:    fcmp s0, s9
1824; CHECK-SD-NEXT:    fmov s0, s8
1825; CHECK-SD-NEXT:    csinv x19, x9, xzr, le
1826; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
1827; CHECK-SD-NEXT:    bl __fixunssfti
1828; CHECK-SD-NEXT:    fcmp s8, #0.0
1829; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1830; CHECK-SD-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
1831; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1832; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1833; CHECK-SD-NEXT:    fcmp s8, s9
1834; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
1835; CHECK-SD-NEXT:    csinv x21, x9, xzr, le
1836; CHECK-SD-NEXT:    csinv x22, x8, xzr, le
1837; CHECK-SD-NEXT:    // kill: def $s0 killed $s0 killed $q0
1838; CHECK-SD-NEXT:    bl __fixunssfti
1839; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1840; CHECK-SD-NEXT:    mov s8, v0.s[1]
1841; CHECK-SD-NEXT:    fcmp s0, #0.0
1842; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1843; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1844; CHECK-SD-NEXT:    fcmp s0, s9
1845; CHECK-SD-NEXT:    fmov s0, s8
1846; CHECK-SD-NEXT:    csinv x23, x9, xzr, le
1847; CHECK-SD-NEXT:    csinv x24, x8, xzr, le
1848; CHECK-SD-NEXT:    bl __fixunssfti
1849; CHECK-SD-NEXT:    fcmp s8, #0.0
1850; CHECK-SD-NEXT:    mov x2, x21
1851; CHECK-SD-NEXT:    mov x3, x22
1852; CHECK-SD-NEXT:    mov x4, x23
1853; CHECK-SD-NEXT:    mov x5, x24
1854; CHECK-SD-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
1855; CHECK-SD-NEXT:    ldp x22, x21, [sp, #64] // 16-byte Folded Reload
1856; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
1857; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
1858; CHECK-SD-NEXT:    fcmp s8, s9
1859; CHECK-SD-NEXT:    mov x0, x19
1860; CHECK-SD-NEXT:    mov x1, x20
1861; CHECK-SD-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
1862; CHECK-SD-NEXT:    ldp x24, x23, [sp, #48] // 16-byte Folded Reload
1863; CHECK-SD-NEXT:    csinv x6, x9, xzr, le
1864; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
1865; CHECK-SD-NEXT:    csinv x7, x8, xzr, le
1866; CHECK-SD-NEXT:    add sp, sp, #96
1867; CHECK-SD-NEXT:    ret
1868;
1869; CHECK-GI-LABEL: test_unsigned_v4f32_v4i128:
1870; CHECK-GI:       // %bb.0:
1871; CHECK-GI-NEXT:    sub sp, sp, #112
1872; CHECK-GI-NEXT:    stp d11, d10, [sp, #16] // 16-byte Folded Spill
1873; CHECK-GI-NEXT:    stp d9, d8, [sp, #32] // 16-byte Folded Spill
1874; CHECK-GI-NEXT:    str x30, [sp, #48] // 8-byte Folded Spill
1875; CHECK-GI-NEXT:    stp x24, x23, [sp, #64] // 16-byte Folded Spill
1876; CHECK-GI-NEXT:    stp x22, x21, [sp, #80] // 16-byte Folded Spill
1877; CHECK-GI-NEXT:    stp x20, x19, [sp, #96] // 16-byte Folded Spill
1878; CHECK-GI-NEXT:    .cfi_def_cfa_offset 112
1879; CHECK-GI-NEXT:    .cfi_offset w19, -8
1880; CHECK-GI-NEXT:    .cfi_offset w20, -16
1881; CHECK-GI-NEXT:    .cfi_offset w21, -24
1882; CHECK-GI-NEXT:    .cfi_offset w22, -32
1883; CHECK-GI-NEXT:    .cfi_offset w23, -40
1884; CHECK-GI-NEXT:    .cfi_offset w24, -48
1885; CHECK-GI-NEXT:    .cfi_offset w30, -64
1886; CHECK-GI-NEXT:    .cfi_offset b8, -72
1887; CHECK-GI-NEXT:    .cfi_offset b9, -80
1888; CHECK-GI-NEXT:    .cfi_offset b10, -88
1889; CHECK-GI-NEXT:    .cfi_offset b11, -96
1890; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
1891; CHECK-GI-NEXT:    mov s8, v0.s[1]
1892; CHECK-GI-NEXT:    mov s9, v0.s[2]
1893; CHECK-GI-NEXT:    mov s10, v0.s[3]
1894; CHECK-GI-NEXT:    // kill: def $s0 killed $s0 killed $q0
1895; CHECK-GI-NEXT:    bl __fixunssfti
1896; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
1897; CHECK-GI-NEXT:    mov w8, #2139095039 // =0x7f7fffff
1898; CHECK-GI-NEXT:    fmov s11, w8
1899; CHECK-GI-NEXT:    fcmp s0, #0.0
1900; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1901; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1902; CHECK-GI-NEXT:    fcmp s0, s11
1903; CHECK-GI-NEXT:    fmov s0, s8
1904; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
1905; CHECK-GI-NEXT:    csinv x20, x9, xzr, le
1906; CHECK-GI-NEXT:    bl __fixunssfti
1907; CHECK-GI-NEXT:    fcmp s8, #0.0
1908; CHECK-GI-NEXT:    fmov s0, s9
1909; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1910; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1911; CHECK-GI-NEXT:    fcmp s8, s11
1912; CHECK-GI-NEXT:    csinv x21, x8, xzr, le
1913; CHECK-GI-NEXT:    csinv x22, x9, xzr, le
1914; CHECK-GI-NEXT:    bl __fixunssfti
1915; CHECK-GI-NEXT:    fcmp s9, #0.0
1916; CHECK-GI-NEXT:    fmov s0, s10
1917; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1918; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1919; CHECK-GI-NEXT:    fcmp s9, s11
1920; CHECK-GI-NEXT:    csinv x23, x8, xzr, le
1921; CHECK-GI-NEXT:    csinv x24, x9, xzr, le
1922; CHECK-GI-NEXT:    bl __fixunssfti
1923; CHECK-GI-NEXT:    fcmp s10, #0.0
1924; CHECK-GI-NEXT:    mov x2, x21
1925; CHECK-GI-NEXT:    mov x3, x22
1926; CHECK-GI-NEXT:    mov x4, x23
1927; CHECK-GI-NEXT:    mov x5, x24
1928; CHECK-GI-NEXT:    ldr x30, [sp, #48] // 8-byte Folded Reload
1929; CHECK-GI-NEXT:    ldp x22, x21, [sp, #80] // 16-byte Folded Reload
1930; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
1931; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
1932; CHECK-GI-NEXT:    fcmp s10, s11
1933; CHECK-GI-NEXT:    mov x0, x19
1934; CHECK-GI-NEXT:    mov x1, x20
1935; CHECK-GI-NEXT:    ldp x20, x19, [sp, #96] // 16-byte Folded Reload
1936; CHECK-GI-NEXT:    ldp x24, x23, [sp, #64] // 16-byte Folded Reload
1937; CHECK-GI-NEXT:    csinv x6, x8, xzr, le
1938; CHECK-GI-NEXT:    ldp d9, d8, [sp, #32] // 16-byte Folded Reload
1939; CHECK-GI-NEXT:    csinv x7, x9, xzr, le
1940; CHECK-GI-NEXT:    ldp d11, d10, [sp, #16] // 16-byte Folded Reload
1941; CHECK-GI-NEXT:    add sp, sp, #112
1942; CHECK-GI-NEXT:    ret
1943    %x = call <4 x i128> @llvm.fptoui.sat.v4f32.v4i128(<4 x float> %f)
1944    ret <4 x i128> %x
1945}
1946
1947;
1948; 2-Vector double to unsigned integer -- result size variation
1949;
1950
1951declare <2 x   i1> @llvm.fptoui.sat.v2f64.v2i1  (<2 x double>)
1952declare <2 x   i8> @llvm.fptoui.sat.v2f64.v2i8  (<2 x double>)
1953declare <2 x  i13> @llvm.fptoui.sat.v2f64.v2i13 (<2 x double>)
1954declare <2 x  i16> @llvm.fptoui.sat.v2f64.v2i16 (<2 x double>)
1955declare <2 x  i19> @llvm.fptoui.sat.v2f64.v2i19 (<2 x double>)
1956declare <2 x  i50> @llvm.fptoui.sat.v2f64.v2i50 (<2 x double>)
1957declare <2 x  i64> @llvm.fptoui.sat.v2f64.v2i64 (<2 x double>)
1958declare <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double>)
1959declare <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double>)
1960
1961define <2 x i1> @test_unsigned_v2f64_v2i1(<2 x double> %f) {
1962; CHECK-SD-LABEL: test_unsigned_v2f64_v2i1:
1963; CHECK-SD:       // %bb.0:
1964; CHECK-SD-NEXT:    mov d1, v0.d[1]
1965; CHECK-SD-NEXT:    fcvtzu w9, d0
1966; CHECK-SD-NEXT:    fcvtzu w8, d1
1967; CHECK-SD-NEXT:    cmp w8, #1
1968; CHECK-SD-NEXT:    csinc w8, w8, wzr, lo
1969; CHECK-SD-NEXT:    cmp w9, #1
1970; CHECK-SD-NEXT:    csinc w9, w9, wzr, lo
1971; CHECK-SD-NEXT:    fmov s0, w9
1972; CHECK-SD-NEXT:    mov v0.s[1], w8
1973; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
1974; CHECK-SD-NEXT:    ret
1975;
1976; CHECK-GI-LABEL: test_unsigned_v2f64_v2i1:
1977; CHECK-GI:       // %bb.0:
1978; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
1979; CHECK-GI-NEXT:    adrp x8, .LCPI46_0
1980; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI46_0]
1981; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
1982; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
1983; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
1984; CHECK-GI-NEXT:    ret
1985    %x = call <2 x i1> @llvm.fptoui.sat.v2f64.v2i1(<2 x double> %f)
1986    ret <2 x i1> %x
1987}
1988
1989define <2 x i8> @test_unsigned_v2f64_v2i8(<2 x double> %f) {
1990; CHECK-SD-LABEL: test_unsigned_v2f64_v2i8:
1991; CHECK-SD:       // %bb.0:
1992; CHECK-SD-NEXT:    mov d1, v0.d[1]
1993; CHECK-SD-NEXT:    fcvtzu w10, d0
1994; CHECK-SD-NEXT:    mov w8, #255 // =0xff
1995; CHECK-SD-NEXT:    fcvtzu w9, d1
1996; CHECK-SD-NEXT:    cmp w9, #255
1997; CHECK-SD-NEXT:    csel w9, w9, w8, lo
1998; CHECK-SD-NEXT:    cmp w10, #255
1999; CHECK-SD-NEXT:    csel w8, w10, w8, lo
2000; CHECK-SD-NEXT:    fmov s0, w8
2001; CHECK-SD-NEXT:    mov v0.s[1], w9
2002; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2003; CHECK-SD-NEXT:    ret
2004;
2005; CHECK-GI-LABEL: test_unsigned_v2f64_v2i8:
2006; CHECK-GI:       // %bb.0:
2007; CHECK-GI-NEXT:    movi v1.2d, #0x000000000000ff
2008; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2009; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2010; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2011; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
2012; CHECK-GI-NEXT:    ret
2013    %x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f)
2014    ret <2 x i8> %x
2015}
2016
2017define <2 x i13> @test_unsigned_v2f64_v2i13(<2 x double> %f) {
2018; CHECK-SD-LABEL: test_unsigned_v2f64_v2i13:
2019; CHECK-SD:       // %bb.0:
2020; CHECK-SD-NEXT:    mov d1, v0.d[1]
2021; CHECK-SD-NEXT:    fcvtzu w9, d0
2022; CHECK-SD-NEXT:    mov w10, #8191 // =0x1fff
2023; CHECK-SD-NEXT:    fcvtzu w8, d1
2024; CHECK-SD-NEXT:    cmp w8, w10
2025; CHECK-SD-NEXT:    csel w8, w8, w10, lo
2026; CHECK-SD-NEXT:    cmp w9, w10
2027; CHECK-SD-NEXT:    csel w9, w9, w10, lo
2028; CHECK-SD-NEXT:    fmov s0, w9
2029; CHECK-SD-NEXT:    mov v0.s[1], w8
2030; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2031; CHECK-SD-NEXT:    ret
2032;
2033; CHECK-GI-LABEL: test_unsigned_v2f64_v2i13:
2034; CHECK-GI:       // %bb.0:
2035; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2036; CHECK-GI-NEXT:    adrp x8, .LCPI48_0
2037; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI48_0]
2038; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2039; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2040; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
2041; CHECK-GI-NEXT:    ret
2042    %x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f)
2043    ret <2 x i13> %x
2044}
2045
2046define <2 x i16> @test_unsigned_v2f64_v2i16(<2 x double> %f) {
2047; CHECK-SD-LABEL: test_unsigned_v2f64_v2i16:
2048; CHECK-SD:       // %bb.0:
2049; CHECK-SD-NEXT:    mov d1, v0.d[1]
2050; CHECK-SD-NEXT:    fcvtzu w9, d0
2051; CHECK-SD-NEXT:    mov w10, #65535 // =0xffff
2052; CHECK-SD-NEXT:    fcvtzu w8, d1
2053; CHECK-SD-NEXT:    cmp w8, w10
2054; CHECK-SD-NEXT:    csel w8, w8, w10, lo
2055; CHECK-SD-NEXT:    cmp w9, w10
2056; CHECK-SD-NEXT:    csel w9, w9, w10, lo
2057; CHECK-SD-NEXT:    fmov s0, w9
2058; CHECK-SD-NEXT:    mov v0.s[1], w8
2059; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2060; CHECK-SD-NEXT:    ret
2061;
2062; CHECK-GI-LABEL: test_unsigned_v2f64_v2i16:
2063; CHECK-GI:       // %bb.0:
2064; CHECK-GI-NEXT:    movi v1.2d, #0x0000000000ffff
2065; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2066; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2067; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2068; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
2069; CHECK-GI-NEXT:    ret
2070    %x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f)
2071    ret <2 x i16> %x
2072}
2073
2074define <2 x i19> @test_unsigned_v2f64_v2i19(<2 x double> %f) {
2075; CHECK-SD-LABEL: test_unsigned_v2f64_v2i19:
2076; CHECK-SD:       // %bb.0:
2077; CHECK-SD-NEXT:    mov d1, v0.d[1]
2078; CHECK-SD-NEXT:    fcvtzu w9, d0
2079; CHECK-SD-NEXT:    mov w10, #524287 // =0x7ffff
2080; CHECK-SD-NEXT:    fcvtzu w8, d1
2081; CHECK-SD-NEXT:    cmp w8, w10
2082; CHECK-SD-NEXT:    csel w8, w8, w10, lo
2083; CHECK-SD-NEXT:    cmp w9, w10
2084; CHECK-SD-NEXT:    csel w9, w9, w10, lo
2085; CHECK-SD-NEXT:    fmov s0, w9
2086; CHECK-SD-NEXT:    mov v0.s[1], w8
2087; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2088; CHECK-SD-NEXT:    ret
2089;
2090; CHECK-GI-LABEL: test_unsigned_v2f64_v2i19:
2091; CHECK-GI:       // %bb.0:
2092; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2093; CHECK-GI-NEXT:    adrp x8, .LCPI50_0
2094; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI50_0]
2095; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2096; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2097; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
2098; CHECK-GI-NEXT:    ret
2099    %x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f)
2100    ret <2 x i19> %x
2101}
2102
2103define <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) {
2104; CHECK-SD-LABEL: test_unsigned_v2f64_v2i32_duplicate:
2105; CHECK-SD:       // %bb.0:
2106; CHECK-SD-NEXT:    mov d1, v0.d[1]
2107; CHECK-SD-NEXT:    fcvtzu w8, d0
2108; CHECK-SD-NEXT:    fcvtzu w9, d1
2109; CHECK-SD-NEXT:    fmov s0, w8
2110; CHECK-SD-NEXT:    mov v0.s[1], w9
2111; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2112; CHECK-SD-NEXT:    ret
2113;
2114; CHECK-GI-LABEL: test_unsigned_v2f64_v2i32_duplicate:
2115; CHECK-GI:       // %bb.0:
2116; CHECK-GI-NEXT:    movi v1.2d, #0x000000ffffffff
2117; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2118; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2119; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2120; CHECK-GI-NEXT:    xtn v0.2s, v0.2d
2121; CHECK-GI-NEXT:    ret
2122    %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
2123    ret <2 x i32> %x
2124}
2125
2126define <2 x i50> @test_unsigned_v2f64_v2i50(<2 x double> %f) {
2127; CHECK-SD-LABEL: test_unsigned_v2f64_v2i50:
2128; CHECK-SD:       // %bb.0:
2129; CHECK-SD-NEXT:    mov d1, v0.d[1]
2130; CHECK-SD-NEXT:    fcvtzu x9, d0
2131; CHECK-SD-NEXT:    mov x10, #1125899906842623 // =0x3ffffffffffff
2132; CHECK-SD-NEXT:    fcvtzu x8, d1
2133; CHECK-SD-NEXT:    cmp x8, x10
2134; CHECK-SD-NEXT:    csel x8, x8, x10, lo
2135; CHECK-SD-NEXT:    cmp x9, x10
2136; CHECK-SD-NEXT:    csel x9, x9, x10, lo
2137; CHECK-SD-NEXT:    fmov d0, x9
2138; CHECK-SD-NEXT:    mov v0.d[1], x8
2139; CHECK-SD-NEXT:    ret
2140;
2141; CHECK-GI-LABEL: test_unsigned_v2f64_v2i50:
2142; CHECK-GI:       // %bb.0:
2143; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
2144; CHECK-GI-NEXT:    adrp x8, .LCPI52_0
2145; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI52_0]
2146; CHECK-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
2147; CHECK-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
2148; CHECK-GI-NEXT:    ret
2149    %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
2150    ret <2 x i50> %x
2151}
2152
2153define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
2154; CHECK-LABEL: test_unsigned_v2f64_v2i64:
2155; CHECK:       // %bb.0:
2156; CHECK-NEXT:    fcvtzu v0.2d, v0.2d
2157; CHECK-NEXT:    ret
2158    %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
2159    ret <2 x i64> %x
2160}
2161
2162define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
2163; CHECK-SD-LABEL: test_unsigned_v2f64_v2i100:
2164; CHECK-SD:       // %bb.0:
2165; CHECK-SD-NEXT:    sub sp, sp, #64
2166; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2167; CHECK-SD-NEXT:    stp x30, x21, [sp, #32] // 16-byte Folded Spill
2168; CHECK-SD-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
2169; CHECK-SD-NEXT:    .cfi_def_cfa_offset 64
2170; CHECK-SD-NEXT:    .cfi_offset w19, -8
2171; CHECK-SD-NEXT:    .cfi_offset w20, -16
2172; CHECK-SD-NEXT:    .cfi_offset w21, -24
2173; CHECK-SD-NEXT:    .cfi_offset w30, -32
2174; CHECK-SD-NEXT:    .cfi_offset b8, -40
2175; CHECK-SD-NEXT:    .cfi_offset b9, -48
2176; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
2177; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2178; CHECK-SD-NEXT:    bl __fixunsdfti
2179; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2180; CHECK-SD-NEXT:    mov x8, #5057542381537067007 // =0x462fffffffffffff
2181; CHECK-SD-NEXT:    mov x21, #68719476735 // =0xfffffffff
2182; CHECK-SD-NEXT:    fmov d9, x8
2183; CHECK-SD-NEXT:    mov d8, v0.d[1]
2184; CHECK-SD-NEXT:    fcmp d0, #0.0
2185; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2186; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2187; CHECK-SD-NEXT:    fcmp d0, d9
2188; CHECK-SD-NEXT:    fmov d0, d8
2189; CHECK-SD-NEXT:    csel x19, x21, x9, gt
2190; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
2191; CHECK-SD-NEXT:    bl __fixunsdfti
2192; CHECK-SD-NEXT:    fcmp d8, #0.0
2193; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2194; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2195; CHECK-SD-NEXT:    fcmp d8, d9
2196; CHECK-SD-NEXT:    mov x0, x20
2197; CHECK-SD-NEXT:    mov x1, x19
2198; CHECK-SD-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
2199; CHECK-SD-NEXT:    csel x3, x21, x9, gt
2200; CHECK-SD-NEXT:    ldp x30, x21, [sp, #32] // 16-byte Folded Reload
2201; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2202; CHECK-SD-NEXT:    csinv x2, x8, xzr, le
2203; CHECK-SD-NEXT:    add sp, sp, #64
2204; CHECK-SD-NEXT:    ret
2205;
2206; CHECK-GI-LABEL: test_unsigned_v2f64_v2i100:
2207; CHECK-GI:       // %bb.0:
2208; CHECK-GI-NEXT:    sub sp, sp, #64
2209; CHECK-GI-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2210; CHECK-GI-NEXT:    stp x30, x21, [sp, #32] // 16-byte Folded Spill
2211; CHECK-GI-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
2212; CHECK-GI-NEXT:    .cfi_def_cfa_offset 64
2213; CHECK-GI-NEXT:    .cfi_offset w19, -8
2214; CHECK-GI-NEXT:    .cfi_offset w20, -16
2215; CHECK-GI-NEXT:    .cfi_offset w21, -24
2216; CHECK-GI-NEXT:    .cfi_offset w30, -32
2217; CHECK-GI-NEXT:    .cfi_offset b8, -40
2218; CHECK-GI-NEXT:    .cfi_offset b9, -48
2219; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
2220; CHECK-GI-NEXT:    mov d8, v0.d[1]
2221; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
2222; CHECK-GI-NEXT:    bl __fixunsdfti
2223; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2224; CHECK-GI-NEXT:    mov x8, #5057542381537067007 // =0x462fffffffffffff
2225; CHECK-GI-NEXT:    mov x21, #68719476735 // =0xfffffffff
2226; CHECK-GI-NEXT:    fmov d9, x8
2227; CHECK-GI-NEXT:    fcmp d0, #0.0
2228; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
2229; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
2230; CHECK-GI-NEXT:    fcmp d0, d9
2231; CHECK-GI-NEXT:    fmov d0, d8
2232; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
2233; CHECK-GI-NEXT:    csel x20, x21, x9, gt
2234; CHECK-GI-NEXT:    bl __fixunsdfti
2235; CHECK-GI-NEXT:    fcmp d8, #0.0
2236; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
2237; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
2238; CHECK-GI-NEXT:    fcmp d8, d9
2239; CHECK-GI-NEXT:    mov x0, x19
2240; CHECK-GI-NEXT:    mov x1, x20
2241; CHECK-GI-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
2242; CHECK-GI-NEXT:    csel x3, x21, x9, gt
2243; CHECK-GI-NEXT:    ldp x30, x21, [sp, #32] // 16-byte Folded Reload
2244; CHECK-GI-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2245; CHECK-GI-NEXT:    csinv x2, x8, xzr, le
2246; CHECK-GI-NEXT:    add sp, sp, #64
2247; CHECK-GI-NEXT:    ret
2248    %x = call <2 x i100> @llvm.fptoui.sat.v2f64.v2i100(<2 x double> %f)
2249    ret <2 x i100> %x
2250}
2251
2252define <2 x i128> @test_unsigned_v2f64_v2i128(<2 x double> %f) {
2253; CHECK-SD-LABEL: test_unsigned_v2f64_v2i128:
2254; CHECK-SD:       // %bb.0:
2255; CHECK-SD-NEXT:    sub sp, sp, #64
2256; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2257; CHECK-SD-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
2258; CHECK-SD-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
2259; CHECK-SD-NEXT:    .cfi_def_cfa_offset 64
2260; CHECK-SD-NEXT:    .cfi_offset w19, -8
2261; CHECK-SD-NEXT:    .cfi_offset w20, -16
2262; CHECK-SD-NEXT:    .cfi_offset w30, -32
2263; CHECK-SD-NEXT:    .cfi_offset b8, -40
2264; CHECK-SD-NEXT:    .cfi_offset b9, -48
2265; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
2266; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
2267; CHECK-SD-NEXT:    bl __fixunsdfti
2268; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2269; CHECK-SD-NEXT:    mov x8, #5183643171103440895 // =0x47efffffffffffff
2270; CHECK-SD-NEXT:    fmov d9, x8
2271; CHECK-SD-NEXT:    mov d8, v0.d[1]
2272; CHECK-SD-NEXT:    fcmp d0, #0.0
2273; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2274; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2275; CHECK-SD-NEXT:    fcmp d0, d9
2276; CHECK-SD-NEXT:    fmov d0, d8
2277; CHECK-SD-NEXT:    csinv x19, x9, xzr, le
2278; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
2279; CHECK-SD-NEXT:    bl __fixunsdfti
2280; CHECK-SD-NEXT:    fcmp d8, #0.0
2281; CHECK-SD-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
2282; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2283; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2284; CHECK-SD-NEXT:    fcmp d8, d9
2285; CHECK-SD-NEXT:    mov x0, x19
2286; CHECK-SD-NEXT:    mov x1, x20
2287; CHECK-SD-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
2288; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2289; CHECK-SD-NEXT:    csinv x2, x9, xzr, le
2290; CHECK-SD-NEXT:    csinv x3, x8, xzr, le
2291; CHECK-SD-NEXT:    add sp, sp, #64
2292; CHECK-SD-NEXT:    ret
2293;
2294; CHECK-GI-LABEL: test_unsigned_v2f64_v2i128:
2295; CHECK-GI:       // %bb.0:
2296; CHECK-GI-NEXT:    sub sp, sp, #64
2297; CHECK-GI-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2298; CHECK-GI-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
2299; CHECK-GI-NEXT:    stp x20, x19, [sp, #48] // 16-byte Folded Spill
2300; CHECK-GI-NEXT:    .cfi_def_cfa_offset 64
2301; CHECK-GI-NEXT:    .cfi_offset w19, -8
2302; CHECK-GI-NEXT:    .cfi_offset w20, -16
2303; CHECK-GI-NEXT:    .cfi_offset w30, -32
2304; CHECK-GI-NEXT:    .cfi_offset b8, -40
2305; CHECK-GI-NEXT:    .cfi_offset b9, -48
2306; CHECK-GI-NEXT:    str q0, [sp] // 16-byte Folded Spill
2307; CHECK-GI-NEXT:    mov d8, v0.d[1]
2308; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
2309; CHECK-GI-NEXT:    bl __fixunsdfti
2310; CHECK-GI-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2311; CHECK-GI-NEXT:    mov x8, #5183643171103440895 // =0x47efffffffffffff
2312; CHECK-GI-NEXT:    fmov d9, x8
2313; CHECK-GI-NEXT:    fcmp d0, #0.0
2314; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
2315; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
2316; CHECK-GI-NEXT:    fcmp d0, d9
2317; CHECK-GI-NEXT:    fmov d0, d8
2318; CHECK-GI-NEXT:    csinv x19, x8, xzr, le
2319; CHECK-GI-NEXT:    csinv x20, x9, xzr, le
2320; CHECK-GI-NEXT:    bl __fixunsdfti
2321; CHECK-GI-NEXT:    fcmp d8, #0.0
2322; CHECK-GI-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
2323; CHECK-GI-NEXT:    csel x8, xzr, x0, lt
2324; CHECK-GI-NEXT:    csel x9, xzr, x1, lt
2325; CHECK-GI-NEXT:    fcmp d8, d9
2326; CHECK-GI-NEXT:    mov x0, x19
2327; CHECK-GI-NEXT:    mov x1, x20
2328; CHECK-GI-NEXT:    ldp x20, x19, [sp, #48] // 16-byte Folded Reload
2329; CHECK-GI-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2330; CHECK-GI-NEXT:    csinv x2, x8, xzr, le
2331; CHECK-GI-NEXT:    csinv x3, x9, xzr, le
2332; CHECK-GI-NEXT:    add sp, sp, #64
2333; CHECK-GI-NEXT:    ret
2334    %x = call <2 x i128> @llvm.fptoui.sat.v2f64.v2i128(<2 x double> %f)
2335    ret <2 x i128> %x
2336}
2337
2338;
2339; 4-Vector half to unsigned integer -- result size variation
2340;
2341
2342declare <4 x   i1> @llvm.fptoui.sat.v4f16.v4i1  (<4 x half>)
2343declare <4 x   i8> @llvm.fptoui.sat.v4f16.v4i8  (<4 x half>)
2344declare <4 x  i13> @llvm.fptoui.sat.v4f16.v4i13 (<4 x half>)
2345declare <4 x  i16> @llvm.fptoui.sat.v4f16.v4i16 (<4 x half>)
2346declare <4 x  i19> @llvm.fptoui.sat.v4f16.v4i19 (<4 x half>)
2347declare <4 x  i50> @llvm.fptoui.sat.v4f16.v4i50 (<4 x half>)
2348declare <4 x  i64> @llvm.fptoui.sat.v4f16.v4i64 (<4 x half>)
2349declare <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half>)
2350declare <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half>)
2351
2352define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
2353; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i1:
2354; CHECK-SD-CVT:       // %bb.0:
2355; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2356; CHECK-SD-CVT-NEXT:    movi v1.4s, #1
2357; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2358; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2359; CHECK-SD-CVT-NEXT:    xtn v0.4h, v0.4s
2360; CHECK-SD-CVT-NEXT:    ret
2361;
2362; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i1:
2363; CHECK-SD-FP16:       // %bb.0:
2364; CHECK-SD-FP16-NEXT:    movi v1.4h, #1
2365; CHECK-SD-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2366; CHECK-SD-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2367; CHECK-SD-FP16-NEXT:    ret
2368;
2369; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i1:
2370; CHECK-GI-CVT:       // %bb.0:
2371; CHECK-GI-CVT-NEXT:    fcvtl v0.4s, v0.4h
2372; CHECK-GI-CVT-NEXT:    movi v1.4s, #1
2373; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2374; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2375; CHECK-GI-CVT-NEXT:    xtn v0.4h, v0.4s
2376; CHECK-GI-CVT-NEXT:    ret
2377;
2378; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i1:
2379; CHECK-GI-FP16:       // %bb.0:
2380; CHECK-GI-FP16-NEXT:    movi v1.4h, #1
2381; CHECK-GI-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2382; CHECK-GI-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2383; CHECK-GI-FP16-NEXT:    ret
2384    %x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
2385    ret <4 x i1> %x
2386}
2387
2388define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
2389; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i8:
2390; CHECK-SD-CVT:       // %bb.0:
2391; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2392; CHECK-SD-CVT-NEXT:    movi v1.2d, #0x0000ff000000ff
2393; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2394; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2395; CHECK-SD-CVT-NEXT:    xtn v0.4h, v0.4s
2396; CHECK-SD-CVT-NEXT:    ret
2397;
2398; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i8:
2399; CHECK-SD-FP16:       // %bb.0:
2400; CHECK-SD-FP16-NEXT:    movi d1, #0xff00ff00ff00ff
2401; CHECK-SD-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2402; CHECK-SD-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2403; CHECK-SD-FP16-NEXT:    ret
2404;
2405; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i8:
2406; CHECK-GI-CVT:       // %bb.0:
2407; CHECK-GI-CVT-NEXT:    fcvtl v0.4s, v0.4h
2408; CHECK-GI-CVT-NEXT:    movi v1.2d, #0x0000ff000000ff
2409; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2410; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2411; CHECK-GI-CVT-NEXT:    xtn v0.4h, v0.4s
2412; CHECK-GI-CVT-NEXT:    ret
2413;
2414; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i8:
2415; CHECK-GI-FP16:       // %bb.0:
2416; CHECK-GI-FP16-NEXT:    movi d1, #0xff00ff00ff00ff
2417; CHECK-GI-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2418; CHECK-GI-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2419; CHECK-GI-FP16-NEXT:    ret
2420    %x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
2421    ret <4 x i8> %x
2422}
2423
2424define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
2425; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i13:
2426; CHECK-SD-CVT:       // %bb.0:
2427; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2428; CHECK-SD-CVT-NEXT:    movi v1.4s, #31, msl #8
2429; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2430; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2431; CHECK-SD-CVT-NEXT:    xtn v0.4h, v0.4s
2432; CHECK-SD-CVT-NEXT:    ret
2433;
2434; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i13:
2435; CHECK-SD-FP16:       // %bb.0:
2436; CHECK-SD-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2437; CHECK-SD-FP16-NEXT:    mvni v1.4h, #224, lsl #8
2438; CHECK-SD-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2439; CHECK-SD-FP16-NEXT:    ret
2440;
2441; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i13:
2442; CHECK-GI-CVT:       // %bb.0:
2443; CHECK-GI-CVT-NEXT:    fcvtl v0.4s, v0.4h
2444; CHECK-GI-CVT-NEXT:    movi v1.4s, #31, msl #8
2445; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2446; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2447; CHECK-GI-CVT-NEXT:    xtn v0.4h, v0.4s
2448; CHECK-GI-CVT-NEXT:    ret
2449;
2450; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i13:
2451; CHECK-GI-FP16:       // %bb.0:
2452; CHECK-GI-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2453; CHECK-GI-FP16-NEXT:    mvni v1.4h, #224, lsl #8
2454; CHECK-GI-FP16-NEXT:    umin v0.4h, v0.4h, v1.4h
2455; CHECK-GI-FP16-NEXT:    ret
2456    %x = call <4 x i13> @llvm.fptoui.sat.v4f16.v4i13(<4 x half> %f)
2457    ret <4 x i13> %x
2458}
2459
2460define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
2461; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i16:
2462; CHECK-SD-CVT:       // %bb.0:
2463; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2464; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2465; CHECK-SD-CVT-NEXT:    uqxtn v0.4h, v0.4s
2466; CHECK-SD-CVT-NEXT:    ret
2467;
2468; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i16:
2469; CHECK-SD-FP16:       // %bb.0:
2470; CHECK-SD-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2471; CHECK-SD-FP16-NEXT:    ret
2472;
2473; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i16:
2474; CHECK-GI-CVT:       // %bb.0:
2475; CHECK-GI-CVT-NEXT:    fcvtl v0.4s, v0.4h
2476; CHECK-GI-CVT-NEXT:    movi v1.2d, #0x00ffff0000ffff
2477; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2478; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2479; CHECK-GI-CVT-NEXT:    xtn v0.4h, v0.4s
2480; CHECK-GI-CVT-NEXT:    ret
2481;
2482; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i16:
2483; CHECK-GI-FP16:       // %bb.0:
2484; CHECK-GI-FP16-NEXT:    fcvtzu v0.4h, v0.4h
2485; CHECK-GI-FP16-NEXT:    ret
2486    %x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
2487    ret <4 x i16> %x
2488}
2489
2490define <4 x i19> @test_unsigned_v4f16_v4i19(<4 x half> %f) {
2491; CHECK-LABEL: test_unsigned_v4f16_v4i19:
2492; CHECK:       // %bb.0:
2493; CHECK-NEXT:    fcvtl v0.4s, v0.4h
2494; CHECK-NEXT:    movi v1.4s, #7, msl #16
2495; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
2496; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
2497; CHECK-NEXT:    ret
2498    %x = call <4 x i19> @llvm.fptoui.sat.v4f16.v4i19(<4 x half> %f)
2499    ret <4 x i19> %x
2500}
2501
2502define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
2503; CHECK-LABEL: test_unsigned_v4f16_v4i32_duplicate:
2504; CHECK:       // %bb.0:
2505; CHECK-NEXT:    fcvtl v0.4s, v0.4h
2506; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
2507; CHECK-NEXT:    ret
2508    %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
2509    ret <4 x i32> %x
2510}
2511
2512define <4 x i50> @test_unsigned_v4f16_v4i50(<4 x half> %f) {
2513; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i50:
2514; CHECK-SD-CVT:       // %bb.0:
2515; CHECK-SD-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
2516; CHECK-SD-CVT-NEXT:    mov h1, v0.h[1]
2517; CHECK-SD-CVT-NEXT:    mov h2, v0.h[2]
2518; CHECK-SD-CVT-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
2519; CHECK-SD-CVT-NEXT:    mov h3, v0.h[3]
2520; CHECK-SD-CVT-NEXT:    fcvt s0, h0
2521; CHECK-SD-CVT-NEXT:    fcvt s1, h1
2522; CHECK-SD-CVT-NEXT:    fcvt s2, h2
2523; CHECK-SD-CVT-NEXT:    fcvt s3, h3
2524; CHECK-SD-CVT-NEXT:    fcvtzu x9, s0
2525; CHECK-SD-CVT-NEXT:    fcvtzu x10, s1
2526; CHECK-SD-CVT-NEXT:    fcvtzu x11, s2
2527; CHECK-SD-CVT-NEXT:    fcvtzu x12, s3
2528; CHECK-SD-CVT-NEXT:    cmp x9, x8
2529; CHECK-SD-CVT-NEXT:    csel x0, x9, x8, lo
2530; CHECK-SD-CVT-NEXT:    cmp x10, x8
2531; CHECK-SD-CVT-NEXT:    csel x1, x10, x8, lo
2532; CHECK-SD-CVT-NEXT:    cmp x11, x8
2533; CHECK-SD-CVT-NEXT:    csel x2, x11, x8, lo
2534; CHECK-SD-CVT-NEXT:    cmp x12, x8
2535; CHECK-SD-CVT-NEXT:    csel x3, x12, x8, lo
2536; CHECK-SD-CVT-NEXT:    ret
2537;
2538; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i50:
2539; CHECK-SD-FP16:       // %bb.0:
2540; CHECK-SD-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2541; CHECK-SD-FP16-NEXT:    mov h1, v0.h[1]
2542; CHECK-SD-FP16-NEXT:    mov h2, v0.h[2]
2543; CHECK-SD-FP16-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
2544; CHECK-SD-FP16-NEXT:    mov h3, v0.h[3]
2545; CHECK-SD-FP16-NEXT:    fcvtzu x9, h0
2546; CHECK-SD-FP16-NEXT:    fcvtzu x10, h1
2547; CHECK-SD-FP16-NEXT:    fcvtzu x11, h2
2548; CHECK-SD-FP16-NEXT:    fcvtzu x12, h3
2549; CHECK-SD-FP16-NEXT:    cmp x9, x8
2550; CHECK-SD-FP16-NEXT:    csel x0, x9, x8, lo
2551; CHECK-SD-FP16-NEXT:    cmp x10, x8
2552; CHECK-SD-FP16-NEXT:    csel x1, x10, x8, lo
2553; CHECK-SD-FP16-NEXT:    cmp x11, x8
2554; CHECK-SD-FP16-NEXT:    csel x2, x11, x8, lo
2555; CHECK-SD-FP16-NEXT:    cmp x12, x8
2556; CHECK-SD-FP16-NEXT:    csel x3, x12, x8, lo
2557; CHECK-SD-FP16-NEXT:    ret
2558;
2559; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i50:
2560; CHECK-GI-CVT:       // %bb.0:
2561; CHECK-GI-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
2562; CHECK-GI-CVT-NEXT:    mov h1, v0.h[1]
2563; CHECK-GI-CVT-NEXT:    mov h2, v0.h[2]
2564; CHECK-GI-CVT-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
2565; CHECK-GI-CVT-NEXT:    mov h3, v0.h[3]
2566; CHECK-GI-CVT-NEXT:    fcvt s0, h0
2567; CHECK-GI-CVT-NEXT:    fcvt s1, h1
2568; CHECK-GI-CVT-NEXT:    fcvt s2, h2
2569; CHECK-GI-CVT-NEXT:    fcvt s3, h3
2570; CHECK-GI-CVT-NEXT:    fcvtzu x9, s0
2571; CHECK-GI-CVT-NEXT:    fcvtzu x10, s1
2572; CHECK-GI-CVT-NEXT:    fcvtzu x11, s2
2573; CHECK-GI-CVT-NEXT:    fcvtzu x12, s3
2574; CHECK-GI-CVT-NEXT:    cmp x9, x8
2575; CHECK-GI-CVT-NEXT:    csel x0, x9, x8, lo
2576; CHECK-GI-CVT-NEXT:    cmp x10, x8
2577; CHECK-GI-CVT-NEXT:    csel x1, x10, x8, lo
2578; CHECK-GI-CVT-NEXT:    cmp x11, x8
2579; CHECK-GI-CVT-NEXT:    csel x2, x11, x8, lo
2580; CHECK-GI-CVT-NEXT:    cmp x12, x8
2581; CHECK-GI-CVT-NEXT:    csel x3, x12, x8, lo
2582; CHECK-GI-CVT-NEXT:    ret
2583;
2584; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i50:
2585; CHECK-GI-FP16:       // %bb.0:
2586; CHECK-GI-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2587; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
2588; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
2589; CHECK-GI-FP16-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
2590; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
2591; CHECK-GI-FP16-NEXT:    fcvtzu x9, h0
2592; CHECK-GI-FP16-NEXT:    fcvtzu x10, h1
2593; CHECK-GI-FP16-NEXT:    fcvtzu x11, h2
2594; CHECK-GI-FP16-NEXT:    fcvtzu x12, h3
2595; CHECK-GI-FP16-NEXT:    cmp x9, x8
2596; CHECK-GI-FP16-NEXT:    csel x0, x9, x8, lo
2597; CHECK-GI-FP16-NEXT:    cmp x10, x8
2598; CHECK-GI-FP16-NEXT:    csel x1, x10, x8, lo
2599; CHECK-GI-FP16-NEXT:    cmp x11, x8
2600; CHECK-GI-FP16-NEXT:    csel x2, x11, x8, lo
2601; CHECK-GI-FP16-NEXT:    cmp x12, x8
2602; CHECK-GI-FP16-NEXT:    csel x3, x12, x8, lo
2603; CHECK-GI-FP16-NEXT:    ret
2604    %x = call <4 x i50> @llvm.fptoui.sat.v4f16.v4i50(<4 x half> %f)
2605    ret <4 x i50> %x
2606}
2607
2608define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
2609; CHECK-SD-CVT-LABEL: test_unsigned_v4f16_v4i64:
2610; CHECK-SD-CVT:       // %bb.0:
2611; CHECK-SD-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
2612; CHECK-SD-CVT-NEXT:    mov h1, v0.h[2]
2613; CHECK-SD-CVT-NEXT:    mov h2, v0.h[1]
2614; CHECK-SD-CVT-NEXT:    mov h3, v0.h[3]
2615; CHECK-SD-CVT-NEXT:    fcvt s0, h0
2616; CHECK-SD-CVT-NEXT:    fcvt s1, h1
2617; CHECK-SD-CVT-NEXT:    fcvt s2, h2
2618; CHECK-SD-CVT-NEXT:    fcvt s3, h3
2619; CHECK-SD-CVT-NEXT:    fcvtzu x8, s0
2620; CHECK-SD-CVT-NEXT:    fcvtzu x9, s1
2621; CHECK-SD-CVT-NEXT:    fcvtzu x10, s2
2622; CHECK-SD-CVT-NEXT:    fcvtzu x11, s3
2623; CHECK-SD-CVT-NEXT:    fmov d0, x8
2624; CHECK-SD-CVT-NEXT:    fmov d1, x9
2625; CHECK-SD-CVT-NEXT:    mov v0.d[1], x10
2626; CHECK-SD-CVT-NEXT:    mov v1.d[1], x11
2627; CHECK-SD-CVT-NEXT:    ret
2628;
2629; CHECK-SD-FP16-LABEL: test_unsigned_v4f16_v4i64:
2630; CHECK-SD-FP16:       // %bb.0:
2631; CHECK-SD-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2632; CHECK-SD-FP16-NEXT:    mov h1, v0.h[2]
2633; CHECK-SD-FP16-NEXT:    mov h2, v0.h[1]
2634; CHECK-SD-FP16-NEXT:    mov h3, v0.h[3]
2635; CHECK-SD-FP16-NEXT:    fcvtzu x8, h0
2636; CHECK-SD-FP16-NEXT:    fcvtzu x9, h1
2637; CHECK-SD-FP16-NEXT:    fcvtzu x10, h2
2638; CHECK-SD-FP16-NEXT:    fcvtzu x11, h3
2639; CHECK-SD-FP16-NEXT:    fmov d0, x8
2640; CHECK-SD-FP16-NEXT:    fmov d1, x9
2641; CHECK-SD-FP16-NEXT:    mov v0.d[1], x10
2642; CHECK-SD-FP16-NEXT:    mov v1.d[1], x11
2643; CHECK-SD-FP16-NEXT:    ret
2644;
2645; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i64:
2646; CHECK-GI-CVT:       // %bb.0:
2647; CHECK-GI-CVT-NEXT:    fcvtl v0.4s, v0.4h
2648; CHECK-GI-CVT-NEXT:    fcvtl v1.2d, v0.2s
2649; CHECK-GI-CVT-NEXT:    fcvtl2 v2.2d, v0.4s
2650; CHECK-GI-CVT-NEXT:    fcvtzu v0.2d, v1.2d
2651; CHECK-GI-CVT-NEXT:    fcvtzu v1.2d, v2.2d
2652; CHECK-GI-CVT-NEXT:    ret
2653;
2654; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i64:
2655; CHECK-GI-FP16:       // %bb.0:
2656; CHECK-GI-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2657; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
2658; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
2659; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
2660; CHECK-GI-FP16-NEXT:    fcvt d0, h0
2661; CHECK-GI-FP16-NEXT:    fcvt d1, h1
2662; CHECK-GI-FP16-NEXT:    fcvt d2, h2
2663; CHECK-GI-FP16-NEXT:    fcvt d3, h3
2664; CHECK-GI-FP16-NEXT:    mov v0.d[1], v1.d[0]
2665; CHECK-GI-FP16-NEXT:    mov v2.d[1], v3.d[0]
2666; CHECK-GI-FP16-NEXT:    fcvtzu v0.2d, v0.2d
2667; CHECK-GI-FP16-NEXT:    fcvtzu v1.2d, v2.2d
2668; CHECK-GI-FP16-NEXT:    ret
2669    %x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
2670    ret <4 x i64> %x
2671}
2672
2673define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) {
2674; CHECK-SD-LABEL: test_unsigned_v4f16_v4i100:
2675; CHECK-SD:       // %bb.0:
2676; CHECK-SD-NEXT:    sub sp, sp, #96
2677; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2678; CHECK-SD-NEXT:    stp x30, x25, [sp, #32] // 16-byte Folded Spill
2679; CHECK-SD-NEXT:    stp x24, x23, [sp, #48] // 16-byte Folded Spill
2680; CHECK-SD-NEXT:    stp x22, x21, [sp, #64] // 16-byte Folded Spill
2681; CHECK-SD-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
2682; CHECK-SD-NEXT:    .cfi_def_cfa_offset 96
2683; CHECK-SD-NEXT:    .cfi_offset w19, -8
2684; CHECK-SD-NEXT:    .cfi_offset w20, -16
2685; CHECK-SD-NEXT:    .cfi_offset w21, -24
2686; CHECK-SD-NEXT:    .cfi_offset w22, -32
2687; CHECK-SD-NEXT:    .cfi_offset w23, -40
2688; CHECK-SD-NEXT:    .cfi_offset w24, -48
2689; CHECK-SD-NEXT:    .cfi_offset w25, -56
2690; CHECK-SD-NEXT:    .cfi_offset w30, -64
2691; CHECK-SD-NEXT:    .cfi_offset b8, -72
2692; CHECK-SD-NEXT:    .cfi_offset b9, -80
2693; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
2694; CHECK-SD-NEXT:    mov h1, v0.h[1]
2695; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
2696; CHECK-SD-NEXT:    fcvt s8, h1
2697; CHECK-SD-NEXT:    fmov s0, s8
2698; CHECK-SD-NEXT:    bl __fixunssfti
2699; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2700; CHECK-SD-NEXT:    mov w8, #1904214015 // =0x717fffff
2701; CHECK-SD-NEXT:    fcmp s8, #0.0
2702; CHECK-SD-NEXT:    fmov s9, w8
2703; CHECK-SD-NEXT:    mov x25, #68719476735 // =0xfffffffff
2704; CHECK-SD-NEXT:    mov h0, v0.h[2]
2705; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2706; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2707; CHECK-SD-NEXT:    fcmp s8, s9
2708; CHECK-SD-NEXT:    fcvt s8, h0
2709; CHECK-SD-NEXT:    csel x19, x25, x8, gt
2710; CHECK-SD-NEXT:    csinv x20, x9, xzr, le
2711; CHECK-SD-NEXT:    fmov s0, s8
2712; CHECK-SD-NEXT:    bl __fixunssfti
2713; CHECK-SD-NEXT:    fcmp s8, #0.0
2714; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2715; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2716; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2717; CHECK-SD-NEXT:    fcmp s8, s9
2718; CHECK-SD-NEXT:    fcvt s8, h0
2719; CHECK-SD-NEXT:    csel x21, x25, x9, gt
2720; CHECK-SD-NEXT:    csinv x22, x8, xzr, le
2721; CHECK-SD-NEXT:    fmov s0, s8
2722; CHECK-SD-NEXT:    bl __fixunssfti
2723; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2724; CHECK-SD-NEXT:    fcmp s8, #0.0
2725; CHECK-SD-NEXT:    mov h0, v0.h[3]
2726; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2727; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2728; CHECK-SD-NEXT:    fcmp s8, s9
2729; CHECK-SD-NEXT:    fcvt s8, h0
2730; CHECK-SD-NEXT:    csel x23, x25, x9, gt
2731; CHECK-SD-NEXT:    csinv x24, x8, xzr, le
2732; CHECK-SD-NEXT:    fmov s0, s8
2733; CHECK-SD-NEXT:    bl __fixunssfti
2734; CHECK-SD-NEXT:    fcmp s8, #0.0
2735; CHECK-SD-NEXT:    mov x2, x20
2736; CHECK-SD-NEXT:    mov x3, x19
2737; CHECK-SD-NEXT:    mov x4, x22
2738; CHECK-SD-NEXT:    mov x5, x21
2739; CHECK-SD-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
2740; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2741; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2742; CHECK-SD-NEXT:    fcmp s8, s9
2743; CHECK-SD-NEXT:    mov x0, x24
2744; CHECK-SD-NEXT:    mov x1, x23
2745; CHECK-SD-NEXT:    ldp x22, x21, [sp, #64] // 16-byte Folded Reload
2746; CHECK-SD-NEXT:    csel x7, x25, x9, gt
2747; CHECK-SD-NEXT:    ldp x24, x23, [sp, #48] // 16-byte Folded Reload
2748; CHECK-SD-NEXT:    ldp x30, x25, [sp, #32] // 16-byte Folded Reload
2749; CHECK-SD-NEXT:    csinv x6, x8, xzr, le
2750; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2751; CHECK-SD-NEXT:    add sp, sp, #96
2752; CHECK-SD-NEXT:    ret
2753;
2754; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i100:
2755; CHECK-GI-CVT:       // %bb.0:
2756; CHECK-GI-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
2757; CHECK-GI-CVT-NEXT:    mov h1, v0.h[1]
2758; CHECK-GI-CVT-NEXT:    mov h2, v0.h[2]
2759; CHECK-GI-CVT-NEXT:    mov x1, xzr
2760; CHECK-GI-CVT-NEXT:    mov h3, v0.h[3]
2761; CHECK-GI-CVT-NEXT:    fcvt s0, h0
2762; CHECK-GI-CVT-NEXT:    mov x3, xzr
2763; CHECK-GI-CVT-NEXT:    mov x5, xzr
2764; CHECK-GI-CVT-NEXT:    mov x7, xzr
2765; CHECK-GI-CVT-NEXT:    fcvt s1, h1
2766; CHECK-GI-CVT-NEXT:    fcvt s2, h2
2767; CHECK-GI-CVT-NEXT:    fcvt s3, h3
2768; CHECK-GI-CVT-NEXT:    fcvtzu x0, s0
2769; CHECK-GI-CVT-NEXT:    fcvtzu x2, s1
2770; CHECK-GI-CVT-NEXT:    fcvtzu x4, s2
2771; CHECK-GI-CVT-NEXT:    fcvtzu x6, s3
2772; CHECK-GI-CVT-NEXT:    ret
2773;
2774; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i100:
2775; CHECK-GI-FP16:       // %bb.0:
2776; CHECK-GI-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2777; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
2778; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
2779; CHECK-GI-FP16-NEXT:    mov x1, xzr
2780; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
2781; CHECK-GI-FP16-NEXT:    fcvtzu x0, h0
2782; CHECK-GI-FP16-NEXT:    mov x3, xzr
2783; CHECK-GI-FP16-NEXT:    mov x5, xzr
2784; CHECK-GI-FP16-NEXT:    mov x7, xzr
2785; CHECK-GI-FP16-NEXT:    fcvtzu x2, h1
2786; CHECK-GI-FP16-NEXT:    fcvtzu x4, h2
2787; CHECK-GI-FP16-NEXT:    fcvtzu x6, h3
2788; CHECK-GI-FP16-NEXT:    ret
2789    %x = call <4 x i100> @llvm.fptoui.sat.v4f16.v4i100(<4 x half> %f)
2790    ret <4 x i100> %x
2791}
2792
2793define <4 x i128> @test_unsigned_v4f16_v4i128(<4 x half> %f) {
2794; CHECK-SD-LABEL: test_unsigned_v4f16_v4i128:
2795; CHECK-SD:       // %bb.0:
2796; CHECK-SD-NEXT:    sub sp, sp, #96
2797; CHECK-SD-NEXT:    stp d9, d8, [sp, #16] // 16-byte Folded Spill
2798; CHECK-SD-NEXT:    str x30, [sp, #32] // 8-byte Folded Spill
2799; CHECK-SD-NEXT:    stp x24, x23, [sp, #48] // 16-byte Folded Spill
2800; CHECK-SD-NEXT:    stp x22, x21, [sp, #64] // 16-byte Folded Spill
2801; CHECK-SD-NEXT:    stp x20, x19, [sp, #80] // 16-byte Folded Spill
2802; CHECK-SD-NEXT:    .cfi_def_cfa_offset 96
2803; CHECK-SD-NEXT:    .cfi_offset w19, -8
2804; CHECK-SD-NEXT:    .cfi_offset w20, -16
2805; CHECK-SD-NEXT:    .cfi_offset w21, -24
2806; CHECK-SD-NEXT:    .cfi_offset w22, -32
2807; CHECK-SD-NEXT:    .cfi_offset w23, -40
2808; CHECK-SD-NEXT:    .cfi_offset w24, -48
2809; CHECK-SD-NEXT:    .cfi_offset w30, -64
2810; CHECK-SD-NEXT:    .cfi_offset b8, -72
2811; CHECK-SD-NEXT:    .cfi_offset b9, -80
2812; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
2813; CHECK-SD-NEXT:    fcvt s8, h0
2814; CHECK-SD-NEXT:    str q0, [sp] // 16-byte Folded Spill
2815; CHECK-SD-NEXT:    fmov s0, s8
2816; CHECK-SD-NEXT:    bl __fixunssfti
2817; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2818; CHECK-SD-NEXT:    mov w8, #2139095039 // =0x7f7fffff
2819; CHECK-SD-NEXT:    fcmp s8, #0.0
2820; CHECK-SD-NEXT:    fmov s9, w8
2821; CHECK-SD-NEXT:    mov h0, v0.h[1]
2822; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
2823; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
2824; CHECK-SD-NEXT:    fcmp s8, s9
2825; CHECK-SD-NEXT:    fcvt s8, h0
2826; CHECK-SD-NEXT:    csinv x19, x8, xzr, le
2827; CHECK-SD-NEXT:    csinv x20, x9, xzr, le
2828; CHECK-SD-NEXT:    fmov s0, s8
2829; CHECK-SD-NEXT:    bl __fixunssfti
2830; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2831; CHECK-SD-NEXT:    fcmp s8, #0.0
2832; CHECK-SD-NEXT:    mov h0, v0.h[2]
2833; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2834; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2835; CHECK-SD-NEXT:    fcmp s8, s9
2836; CHECK-SD-NEXT:    fcvt s8, h0
2837; CHECK-SD-NEXT:    csinv x21, x9, xzr, le
2838; CHECK-SD-NEXT:    csinv x22, x8, xzr, le
2839; CHECK-SD-NEXT:    fmov s0, s8
2840; CHECK-SD-NEXT:    bl __fixunssfti
2841; CHECK-SD-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
2842; CHECK-SD-NEXT:    fcmp s8, #0.0
2843; CHECK-SD-NEXT:    mov h0, v0.h[3]
2844; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2845; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2846; CHECK-SD-NEXT:    fcmp s8, s9
2847; CHECK-SD-NEXT:    fcvt s8, h0
2848; CHECK-SD-NEXT:    csinv x23, x9, xzr, le
2849; CHECK-SD-NEXT:    csinv x24, x8, xzr, le
2850; CHECK-SD-NEXT:    fmov s0, s8
2851; CHECK-SD-NEXT:    bl __fixunssfti
2852; CHECK-SD-NEXT:    fcmp s8, #0.0
2853; CHECK-SD-NEXT:    mov x2, x21
2854; CHECK-SD-NEXT:    mov x3, x22
2855; CHECK-SD-NEXT:    mov x4, x23
2856; CHECK-SD-NEXT:    mov x5, x24
2857; CHECK-SD-NEXT:    ldr x30, [sp, #32] // 8-byte Folded Reload
2858; CHECK-SD-NEXT:    ldp x22, x21, [sp, #64] // 16-byte Folded Reload
2859; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
2860; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
2861; CHECK-SD-NEXT:    fcmp s8, s9
2862; CHECK-SD-NEXT:    mov x0, x19
2863; CHECK-SD-NEXT:    mov x1, x20
2864; CHECK-SD-NEXT:    ldp x20, x19, [sp, #80] // 16-byte Folded Reload
2865; CHECK-SD-NEXT:    ldp x24, x23, [sp, #48] // 16-byte Folded Reload
2866; CHECK-SD-NEXT:    csinv x6, x9, xzr, le
2867; CHECK-SD-NEXT:    ldp d9, d8, [sp, #16] // 16-byte Folded Reload
2868; CHECK-SD-NEXT:    csinv x7, x8, xzr, le
2869; CHECK-SD-NEXT:    add sp, sp, #96
2870; CHECK-SD-NEXT:    ret
2871;
2872; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i128:
2873; CHECK-GI-CVT:       // %bb.0:
2874; CHECK-GI-CVT-NEXT:    // kill: def $d0 killed $d0 def $q0
2875; CHECK-GI-CVT-NEXT:    mov h1, v0.h[1]
2876; CHECK-GI-CVT-NEXT:    mov h2, v0.h[2]
2877; CHECK-GI-CVT-NEXT:    mov x1, xzr
2878; CHECK-GI-CVT-NEXT:    mov h3, v0.h[3]
2879; CHECK-GI-CVT-NEXT:    fcvt s0, h0
2880; CHECK-GI-CVT-NEXT:    mov x3, xzr
2881; CHECK-GI-CVT-NEXT:    mov x5, xzr
2882; CHECK-GI-CVT-NEXT:    mov x7, xzr
2883; CHECK-GI-CVT-NEXT:    fcvt s1, h1
2884; CHECK-GI-CVT-NEXT:    fcvt s2, h2
2885; CHECK-GI-CVT-NEXT:    fcvt s3, h3
2886; CHECK-GI-CVT-NEXT:    fcvtzu x0, s0
2887; CHECK-GI-CVT-NEXT:    fcvtzu x2, s1
2888; CHECK-GI-CVT-NEXT:    fcvtzu x4, s2
2889; CHECK-GI-CVT-NEXT:    fcvtzu x6, s3
2890; CHECK-GI-CVT-NEXT:    ret
2891;
2892; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i128:
2893; CHECK-GI-FP16:       // %bb.0:
2894; CHECK-GI-FP16-NEXT:    // kill: def $d0 killed $d0 def $q0
2895; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
2896; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
2897; CHECK-GI-FP16-NEXT:    mov x1, xzr
2898; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
2899; CHECK-GI-FP16-NEXT:    fcvtzu x0, h0
2900; CHECK-GI-FP16-NEXT:    mov x3, xzr
2901; CHECK-GI-FP16-NEXT:    mov x5, xzr
2902; CHECK-GI-FP16-NEXT:    mov x7, xzr
2903; CHECK-GI-FP16-NEXT:    fcvtzu x2, h1
2904; CHECK-GI-FP16-NEXT:    fcvtzu x4, h2
2905; CHECK-GI-FP16-NEXT:    fcvtzu x6, h3
2906; CHECK-GI-FP16-NEXT:    ret
2907    %x = call <4 x i128> @llvm.fptoui.sat.v4f16.v4i128(<4 x half> %f)
2908    ret <4 x i128> %x
2909}
2910
2911;
2912; 8-Vector half to unsigned integer -- result size variation
2913;
2914
2915declare <8 x   i1> @llvm.fptoui.sat.v8f16.v8i1  (<8 x half>)
2916declare <8 x   i8> @llvm.fptoui.sat.v8f16.v8i8  (<8 x half>)
2917declare <8 x  i13> @llvm.fptoui.sat.v8f16.v8i13 (<8 x half>)
2918declare <8 x  i16> @llvm.fptoui.sat.v8f16.v8i16 (<8 x half>)
2919declare <8 x  i19> @llvm.fptoui.sat.v8f16.v8i19 (<8 x half>)
2920declare <8 x  i50> @llvm.fptoui.sat.v8f16.v8i50 (<8 x half>)
2921declare <8 x  i64> @llvm.fptoui.sat.v8f16.v8i64 (<8 x half>)
2922declare <8 x i100> @llvm.fptoui.sat.v8f16.v8i100(<8 x half>)
2923declare <8 x i128> @llvm.fptoui.sat.v8f16.v8i128(<8 x half>)
2924
2925define <8 x i1> @test_unsigned_v8f16_v8i1(<8 x half> %f) {
2926; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i1:
2927; CHECK-SD-CVT:       // %bb.0:
2928; CHECK-SD-CVT-NEXT:    fcvtl2 v2.4s, v0.8h
2929; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2930; CHECK-SD-CVT-NEXT:    movi v1.4s, #1
2931; CHECK-SD-CVT-NEXT:    fcvtzu v2.4s, v2.4s
2932; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2933; CHECK-SD-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
2934; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2935; CHECK-SD-CVT-NEXT:    uzp1 v0.8h, v0.8h, v2.8h
2936; CHECK-SD-CVT-NEXT:    xtn v0.8b, v0.8h
2937; CHECK-SD-CVT-NEXT:    ret
2938;
2939; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i1:
2940; CHECK-SD-FP16:       // %bb.0:
2941; CHECK-SD-FP16-NEXT:    movi v1.8h, #1
2942; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
2943; CHECK-SD-FP16-NEXT:    umin v0.8h, v0.8h, v1.8h
2944; CHECK-SD-FP16-NEXT:    xtn v0.8b, v0.8h
2945; CHECK-SD-FP16-NEXT:    ret
2946;
2947; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i1:
2948; CHECK-GI-CVT:       // %bb.0:
2949; CHECK-GI-CVT-NEXT:    fcvtl v2.4s, v0.4h
2950; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
2951; CHECK-GI-CVT-NEXT:    movi v1.4s, #1
2952; CHECK-GI-CVT-NEXT:    fcvtzu v2.4s, v2.4s
2953; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2954; CHECK-GI-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
2955; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2956; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
2957; CHECK-GI-CVT-NEXT:    xtn v0.8b, v0.8h
2958; CHECK-GI-CVT-NEXT:    ret
2959;
2960; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i1:
2961; CHECK-GI-FP16:       // %bb.0:
2962; CHECK-GI-FP16-NEXT:    movi v1.8h, #1
2963; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
2964; CHECK-GI-FP16-NEXT:    umin v0.8h, v0.8h, v1.8h
2965; CHECK-GI-FP16-NEXT:    xtn v0.8b, v0.8h
2966; CHECK-GI-FP16-NEXT:    ret
2967    %x = call <8 x i1> @llvm.fptoui.sat.v8f16.v8i1(<8 x half> %f)
2968    ret <8 x i1> %x
2969}
2970
2971define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
2972; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i8:
2973; CHECK-SD-CVT:       // %bb.0:
2974; CHECK-SD-CVT-NEXT:    fcvtl2 v2.4s, v0.8h
2975; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
2976; CHECK-SD-CVT-NEXT:    movi v1.2d, #0x0000ff000000ff
2977; CHECK-SD-CVT-NEXT:    fcvtzu v2.4s, v2.4s
2978; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2979; CHECK-SD-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
2980; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
2981; CHECK-SD-CVT-NEXT:    uzp1 v0.8h, v0.8h, v2.8h
2982; CHECK-SD-CVT-NEXT:    xtn v0.8b, v0.8h
2983; CHECK-SD-CVT-NEXT:    ret
2984;
2985; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i8:
2986; CHECK-SD-FP16:       // %bb.0:
2987; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
2988; CHECK-SD-FP16-NEXT:    uqxtn v0.8b, v0.8h
2989; CHECK-SD-FP16-NEXT:    ret
2990;
2991; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i8:
2992; CHECK-GI-CVT:       // %bb.0:
2993; CHECK-GI-CVT-NEXT:    fcvtl v2.4s, v0.4h
2994; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
2995; CHECK-GI-CVT-NEXT:    movi v1.2d, #0x0000ff000000ff
2996; CHECK-GI-CVT-NEXT:    fcvtzu v2.4s, v2.4s
2997; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
2998; CHECK-GI-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
2999; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
3000; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
3001; CHECK-GI-CVT-NEXT:    xtn v0.8b, v0.8h
3002; CHECK-GI-CVT-NEXT:    ret
3003;
3004; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i8:
3005; CHECK-GI-FP16:       // %bb.0:
3006; CHECK-GI-FP16-NEXT:    movi v1.2d, #0xff00ff00ff00ff
3007; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
3008; CHECK-GI-FP16-NEXT:    umin v0.8h, v0.8h, v1.8h
3009; CHECK-GI-FP16-NEXT:    xtn v0.8b, v0.8h
3010; CHECK-GI-FP16-NEXT:    ret
3011    %x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
3012    ret <8 x i8> %x
3013}
3014
3015define <8 x i13> @test_unsigned_v8f16_v8i13(<8 x half> %f) {
3016; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i13:
3017; CHECK-SD-CVT:       // %bb.0:
3018; CHECK-SD-CVT-NEXT:    fcvtl2 v2.4s, v0.8h
3019; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
3020; CHECK-SD-CVT-NEXT:    movi v1.4s, #31, msl #8
3021; CHECK-SD-CVT-NEXT:    fcvtzu v2.4s, v2.4s
3022; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
3023; CHECK-SD-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
3024; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
3025; CHECK-SD-CVT-NEXT:    uzp1 v0.8h, v0.8h, v2.8h
3026; CHECK-SD-CVT-NEXT:    ret
3027;
3028; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i13:
3029; CHECK-SD-FP16:       // %bb.0:
3030; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
3031; CHECK-SD-FP16-NEXT:    mvni v1.8h, #224, lsl #8
3032; CHECK-SD-FP16-NEXT:    umin v0.8h, v0.8h, v1.8h
3033; CHECK-SD-FP16-NEXT:    ret
3034;
3035; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i13:
3036; CHECK-GI-CVT:       // %bb.0:
3037; CHECK-GI-CVT-NEXT:    fcvtl v2.4s, v0.4h
3038; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
3039; CHECK-GI-CVT-NEXT:    movi v1.4s, #31, msl #8
3040; CHECK-GI-CVT-NEXT:    fcvtzu v2.4s, v2.4s
3041; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
3042; CHECK-GI-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
3043; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
3044; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
3045; CHECK-GI-CVT-NEXT:    ret
3046;
3047; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i13:
3048; CHECK-GI-FP16:       // %bb.0:
3049; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
3050; CHECK-GI-FP16-NEXT:    mvni v1.8h, #224, lsl #8
3051; CHECK-GI-FP16-NEXT:    umin v0.8h, v0.8h, v1.8h
3052; CHECK-GI-FP16-NEXT:    ret
3053    %x = call <8 x i13> @llvm.fptoui.sat.v8f16.v8i13(<8 x half> %f)
3054    ret <8 x i13> %x
3055}
3056
3057define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
3058; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i16:
3059; CHECK-SD-CVT:       // %bb.0:
3060; CHECK-SD-CVT-NEXT:    fcvtl v1.4s, v0.4h
3061; CHECK-SD-CVT-NEXT:    fcvtl2 v2.4s, v0.8h
3062; CHECK-SD-CVT-NEXT:    fcvtzu v1.4s, v1.4s
3063; CHECK-SD-CVT-NEXT:    uqxtn v0.4h, v1.4s
3064; CHECK-SD-CVT-NEXT:    fcvtzu v1.4s, v2.4s
3065; CHECK-SD-CVT-NEXT:    uqxtn2 v0.8h, v1.4s
3066; CHECK-SD-CVT-NEXT:    ret
3067;
3068; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i16:
3069; CHECK-SD-FP16:       // %bb.0:
3070; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
3071; CHECK-SD-FP16-NEXT:    ret
3072;
3073; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i16:
3074; CHECK-GI-CVT:       // %bb.0:
3075; CHECK-GI-CVT-NEXT:    fcvtl v2.4s, v0.4h
3076; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
3077; CHECK-GI-CVT-NEXT:    movi v1.2d, #0x00ffff0000ffff
3078; CHECK-GI-CVT-NEXT:    fcvtzu v2.4s, v2.4s
3079; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
3080; CHECK-GI-CVT-NEXT:    umin v2.4s, v2.4s, v1.4s
3081; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v1.4s
3082; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v2.8h, v0.8h
3083; CHECK-GI-CVT-NEXT:    ret
3084;
3085; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i16:
3086; CHECK-GI-FP16:       // %bb.0:
3087; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
3088; CHECK-GI-FP16-NEXT:    ret
3089    %x = call <8 x i16> @llvm.fptoui.sat.v8f16.v8i16(<8 x half> %f)
3090    ret <8 x i16> %x
3091}
3092
3093define <8 x i19> @test_unsigned_v8f16_v8i19(<8 x half> %f) {
3094; CHECK-LABEL: test_unsigned_v8f16_v8i19:
3095; CHECK:       // %bb.0:
3096; CHECK-NEXT:    fcvtl v2.4s, v0.4h
3097; CHECK-NEXT:    fcvtl2 v0.4s, v0.8h
3098; CHECK-NEXT:    movi v1.4s, #7, msl #16
3099; CHECK-NEXT:    fcvtzu v2.4s, v2.4s
3100; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
3101; CHECK-NEXT:    umin v2.4s, v2.4s, v1.4s
3102; CHECK-NEXT:    umin v0.4s, v0.4s, v1.4s
3103; CHECK-NEXT:    mov w1, v2.s[1]
3104; CHECK-NEXT:    mov w2, v2.s[2]
3105; CHECK-NEXT:    mov w3, v2.s[3]
3106; CHECK-NEXT:    mov w5, v0.s[1]
3107; CHECK-NEXT:    mov w6, v0.s[2]
3108; CHECK-NEXT:    mov w7, v0.s[3]
3109; CHECK-NEXT:    fmov w4, s0
3110; CHECK-NEXT:    fmov w0, s2
3111; CHECK-NEXT:    ret
3112    %x = call <8 x i19> @llvm.fptoui.sat.v8f16.v8i19(<8 x half> %f)
3113    ret <8 x i19> %x
3114}
3115
3116define <8 x i32> @test_unsigned_v8f16_v8i32_duplicate(<8 x half> %f) {
3117; CHECK-SD-LABEL: test_unsigned_v8f16_v8i32_duplicate:
3118; CHECK-SD:       // %bb.0:
3119; CHECK-SD-NEXT:    fcvtl2 v1.4s, v0.8h
3120; CHECK-SD-NEXT:    fcvtl v0.4s, v0.4h
3121; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
3122; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
3123; CHECK-SD-NEXT:    ret
3124;
3125; CHECK-GI-LABEL: test_unsigned_v8f16_v8i32_duplicate:
3126; CHECK-GI:       // %bb.0:
3127; CHECK-GI-NEXT:    fcvtl v1.4s, v0.4h
3128; CHECK-GI-NEXT:    fcvtl2 v2.4s, v0.8h
3129; CHECK-GI-NEXT:    fcvtzu v0.4s, v1.4s
3130; CHECK-GI-NEXT:    fcvtzu v1.4s, v2.4s
3131; CHECK-GI-NEXT:    ret
3132    %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
3133    ret <8 x i32> %x
3134}
3135
3136define <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
3137; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i50:
3138; CHECK-SD-CVT:       // %bb.0:
3139; CHECK-SD-CVT-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3140; CHECK-SD-CVT-NEXT:    mov h5, v0.h[1]
3141; CHECK-SD-CVT-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
3142; CHECK-SD-CVT-NEXT:    mov h6, v0.h[2]
3143; CHECK-SD-CVT-NEXT:    mov h7, v0.h[3]
3144; CHECK-SD-CVT-NEXT:    fcvt s0, h0
3145; CHECK-SD-CVT-NEXT:    mov h2, v1.h[1]
3146; CHECK-SD-CVT-NEXT:    mov h3, v1.h[2]
3147; CHECK-SD-CVT-NEXT:    mov h4, v1.h[3]
3148; CHECK-SD-CVT-NEXT:    fcvt s1, h1
3149; CHECK-SD-CVT-NEXT:    fcvtzu x13, s0
3150; CHECK-SD-CVT-NEXT:    fcvt s2, h2
3151; CHECK-SD-CVT-NEXT:    fcvt s3, h3
3152; CHECK-SD-CVT-NEXT:    fcvt s4, h4
3153; CHECK-SD-CVT-NEXT:    fcvtzu x9, s1
3154; CHECK-SD-CVT-NEXT:    fcvt s1, h5
3155; CHECK-SD-CVT-NEXT:    fcvtzu x10, s2
3156; CHECK-SD-CVT-NEXT:    fcvtzu x11, s3
3157; CHECK-SD-CVT-NEXT:    fcvt s2, h6
3158; CHECK-SD-CVT-NEXT:    fcvtzu x12, s4
3159; CHECK-SD-CVT-NEXT:    fcvt s3, h7
3160; CHECK-SD-CVT-NEXT:    cmp x9, x8
3161; CHECK-SD-CVT-NEXT:    fcvtzu x14, s1
3162; CHECK-SD-CVT-NEXT:    csel x4, x9, x8, lo
3163; CHECK-SD-CVT-NEXT:    cmp x10, x8
3164; CHECK-SD-CVT-NEXT:    fcvtzu x9, s2
3165; CHECK-SD-CVT-NEXT:    csel x5, x10, x8, lo
3166; CHECK-SD-CVT-NEXT:    cmp x11, x8
3167; CHECK-SD-CVT-NEXT:    fcvtzu x10, s3
3168; CHECK-SD-CVT-NEXT:    csel x6, x11, x8, lo
3169; CHECK-SD-CVT-NEXT:    cmp x12, x8
3170; CHECK-SD-CVT-NEXT:    csel x7, x12, x8, lo
3171; CHECK-SD-CVT-NEXT:    cmp x13, x8
3172; CHECK-SD-CVT-NEXT:    csel x0, x13, x8, lo
3173; CHECK-SD-CVT-NEXT:    cmp x14, x8
3174; CHECK-SD-CVT-NEXT:    csel x1, x14, x8, lo
3175; CHECK-SD-CVT-NEXT:    cmp x9, x8
3176; CHECK-SD-CVT-NEXT:    csel x2, x9, x8, lo
3177; CHECK-SD-CVT-NEXT:    cmp x10, x8
3178; CHECK-SD-CVT-NEXT:    csel x3, x10, x8, lo
3179; CHECK-SD-CVT-NEXT:    ret
3180;
3181; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i50:
3182; CHECK-SD-FP16:       // %bb.0:
3183; CHECK-SD-FP16-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3184; CHECK-SD-FP16-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
3185; CHECK-SD-FP16-NEXT:    fcvtzu x13, h0
3186; CHECK-SD-FP16-NEXT:    mov h2, v1.h[1]
3187; CHECK-SD-FP16-NEXT:    mov h3, v1.h[2]
3188; CHECK-SD-FP16-NEXT:    mov h4, v1.h[3]
3189; CHECK-SD-FP16-NEXT:    fcvtzu x9, h1
3190; CHECK-SD-FP16-NEXT:    mov h1, v0.h[1]
3191; CHECK-SD-FP16-NEXT:    fcvtzu x10, h2
3192; CHECK-SD-FP16-NEXT:    fcvtzu x11, h3
3193; CHECK-SD-FP16-NEXT:    mov h2, v0.h[2]
3194; CHECK-SD-FP16-NEXT:    fcvtzu x12, h4
3195; CHECK-SD-FP16-NEXT:    mov h3, v0.h[3]
3196; CHECK-SD-FP16-NEXT:    cmp x9, x8
3197; CHECK-SD-FP16-NEXT:    fcvtzu x14, h1
3198; CHECK-SD-FP16-NEXT:    csel x4, x9, x8, lo
3199; CHECK-SD-FP16-NEXT:    cmp x10, x8
3200; CHECK-SD-FP16-NEXT:    fcvtzu x9, h2
3201; CHECK-SD-FP16-NEXT:    csel x5, x10, x8, lo
3202; CHECK-SD-FP16-NEXT:    cmp x11, x8
3203; CHECK-SD-FP16-NEXT:    fcvtzu x10, h3
3204; CHECK-SD-FP16-NEXT:    csel x6, x11, x8, lo
3205; CHECK-SD-FP16-NEXT:    cmp x12, x8
3206; CHECK-SD-FP16-NEXT:    csel x7, x12, x8, lo
3207; CHECK-SD-FP16-NEXT:    cmp x13, x8
3208; CHECK-SD-FP16-NEXT:    csel x0, x13, x8, lo
3209; CHECK-SD-FP16-NEXT:    cmp x14, x8
3210; CHECK-SD-FP16-NEXT:    csel x1, x14, x8, lo
3211; CHECK-SD-FP16-NEXT:    cmp x9, x8
3212; CHECK-SD-FP16-NEXT:    csel x2, x9, x8, lo
3213; CHECK-SD-FP16-NEXT:    cmp x10, x8
3214; CHECK-SD-FP16-NEXT:    csel x3, x10, x8, lo
3215; CHECK-SD-FP16-NEXT:    ret
3216;
3217; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i50:
3218; CHECK-GI-CVT:       // %bb.0:
3219; CHECK-GI-CVT-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3220; CHECK-GI-CVT-NEXT:    mov h5, v0.h[1]
3221; CHECK-GI-CVT-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
3222; CHECK-GI-CVT-NEXT:    mov h6, v0.h[2]
3223; CHECK-GI-CVT-NEXT:    mov h7, v0.h[3]
3224; CHECK-GI-CVT-NEXT:    fcvt s0, h0
3225; CHECK-GI-CVT-NEXT:    mov h2, v1.h[1]
3226; CHECK-GI-CVT-NEXT:    mov h3, v1.h[2]
3227; CHECK-GI-CVT-NEXT:    mov h4, v1.h[3]
3228; CHECK-GI-CVT-NEXT:    fcvt s1, h1
3229; CHECK-GI-CVT-NEXT:    fcvtzu x13, s0
3230; CHECK-GI-CVT-NEXT:    fcvt s2, h2
3231; CHECK-GI-CVT-NEXT:    fcvt s3, h3
3232; CHECK-GI-CVT-NEXT:    fcvt s4, h4
3233; CHECK-GI-CVT-NEXT:    fcvtzu x9, s1
3234; CHECK-GI-CVT-NEXT:    fcvt s1, h5
3235; CHECK-GI-CVT-NEXT:    fcvtzu x10, s2
3236; CHECK-GI-CVT-NEXT:    fcvtzu x11, s3
3237; CHECK-GI-CVT-NEXT:    fcvt s2, h6
3238; CHECK-GI-CVT-NEXT:    fcvtzu x12, s4
3239; CHECK-GI-CVT-NEXT:    fcvt s3, h7
3240; CHECK-GI-CVT-NEXT:    cmp x9, x8
3241; CHECK-GI-CVT-NEXT:    fcvtzu x14, s1
3242; CHECK-GI-CVT-NEXT:    csel x4, x9, x8, lo
3243; CHECK-GI-CVT-NEXT:    cmp x10, x8
3244; CHECK-GI-CVT-NEXT:    fcvtzu x9, s2
3245; CHECK-GI-CVT-NEXT:    csel x5, x10, x8, lo
3246; CHECK-GI-CVT-NEXT:    cmp x11, x8
3247; CHECK-GI-CVT-NEXT:    fcvtzu x10, s3
3248; CHECK-GI-CVT-NEXT:    csel x6, x11, x8, lo
3249; CHECK-GI-CVT-NEXT:    cmp x12, x8
3250; CHECK-GI-CVT-NEXT:    csel x7, x12, x8, lo
3251; CHECK-GI-CVT-NEXT:    cmp x13, x8
3252; CHECK-GI-CVT-NEXT:    csel x0, x13, x8, lo
3253; CHECK-GI-CVT-NEXT:    cmp x14, x8
3254; CHECK-GI-CVT-NEXT:    csel x1, x14, x8, lo
3255; CHECK-GI-CVT-NEXT:    cmp x9, x8
3256; CHECK-GI-CVT-NEXT:    csel x2, x9, x8, lo
3257; CHECK-GI-CVT-NEXT:    cmp x10, x8
3258; CHECK-GI-CVT-NEXT:    csel x3, x10, x8, lo
3259; CHECK-GI-CVT-NEXT:    ret
3260;
3261; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i50:
3262; CHECK-GI-FP16:       // %bb.0:
3263; CHECK-GI-FP16-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3264; CHECK-GI-FP16-NEXT:    mov x8, #1125899906842623 // =0x3ffffffffffff
3265; CHECK-GI-FP16-NEXT:    fcvtzu x13, h0
3266; CHECK-GI-FP16-NEXT:    mov h2, v1.h[1]
3267; CHECK-GI-FP16-NEXT:    mov h3, v1.h[2]
3268; CHECK-GI-FP16-NEXT:    mov h4, v1.h[3]
3269; CHECK-GI-FP16-NEXT:    fcvtzu x9, h1
3270; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
3271; CHECK-GI-FP16-NEXT:    fcvtzu x10, h2
3272; CHECK-GI-FP16-NEXT:    fcvtzu x11, h3
3273; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
3274; CHECK-GI-FP16-NEXT:    fcvtzu x12, h4
3275; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
3276; CHECK-GI-FP16-NEXT:    cmp x9, x8
3277; CHECK-GI-FP16-NEXT:    fcvtzu x14, h1
3278; CHECK-GI-FP16-NEXT:    csel x4, x9, x8, lo
3279; CHECK-GI-FP16-NEXT:    cmp x10, x8
3280; CHECK-GI-FP16-NEXT:    fcvtzu x9, h2
3281; CHECK-GI-FP16-NEXT:    csel x5, x10, x8, lo
3282; CHECK-GI-FP16-NEXT:    cmp x11, x8
3283; CHECK-GI-FP16-NEXT:    fcvtzu x10, h3
3284; CHECK-GI-FP16-NEXT:    csel x6, x11, x8, lo
3285; CHECK-GI-FP16-NEXT:    cmp x12, x8
3286; CHECK-GI-FP16-NEXT:    csel x7, x12, x8, lo
3287; CHECK-GI-FP16-NEXT:    cmp x13, x8
3288; CHECK-GI-FP16-NEXT:    csel x0, x13, x8, lo
3289; CHECK-GI-FP16-NEXT:    cmp x14, x8
3290; CHECK-GI-FP16-NEXT:    csel x1, x14, x8, lo
3291; CHECK-GI-FP16-NEXT:    cmp x9, x8
3292; CHECK-GI-FP16-NEXT:    csel x2, x9, x8, lo
3293; CHECK-GI-FP16-NEXT:    cmp x10, x8
3294; CHECK-GI-FP16-NEXT:    csel x3, x10, x8, lo
3295; CHECK-GI-FP16-NEXT:    ret
3296    %x = call <8 x i50> @llvm.fptoui.sat.v8f16.v8i50(<8 x half> %f)
3297    ret <8 x i50> %x
3298}
3299
3300define <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
3301; CHECK-SD-CVT-LABEL: test_unsigned_v8f16_v8i64:
3302; CHECK-SD-CVT:       // %bb.0:
3303; CHECK-SD-CVT-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3304; CHECK-SD-CVT-NEXT:    mov h4, v0.h[2]
3305; CHECK-SD-CVT-NEXT:    mov h3, v0.h[1]
3306; CHECK-SD-CVT-NEXT:    mov h7, v0.h[3]
3307; CHECK-SD-CVT-NEXT:    fcvt s0, h0
3308; CHECK-SD-CVT-NEXT:    mov h2, v1.h[2]
3309; CHECK-SD-CVT-NEXT:    mov h5, v1.h[1]
3310; CHECK-SD-CVT-NEXT:    mov h6, v1.h[3]
3311; CHECK-SD-CVT-NEXT:    fcvt s1, h1
3312; CHECK-SD-CVT-NEXT:    fcvt s4, h4
3313; CHECK-SD-CVT-NEXT:    fcvt s3, h3
3314; CHECK-SD-CVT-NEXT:    fcvt s7, h7
3315; CHECK-SD-CVT-NEXT:    fcvtzu x9, s0
3316; CHECK-SD-CVT-NEXT:    fcvt s2, h2
3317; CHECK-SD-CVT-NEXT:    fcvt s5, h5
3318; CHECK-SD-CVT-NEXT:    fcvt s6, h6
3319; CHECK-SD-CVT-NEXT:    fcvtzu x8, s1
3320; CHECK-SD-CVT-NEXT:    fcvtzu x12, s4
3321; CHECK-SD-CVT-NEXT:    fcvtzu x11, s3
3322; CHECK-SD-CVT-NEXT:    fcvtzu x15, s7
3323; CHECK-SD-CVT-NEXT:    fmov d0, x9
3324; CHECK-SD-CVT-NEXT:    fcvtzu x10, s2
3325; CHECK-SD-CVT-NEXT:    fcvtzu x13, s5
3326; CHECK-SD-CVT-NEXT:    fcvtzu x14, s6
3327; CHECK-SD-CVT-NEXT:    fmov d2, x8
3328; CHECK-SD-CVT-NEXT:    fmov d1, x12
3329; CHECK-SD-CVT-NEXT:    mov v0.d[1], x11
3330; CHECK-SD-CVT-NEXT:    fmov d3, x10
3331; CHECK-SD-CVT-NEXT:    mov v2.d[1], x13
3332; CHECK-SD-CVT-NEXT:    mov v1.d[1], x15
3333; CHECK-SD-CVT-NEXT:    mov v3.d[1], x14
3334; CHECK-SD-CVT-NEXT:    ret
3335;
3336; CHECK-SD-FP16-LABEL: test_unsigned_v8f16_v8i64:
3337; CHECK-SD-FP16:       // %bb.0:
3338; CHECK-SD-FP16-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
3339; CHECK-SD-FP16-NEXT:    mov h4, v0.h[2]
3340; CHECK-SD-FP16-NEXT:    mov h3, v0.h[1]
3341; CHECK-SD-FP16-NEXT:    mov h7, v0.h[3]
3342; CHECK-SD-FP16-NEXT:    fcvtzu x9, h0
3343; CHECK-SD-FP16-NEXT:    mov h2, v1.h[2]
3344; CHECK-SD-FP16-NEXT:    mov h5, v1.h[1]
3345; CHECK-SD-FP16-NEXT:    mov h6, v1.h[3]
3346; CHECK-SD-FP16-NEXT:    fcvtzu x8, h1
3347; CHECK-SD-FP16-NEXT:    fcvtzu x12, h4
3348; CHECK-SD-FP16-NEXT:    fcvtzu x11, h3
3349; CHECK-SD-FP16-NEXT:    fcvtzu x15, h7
3350; CHECK-SD-FP16-NEXT:    fmov d0, x9
3351; CHECK-SD-FP16-NEXT:    fcvtzu x10, h2
3352; CHECK-SD-FP16-NEXT:    fcvtzu x13, h5
3353; CHECK-SD-FP16-NEXT:    fcvtzu x14, h6
3354; CHECK-SD-FP16-NEXT:    fmov d2, x8
3355; CHECK-SD-FP16-NEXT:    fmov d1, x12
3356; CHECK-SD-FP16-NEXT:    mov v0.d[1], x11
3357; CHECK-SD-FP16-NEXT:    fmov d3, x10
3358; CHECK-SD-FP16-NEXT:    mov v2.d[1], x13
3359; CHECK-SD-FP16-NEXT:    mov v1.d[1], x15
3360; CHECK-SD-FP16-NEXT:    mov v3.d[1], x14
3361; CHECK-SD-FP16-NEXT:    ret
3362;
3363; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i64:
3364; CHECK-GI-CVT:       // %bb.0:
3365; CHECK-GI-CVT-NEXT:    fcvtl v1.4s, v0.4h
3366; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
3367; CHECK-GI-CVT-NEXT:    fcvtl v2.2d, v1.2s
3368; CHECK-GI-CVT-NEXT:    fcvtl2 v1.2d, v1.4s
3369; CHECK-GI-CVT-NEXT:    fcvtl v3.2d, v0.2s
3370; CHECK-GI-CVT-NEXT:    fcvtl2 v4.2d, v0.4s
3371; CHECK-GI-CVT-NEXT:    fcvtzu v0.2d, v2.2d
3372; CHECK-GI-CVT-NEXT:    fcvtzu v1.2d, v1.2d
3373; CHECK-GI-CVT-NEXT:    fcvtzu v2.2d, v3.2d
3374; CHECK-GI-CVT-NEXT:    fcvtzu v3.2d, v4.2d
3375; CHECK-GI-CVT-NEXT:    ret
3376;
3377; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i64:
3378; CHECK-GI-FP16:       // %bb.0:
3379; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
3380; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
3381; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
3382; CHECK-GI-FP16-NEXT:    mov h4, v0.h[4]
3383; CHECK-GI-FP16-NEXT:    mov h5, v0.h[5]
3384; CHECK-GI-FP16-NEXT:    mov h6, v0.h[6]
3385; CHECK-GI-FP16-NEXT:    mov h7, v0.h[7]
3386; CHECK-GI-FP16-NEXT:    fcvt d0, h0
3387; CHECK-GI-FP16-NEXT:    fcvt d1, h1
3388; CHECK-GI-FP16-NEXT:    fcvt d2, h2
3389; CHECK-GI-FP16-NEXT:    fcvt d3, h3
3390; CHECK-GI-FP16-NEXT:    fcvt d4, h4
3391; CHECK-GI-FP16-NEXT:    fcvt d5, h5
3392; CHECK-GI-FP16-NEXT:    fcvt d6, h6
3393; CHECK-GI-FP16-NEXT:    fcvt d7, h7
3394; CHECK-GI-FP16-NEXT:    mov v0.d[1], v1.d[0]
3395; CHECK-GI-FP16-NEXT:    mov v2.d[1], v3.d[0]
3396; CHECK-GI-FP16-NEXT:    mov v4.d[1], v5.d[0]
3397; CHECK-GI-FP16-NEXT:    mov v6.d[1], v7.d[0]
3398; CHECK-GI-FP16-NEXT:    fcvtzu v0.2d, v0.2d
3399; CHECK-GI-FP16-NEXT:    fcvtzu v1.2d, v2.2d
3400; CHECK-GI-FP16-NEXT:    fcvtzu v2.2d, v4.2d
3401; CHECK-GI-FP16-NEXT:    fcvtzu v3.2d, v6.2d
3402; CHECK-GI-FP16-NEXT:    ret
3403    %x = call <8 x i64> @llvm.fptoui.sat.v8f16.v8i64(<8 x half> %f)
3404    ret <8 x i64> %x
3405}
3406
3407define <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) {
3408; CHECK-SD-LABEL: test_unsigned_v8f16_v8i100:
3409; CHECK-SD:       // %bb.0:
3410; CHECK-SD-NEXT:    sub sp, sp, #176
3411; CHECK-SD-NEXT:    stp d9, d8, [sp, #64] // 16-byte Folded Spill
3412; CHECK-SD-NEXT:    stp x29, x30, [sp, #80] // 16-byte Folded Spill
3413; CHECK-SD-NEXT:    stp x28, x27, [sp, #96] // 16-byte Folded Spill
3414; CHECK-SD-NEXT:    stp x26, x25, [sp, #112] // 16-byte Folded Spill
3415; CHECK-SD-NEXT:    stp x24, x23, [sp, #128] // 16-byte Folded Spill
3416; CHECK-SD-NEXT:    stp x22, x21, [sp, #144] // 16-byte Folded Spill
3417; CHECK-SD-NEXT:    stp x20, x19, [sp, #160] // 16-byte Folded Spill
3418; CHECK-SD-NEXT:    .cfi_def_cfa_offset 176
3419; CHECK-SD-NEXT:    .cfi_offset w19, -8
3420; CHECK-SD-NEXT:    .cfi_offset w20, -16
3421; CHECK-SD-NEXT:    .cfi_offset w21, -24
3422; CHECK-SD-NEXT:    .cfi_offset w22, -32
3423; CHECK-SD-NEXT:    .cfi_offset w23, -40
3424; CHECK-SD-NEXT:    .cfi_offset w24, -48
3425; CHECK-SD-NEXT:    .cfi_offset w25, -56
3426; CHECK-SD-NEXT:    .cfi_offset w26, -64
3427; CHECK-SD-NEXT:    .cfi_offset w27, -72
3428; CHECK-SD-NEXT:    .cfi_offset w28, -80
3429; CHECK-SD-NEXT:    .cfi_offset w30, -88
3430; CHECK-SD-NEXT:    .cfi_offset w29, -96
3431; CHECK-SD-NEXT:    .cfi_offset b8, -104
3432; CHECK-SD-NEXT:    .cfi_offset b9, -112
3433; CHECK-SD-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
3434; CHECK-SD-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
3435; CHECK-SD-NEXT:    mov x19, x8
3436; CHECK-SD-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
3437; CHECK-SD-NEXT:    mov h0, v0.h[1]
3438; CHECK-SD-NEXT:    fcvt s8, h0
3439; CHECK-SD-NEXT:    fmov s0, s8
3440; CHECK-SD-NEXT:    bl __fixunssfti
3441; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3442; CHECK-SD-NEXT:    mov w8, #1904214015 // =0x717fffff
3443; CHECK-SD-NEXT:    fcmp s8, #0.0
3444; CHECK-SD-NEXT:    fmov s9, w8
3445; CHECK-SD-NEXT:    mov x23, #68719476735 // =0xfffffffff
3446; CHECK-SD-NEXT:    mov h0, v0.h[3]
3447; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3448; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3449; CHECK-SD-NEXT:    fcmp s8, s9
3450; CHECK-SD-NEXT:    fcvt s8, h0
3451; CHECK-SD-NEXT:    csel x10, x23, x8, gt
3452; CHECK-SD-NEXT:    csinv x8, x9, xzr, le
3453; CHECK-SD-NEXT:    stp x8, x10, [sp, #16] // 16-byte Folded Spill
3454; CHECK-SD-NEXT:    fmov s0, s8
3455; CHECK-SD-NEXT:    bl __fixunssfti
3456; CHECK-SD-NEXT:    fcmp s8, #0.0
3457; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3458; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3459; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3460; CHECK-SD-NEXT:    fcmp s8, s9
3461; CHECK-SD-NEXT:    fcvt s8, h0
3462; CHECK-SD-NEXT:    csel x9, x23, x9, gt
3463; CHECK-SD-NEXT:    csinv x8, x8, xzr, le
3464; CHECK-SD-NEXT:    stp x8, x9, [sp] // 16-byte Folded Spill
3465; CHECK-SD-NEXT:    fmov s0, s8
3466; CHECK-SD-NEXT:    bl __fixunssfti
3467; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3468; CHECK-SD-NEXT:    fcmp s8, #0.0
3469; CHECK-SD-NEXT:    mov h0, v0.h[2]
3470; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3471; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3472; CHECK-SD-NEXT:    fcmp s8, s9
3473; CHECK-SD-NEXT:    fcvt s8, h0
3474; CHECK-SD-NEXT:    csinv x8, x8, xzr, le
3475; CHECK-SD-NEXT:    csel x25, x23, x9, gt
3476; CHECK-SD-NEXT:    str x8, [sp, #32] // 8-byte Folded Spill
3477; CHECK-SD-NEXT:    fmov s0, s8
3478; CHECK-SD-NEXT:    bl __fixunssfti
3479; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3480; CHECK-SD-NEXT:    fcmp s8, #0.0
3481; CHECK-SD-NEXT:    mov h0, v0.h[1]
3482; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3483; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3484; CHECK-SD-NEXT:    fcmp s8, s9
3485; CHECK-SD-NEXT:    fcvt s8, h0
3486; CHECK-SD-NEXT:    csel x26, x23, x9, gt
3487; CHECK-SD-NEXT:    csinv x28, x8, xzr, le
3488; CHECK-SD-NEXT:    fmov s0, s8
3489; CHECK-SD-NEXT:    bl __fixunssfti
3490; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3491; CHECK-SD-NEXT:    fcmp s8, #0.0
3492; CHECK-SD-NEXT:    mov h0, v0.h[3]
3493; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3494; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3495; CHECK-SD-NEXT:    fcmp s8, s9
3496; CHECK-SD-NEXT:    fcvt s8, h0
3497; CHECK-SD-NEXT:    csel x29, x23, x9, gt
3498; CHECK-SD-NEXT:    csinv x20, x8, xzr, le
3499; CHECK-SD-NEXT:    fmov s0, s8
3500; CHECK-SD-NEXT:    bl __fixunssfti
3501; CHECK-SD-NEXT:    fcmp s8, #0.0
3502; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3503; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3504; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3505; CHECK-SD-NEXT:    fcmp s8, s9
3506; CHECK-SD-NEXT:    fcvt s8, h0
3507; CHECK-SD-NEXT:    csel x21, x23, x9, gt
3508; CHECK-SD-NEXT:    csinv x27, x8, xzr, le
3509; CHECK-SD-NEXT:    fmov s0, s8
3510; CHECK-SD-NEXT:    bl __fixunssfti
3511; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3512; CHECK-SD-NEXT:    fcmp s8, #0.0
3513; CHECK-SD-NEXT:    mov h0, v0.h[2]
3514; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3515; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3516; CHECK-SD-NEXT:    fcmp s8, s9
3517; CHECK-SD-NEXT:    fcvt s8, h0
3518; CHECK-SD-NEXT:    csel x22, x23, x9, gt
3519; CHECK-SD-NEXT:    csinv x24, x8, xzr, le
3520; CHECK-SD-NEXT:    fmov s0, s8
3521; CHECK-SD-NEXT:    bl __fixunssfti
3522; CHECK-SD-NEXT:    extr x8, x21, x27, #28
3523; CHECK-SD-NEXT:    extr x9, x29, x20, #28
3524; CHECK-SD-NEXT:    stur x28, [x19, #75]
3525; CHECK-SD-NEXT:    fcmp s8, #0.0
3526; CHECK-SD-NEXT:    bfi x22, x20, #36, #28
3527; CHECK-SD-NEXT:    lsr x11, x29, #28
3528; CHECK-SD-NEXT:    stur x8, [x19, #41]
3529; CHECK-SD-NEXT:    str x9, [x19, #16]
3530; CHECK-SD-NEXT:    ldr x10, [sp, #32] // 8-byte Folded Reload
3531; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3532; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3533; CHECK-SD-NEXT:    fcmp s8, s9
3534; CHECK-SD-NEXT:    stp x24, x22, [x19]
3535; CHECK-SD-NEXT:    stur x10, [x19, #50]
3536; CHECK-SD-NEXT:    lsr x10, x21, #28
3537; CHECK-SD-NEXT:    strb w11, [x19, #24]
3538; CHECK-SD-NEXT:    strb w10, [x19, #49]
3539; CHECK-SD-NEXT:    csel x9, x23, x9, gt
3540; CHECK-SD-NEXT:    csinv x8, x8, xzr, le
3541; CHECK-SD-NEXT:    ldp x12, x11, [sp] // 16-byte Folded Reload
3542; CHECK-SD-NEXT:    bfi x9, x27, #36, #28
3543; CHECK-SD-NEXT:    stur x8, [x19, #25]
3544; CHECK-SD-NEXT:    stur x9, [x19, #33]
3545; CHECK-SD-NEXT:    extr x10, x11, x12, #28
3546; CHECK-SD-NEXT:    bfi x26, x12, #36, #28
3547; CHECK-SD-NEXT:    stur x10, [x19, #91]
3548; CHECK-SD-NEXT:    ldp x10, x9, [sp, #16] // 16-byte Folded Reload
3549; CHECK-SD-NEXT:    stur x26, [x19, #83]
3550; CHECK-SD-NEXT:    extr x8, x9, x10, #28
3551; CHECK-SD-NEXT:    bfi x25, x10, #36, #28
3552; CHECK-SD-NEXT:    lsr x9, x9, #28
3553; CHECK-SD-NEXT:    stur x8, [x19, #66]
3554; CHECK-SD-NEXT:    lsr x8, x11, #28
3555; CHECK-SD-NEXT:    stur x25, [x19, #58]
3556; CHECK-SD-NEXT:    strb w8, [x19, #99]
3557; CHECK-SD-NEXT:    strb w9, [x19, #74]
3558; CHECK-SD-NEXT:    ldp x20, x19, [sp, #160] // 16-byte Folded Reload
3559; CHECK-SD-NEXT:    ldp x22, x21, [sp, #144] // 16-byte Folded Reload
3560; CHECK-SD-NEXT:    ldp x24, x23, [sp, #128] // 16-byte Folded Reload
3561; CHECK-SD-NEXT:    ldp x26, x25, [sp, #112] // 16-byte Folded Reload
3562; CHECK-SD-NEXT:    ldp x28, x27, [sp, #96] // 16-byte Folded Reload
3563; CHECK-SD-NEXT:    ldp x29, x30, [sp, #80] // 16-byte Folded Reload
3564; CHECK-SD-NEXT:    ldp d9, d8, [sp, #64] // 16-byte Folded Reload
3565; CHECK-SD-NEXT:    add sp, sp, #176
3566; CHECK-SD-NEXT:    ret
3567;
3568; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i100:
3569; CHECK-GI-CVT:       // %bb.0:
3570; CHECK-GI-CVT-NEXT:    mov h1, v0.h[1]
3571; CHECK-GI-CVT-NEXT:    mov h2, v0.h[2]
3572; CHECK-GI-CVT-NEXT:    mov x11, x8
3573; CHECK-GI-CVT-NEXT:    fcvt s3, h0
3574; CHECK-GI-CVT-NEXT:    mov h4, v0.h[3]
3575; CHECK-GI-CVT-NEXT:    str wzr, [x8, #8]
3576; CHECK-GI-CVT-NEXT:    strb wzr, [x8, #12]
3577; CHECK-GI-CVT-NEXT:    fcvt s1, h1
3578; CHECK-GI-CVT-NEXT:    fcvt s2, h2
3579; CHECK-GI-CVT-NEXT:    fcvtzu x9, s3
3580; CHECK-GI-CVT-NEXT:    fcvt s3, h4
3581; CHECK-GI-CVT-NEXT:    fcvtzu x10, s1
3582; CHECK-GI-CVT-NEXT:    mov h1, v0.h[4]
3583; CHECK-GI-CVT-NEXT:    fcvtzu x12, s2
3584; CHECK-GI-CVT-NEXT:    mov h2, v0.h[5]
3585; CHECK-GI-CVT-NEXT:    str x9, [x8]
3586; CHECK-GI-CVT-NEXT:    mov x9, x8
3587; CHECK-GI-CVT-NEXT:    fcvt s1, h1
3588; CHECK-GI-CVT-NEXT:    str x10, [x11, #12]!
3589; CHECK-GI-CVT-NEXT:    fcvtzu x10, s3
3590; CHECK-GI-CVT-NEXT:    mov h3, v0.h[6]
3591; CHECK-GI-CVT-NEXT:    fcvt s2, h2
3592; CHECK-GI-CVT-NEXT:    mov h0, v0.h[7]
3593; CHECK-GI-CVT-NEXT:    str wzr, [x11, #8]
3594; CHECK-GI-CVT-NEXT:    strb wzr, [x11, #12]
3595; CHECK-GI-CVT-NEXT:    mov x11, x8
3596; CHECK-GI-CVT-NEXT:    str x12, [x9, #25]!
3597; CHECK-GI-CVT-NEXT:    fcvtzu x12, s1
3598; CHECK-GI-CVT-NEXT:    str wzr, [x9, #8]
3599; CHECK-GI-CVT-NEXT:    fcvt s1, h3
3600; CHECK-GI-CVT-NEXT:    strb wzr, [x9, #12]
3601; CHECK-GI-CVT-NEXT:    fcvt s0, h0
3602; CHECK-GI-CVT-NEXT:    mov x9, x8
3603; CHECK-GI-CVT-NEXT:    str x10, [x11, #37]!
3604; CHECK-GI-CVT-NEXT:    fcvtzu x10, s2
3605; CHECK-GI-CVT-NEXT:    str wzr, [x11, #8]
3606; CHECK-GI-CVT-NEXT:    strb wzr, [x11, #12]
3607; CHECK-GI-CVT-NEXT:    fcvtzu x11, s1
3608; CHECK-GI-CVT-NEXT:    str x12, [x9, #50]!
3609; CHECK-GI-CVT-NEXT:    str wzr, [x9, #8]
3610; CHECK-GI-CVT-NEXT:    strb wzr, [x9, #12]
3611; CHECK-GI-CVT-NEXT:    mov x9, x8
3612; CHECK-GI-CVT-NEXT:    str x10, [x9, #62]!
3613; CHECK-GI-CVT-NEXT:    fcvtzu x10, s0
3614; CHECK-GI-CVT-NEXT:    str wzr, [x9, #8]
3615; CHECK-GI-CVT-NEXT:    strb wzr, [x9, #12]
3616; CHECK-GI-CVT-NEXT:    mov x9, x8
3617; CHECK-GI-CVT-NEXT:    str x11, [x9, #75]!
3618; CHECK-GI-CVT-NEXT:    str wzr, [x9, #8]
3619; CHECK-GI-CVT-NEXT:    strb wzr, [x9, #12]
3620; CHECK-GI-CVT-NEXT:    str x10, [x8, #87]!
3621; CHECK-GI-CVT-NEXT:    str wzr, [x8, #8]
3622; CHECK-GI-CVT-NEXT:    strb wzr, [x8, #12]
3623; CHECK-GI-CVT-NEXT:    ret
3624;
3625; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i100:
3626; CHECK-GI-FP16:       // %bb.0:
3627; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
3628; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
3629; CHECK-GI-FP16-NEXT:    mov x11, x8
3630; CHECK-GI-FP16-NEXT:    fcvtzu x9, h0
3631; CHECK-GI-FP16-NEXT:    str wzr, [x8, #8]
3632; CHECK-GI-FP16-NEXT:    strb wzr, [x8, #12]
3633; CHECK-GI-FP16-NEXT:    fcvtzu x10, h1
3634; CHECK-GI-FP16-NEXT:    mov h1, v0.h[3]
3635; CHECK-GI-FP16-NEXT:    fcvtzu x12, h2
3636; CHECK-GI-FP16-NEXT:    mov h2, v0.h[4]
3637; CHECK-GI-FP16-NEXT:    str x9, [x8]
3638; CHECK-GI-FP16-NEXT:    mov x9, x8
3639; CHECK-GI-FP16-NEXT:    str x10, [x11, #12]!
3640; CHECK-GI-FP16-NEXT:    fcvtzu x10, h1
3641; CHECK-GI-FP16-NEXT:    mov h1, v0.h[5]
3642; CHECK-GI-FP16-NEXT:    str wzr, [x11, #8]
3643; CHECK-GI-FP16-NEXT:    strb wzr, [x11, #12]
3644; CHECK-GI-FP16-NEXT:    mov x11, x8
3645; CHECK-GI-FP16-NEXT:    str x12, [x9, #25]!
3646; CHECK-GI-FP16-NEXT:    fcvtzu x12, h2
3647; CHECK-GI-FP16-NEXT:    str wzr, [x9, #8]
3648; CHECK-GI-FP16-NEXT:    mov h2, v0.h[6]
3649; CHECK-GI-FP16-NEXT:    mov h0, v0.h[7]
3650; CHECK-GI-FP16-NEXT:    strb wzr, [x9, #12]
3651; CHECK-GI-FP16-NEXT:    fcvtzu x9, h1
3652; CHECK-GI-FP16-NEXT:    str x10, [x11, #37]!
3653; CHECK-GI-FP16-NEXT:    mov x10, x8
3654; CHECK-GI-FP16-NEXT:    str wzr, [x11, #8]
3655; CHECK-GI-FP16-NEXT:    strb wzr, [x11, #12]
3656; CHECK-GI-FP16-NEXT:    fcvtzu x11, h2
3657; CHECK-GI-FP16-NEXT:    str x12, [x10, #50]!
3658; CHECK-GI-FP16-NEXT:    str wzr, [x10, #8]
3659; CHECK-GI-FP16-NEXT:    strb wzr, [x10, #12]
3660; CHECK-GI-FP16-NEXT:    mov x10, x8
3661; CHECK-GI-FP16-NEXT:    str x9, [x10, #62]!
3662; CHECK-GI-FP16-NEXT:    fcvtzu x9, h0
3663; CHECK-GI-FP16-NEXT:    str wzr, [x10, #8]
3664; CHECK-GI-FP16-NEXT:    strb wzr, [x10, #12]
3665; CHECK-GI-FP16-NEXT:    mov x10, x8
3666; CHECK-GI-FP16-NEXT:    str x11, [x10, #75]!
3667; CHECK-GI-FP16-NEXT:    str wzr, [x10, #8]
3668; CHECK-GI-FP16-NEXT:    strb wzr, [x10, #12]
3669; CHECK-GI-FP16-NEXT:    str x9, [x8, #87]!
3670; CHECK-GI-FP16-NEXT:    str wzr, [x8, #8]
3671; CHECK-GI-FP16-NEXT:    strb wzr, [x8, #12]
3672; CHECK-GI-FP16-NEXT:    ret
3673    %x = call <8 x i100> @llvm.fptoui.sat.v8f16.v8i100(<8 x half> %f)
3674    ret <8 x i100> %x
3675}
3676
3677define <8 x i128> @test_unsigned_v8f16_v8i128(<8 x half> %f) {
3678; CHECK-SD-LABEL: test_unsigned_v8f16_v8i128:
3679; CHECK-SD:       // %bb.0:
3680; CHECK-SD-NEXT:    sub sp, sp, #176
3681; CHECK-SD-NEXT:    stp d9, d8, [sp, #64] // 16-byte Folded Spill
3682; CHECK-SD-NEXT:    stp x29, x30, [sp, #80] // 16-byte Folded Spill
3683; CHECK-SD-NEXT:    stp x28, x27, [sp, #96] // 16-byte Folded Spill
3684; CHECK-SD-NEXT:    stp x26, x25, [sp, #112] // 16-byte Folded Spill
3685; CHECK-SD-NEXT:    stp x24, x23, [sp, #128] // 16-byte Folded Spill
3686; CHECK-SD-NEXT:    stp x22, x21, [sp, #144] // 16-byte Folded Spill
3687; CHECK-SD-NEXT:    stp x20, x19, [sp, #160] // 16-byte Folded Spill
3688; CHECK-SD-NEXT:    .cfi_def_cfa_offset 176
3689; CHECK-SD-NEXT:    .cfi_offset w19, -8
3690; CHECK-SD-NEXT:    .cfi_offset w20, -16
3691; CHECK-SD-NEXT:    .cfi_offset w21, -24
3692; CHECK-SD-NEXT:    .cfi_offset w22, -32
3693; CHECK-SD-NEXT:    .cfi_offset w23, -40
3694; CHECK-SD-NEXT:    .cfi_offset w24, -48
3695; CHECK-SD-NEXT:    .cfi_offset w25, -56
3696; CHECK-SD-NEXT:    .cfi_offset w26, -64
3697; CHECK-SD-NEXT:    .cfi_offset w27, -72
3698; CHECK-SD-NEXT:    .cfi_offset w28, -80
3699; CHECK-SD-NEXT:    .cfi_offset w30, -88
3700; CHECK-SD-NEXT:    .cfi_offset w29, -96
3701; CHECK-SD-NEXT:    .cfi_offset b8, -104
3702; CHECK-SD-NEXT:    .cfi_offset b9, -112
3703; CHECK-SD-NEXT:    str q0, [sp, #48] // 16-byte Folded Spill
3704; CHECK-SD-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
3705; CHECK-SD-NEXT:    mov x19, x8
3706; CHECK-SD-NEXT:    fcvt s8, h0
3707; CHECK-SD-NEXT:    str q0, [sp, #32] // 16-byte Folded Spill
3708; CHECK-SD-NEXT:    fmov s0, s8
3709; CHECK-SD-NEXT:    bl __fixunssfti
3710; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3711; CHECK-SD-NEXT:    mov w8, #2139095039 // =0x7f7fffff
3712; CHECK-SD-NEXT:    fcmp s8, #0.0
3713; CHECK-SD-NEXT:    fmov s9, w8
3714; CHECK-SD-NEXT:    mov h0, v0.h[1]
3715; CHECK-SD-NEXT:    csel x9, xzr, x1, lt
3716; CHECK-SD-NEXT:    csel x8, xzr, x0, lt
3717; CHECK-SD-NEXT:    fcmp s8, s9
3718; CHECK-SD-NEXT:    fcvt s8, h0
3719; CHECK-SD-NEXT:    csinv x10, x8, xzr, le
3720; CHECK-SD-NEXT:    csinv x8, x9, xzr, le
3721; CHECK-SD-NEXT:    stp x8, x10, [sp, #16] // 16-byte Folded Spill
3722; CHECK-SD-NEXT:    fmov s0, s8
3723; CHECK-SD-NEXT:    bl __fixunssfti
3724; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3725; CHECK-SD-NEXT:    fcmp s8, #0.0
3726; CHECK-SD-NEXT:    mov h0, v0.h[2]
3727; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3728; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3729; CHECK-SD-NEXT:    fcmp s8, s9
3730; CHECK-SD-NEXT:    fcvt s8, h0
3731; CHECK-SD-NEXT:    csinv x9, x9, xzr, le
3732; CHECK-SD-NEXT:    csinv x8, x8, xzr, le
3733; CHECK-SD-NEXT:    stp x8, x9, [sp] // 16-byte Folded Spill
3734; CHECK-SD-NEXT:    fmov s0, s8
3735; CHECK-SD-NEXT:    bl __fixunssfti
3736; CHECK-SD-NEXT:    ldr q0, [sp, #32] // 16-byte Folded Reload
3737; CHECK-SD-NEXT:    fcmp s8, #0.0
3738; CHECK-SD-NEXT:    mov h0, v0.h[3]
3739; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3740; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3741; CHECK-SD-NEXT:    fcmp s8, s9
3742; CHECK-SD-NEXT:    fcvt s8, h0
3743; CHECK-SD-NEXT:    csinv x24, x9, xzr, le
3744; CHECK-SD-NEXT:    csinv x25, x8, xzr, le
3745; CHECK-SD-NEXT:    fmov s0, s8
3746; CHECK-SD-NEXT:    bl __fixunssfti
3747; CHECK-SD-NEXT:    fcmp s8, #0.0
3748; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3749; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3750; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3751; CHECK-SD-NEXT:    fcmp s8, s9
3752; CHECK-SD-NEXT:    fcvt s8, h0
3753; CHECK-SD-NEXT:    csinv x26, x9, xzr, le
3754; CHECK-SD-NEXT:    csinv x27, x8, xzr, le
3755; CHECK-SD-NEXT:    fmov s0, s8
3756; CHECK-SD-NEXT:    bl __fixunssfti
3757; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3758; CHECK-SD-NEXT:    fcmp s8, #0.0
3759; CHECK-SD-NEXT:    mov h0, v0.h[1]
3760; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3761; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3762; CHECK-SD-NEXT:    fcmp s8, s9
3763; CHECK-SD-NEXT:    fcvt s8, h0
3764; CHECK-SD-NEXT:    csinv x28, x9, xzr, le
3765; CHECK-SD-NEXT:    csinv x29, x8, xzr, le
3766; CHECK-SD-NEXT:    fmov s0, s8
3767; CHECK-SD-NEXT:    bl __fixunssfti
3768; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3769; CHECK-SD-NEXT:    fcmp s8, #0.0
3770; CHECK-SD-NEXT:    mov h0, v0.h[2]
3771; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3772; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3773; CHECK-SD-NEXT:    fcmp s8, s9
3774; CHECK-SD-NEXT:    fcvt s8, h0
3775; CHECK-SD-NEXT:    csinv x20, x9, xzr, le
3776; CHECK-SD-NEXT:    csinv x21, x8, xzr, le
3777; CHECK-SD-NEXT:    fmov s0, s8
3778; CHECK-SD-NEXT:    bl __fixunssfti
3779; CHECK-SD-NEXT:    ldr q0, [sp, #48] // 16-byte Folded Reload
3780; CHECK-SD-NEXT:    fcmp s8, #0.0
3781; CHECK-SD-NEXT:    mov h0, v0.h[3]
3782; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3783; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3784; CHECK-SD-NEXT:    fcmp s8, s9
3785; CHECK-SD-NEXT:    fcvt s8, h0
3786; CHECK-SD-NEXT:    csinv x22, x9, xzr, le
3787; CHECK-SD-NEXT:    csinv x23, x8, xzr, le
3788; CHECK-SD-NEXT:    fmov s0, s8
3789; CHECK-SD-NEXT:    bl __fixunssfti
3790; CHECK-SD-NEXT:    fcmp s8, #0.0
3791; CHECK-SD-NEXT:    stp x22, x23, [x19, #32]
3792; CHECK-SD-NEXT:    stp x20, x21, [x19, #16]
3793; CHECK-SD-NEXT:    stp x28, x29, [x19]
3794; CHECK-SD-NEXT:    csel x8, xzr, x1, lt
3795; CHECK-SD-NEXT:    csel x9, xzr, x0, lt
3796; CHECK-SD-NEXT:    fcmp s8, s9
3797; CHECK-SD-NEXT:    stp x26, x27, [x19, #112]
3798; CHECK-SD-NEXT:    stp x24, x25, [x19, #96]
3799; CHECK-SD-NEXT:    csinv x8, x8, xzr, le
3800; CHECK-SD-NEXT:    csinv x9, x9, xzr, le
3801; CHECK-SD-NEXT:    stp x9, x8, [x19, #48]
3802; CHECK-SD-NEXT:    ldr x8, [sp] // 8-byte Folded Reload
3803; CHECK-SD-NEXT:    str x8, [x19, #88]
3804; CHECK-SD-NEXT:    ldr x8, [sp, #8] // 8-byte Folded Reload
3805; CHECK-SD-NEXT:    str x8, [x19, #80]
3806; CHECK-SD-NEXT:    ldr x8, [sp, #16] // 8-byte Folded Reload
3807; CHECK-SD-NEXT:    str x8, [x19, #72]
3808; CHECK-SD-NEXT:    ldr x8, [sp, #24] // 8-byte Folded Reload
3809; CHECK-SD-NEXT:    str x8, [x19, #64]
3810; CHECK-SD-NEXT:    ldp x20, x19, [sp, #160] // 16-byte Folded Reload
3811; CHECK-SD-NEXT:    ldp x22, x21, [sp, #144] // 16-byte Folded Reload
3812; CHECK-SD-NEXT:    ldp x24, x23, [sp, #128] // 16-byte Folded Reload
3813; CHECK-SD-NEXT:    ldp x26, x25, [sp, #112] // 16-byte Folded Reload
3814; CHECK-SD-NEXT:    ldp x28, x27, [sp, #96] // 16-byte Folded Reload
3815; CHECK-SD-NEXT:    ldp x29, x30, [sp, #80] // 16-byte Folded Reload
3816; CHECK-SD-NEXT:    ldp d9, d8, [sp, #64] // 16-byte Folded Reload
3817; CHECK-SD-NEXT:    add sp, sp, #176
3818; CHECK-SD-NEXT:    ret
3819;
3820; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i128:
3821; CHECK-GI-CVT:       // %bb.0:
3822; CHECK-GI-CVT-NEXT:    mov h1, v0.h[1]
3823; CHECK-GI-CVT-NEXT:    mov h2, v0.h[2]
3824; CHECK-GI-CVT-NEXT:    mov h3, v0.h[3]
3825; CHECK-GI-CVT-NEXT:    mov h4, v0.h[4]
3826; CHECK-GI-CVT-NEXT:    fcvt s5, h0
3827; CHECK-GI-CVT-NEXT:    mov h6, v0.h[5]
3828; CHECK-GI-CVT-NEXT:    mov h7, v0.h[6]
3829; CHECK-GI-CVT-NEXT:    mov h0, v0.h[7]
3830; CHECK-GI-CVT-NEXT:    fcvt s1, h1
3831; CHECK-GI-CVT-NEXT:    fcvt s2, h2
3832; CHECK-GI-CVT-NEXT:    fcvt s3, h3
3833; CHECK-GI-CVT-NEXT:    fcvtzu x9, s5
3834; CHECK-GI-CVT-NEXT:    fcvt s4, h4
3835; CHECK-GI-CVT-NEXT:    fcvt s5, h6
3836; CHECK-GI-CVT-NEXT:    fcvt s0, h0
3837; CHECK-GI-CVT-NEXT:    fcvtzu x10, s1
3838; CHECK-GI-CVT-NEXT:    fcvt s1, h7
3839; CHECK-GI-CVT-NEXT:    fcvtzu x11, s2
3840; CHECK-GI-CVT-NEXT:    fcvtzu x12, s3
3841; CHECK-GI-CVT-NEXT:    mov v2.d[0], x9
3842; CHECK-GI-CVT-NEXT:    fcvtzu x9, s4
3843; CHECK-GI-CVT-NEXT:    mov v3.d[0], x10
3844; CHECK-GI-CVT-NEXT:    fcvtzu x10, s5
3845; CHECK-GI-CVT-NEXT:    mov v4.d[0], x11
3846; CHECK-GI-CVT-NEXT:    fcvtzu x11, s1
3847; CHECK-GI-CVT-NEXT:    mov v1.d[0], x12
3848; CHECK-GI-CVT-NEXT:    fcvtzu x12, s0
3849; CHECK-GI-CVT-NEXT:    mov v0.d[0], x9
3850; CHECK-GI-CVT-NEXT:    mov v2.d[1], xzr
3851; CHECK-GI-CVT-NEXT:    mov v5.d[0], x10
3852; CHECK-GI-CVT-NEXT:    mov v3.d[1], xzr
3853; CHECK-GI-CVT-NEXT:    mov v4.d[1], xzr
3854; CHECK-GI-CVT-NEXT:    mov v6.d[0], x11
3855; CHECK-GI-CVT-NEXT:    mov v7.d[0], x12
3856; CHECK-GI-CVT-NEXT:    mov v1.d[1], xzr
3857; CHECK-GI-CVT-NEXT:    mov v0.d[1], xzr
3858; CHECK-GI-CVT-NEXT:    mov v5.d[1], xzr
3859; CHECK-GI-CVT-NEXT:    stp q2, q3, [x8]
3860; CHECK-GI-CVT-NEXT:    mov v6.d[1], xzr
3861; CHECK-GI-CVT-NEXT:    mov v7.d[1], xzr
3862; CHECK-GI-CVT-NEXT:    stp q4, q1, [x8, #32]
3863; CHECK-GI-CVT-NEXT:    stp q0, q5, [x8, #64]
3864; CHECK-GI-CVT-NEXT:    stp q6, q7, [x8, #96]
3865; CHECK-GI-CVT-NEXT:    ret
3866;
3867; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i128:
3868; CHECK-GI-FP16:       // %bb.0:
3869; CHECK-GI-FP16-NEXT:    mov h1, v0.h[1]
3870; CHECK-GI-FP16-NEXT:    mov h2, v0.h[2]
3871; CHECK-GI-FP16-NEXT:    mov h3, v0.h[3]
3872; CHECK-GI-FP16-NEXT:    mov h4, v0.h[4]
3873; CHECK-GI-FP16-NEXT:    fcvtzu x9, h0
3874; CHECK-GI-FP16-NEXT:    mov h5, v0.h[5]
3875; CHECK-GI-FP16-NEXT:    fcvtzu x10, h1
3876; CHECK-GI-FP16-NEXT:    mov h1, v0.h[6]
3877; CHECK-GI-FP16-NEXT:    fcvtzu x11, h2
3878; CHECK-GI-FP16-NEXT:    mov h0, v0.h[7]
3879; CHECK-GI-FP16-NEXT:    fcvtzu x12, h3
3880; CHECK-GI-FP16-NEXT:    mov v2.d[0], x9
3881; CHECK-GI-FP16-NEXT:    fcvtzu x9, h4
3882; CHECK-GI-FP16-NEXT:    mov v3.d[0], x10
3883; CHECK-GI-FP16-NEXT:    fcvtzu x10, h5
3884; CHECK-GI-FP16-NEXT:    mov v4.d[0], x11
3885; CHECK-GI-FP16-NEXT:    fcvtzu x11, h1
3886; CHECK-GI-FP16-NEXT:    mov v1.d[0], x12
3887; CHECK-GI-FP16-NEXT:    fcvtzu x12, h0
3888; CHECK-GI-FP16-NEXT:    mov v0.d[0], x9
3889; CHECK-GI-FP16-NEXT:    mov v2.d[1], xzr
3890; CHECK-GI-FP16-NEXT:    mov v5.d[0], x10
3891; CHECK-GI-FP16-NEXT:    mov v3.d[1], xzr
3892; CHECK-GI-FP16-NEXT:    mov v4.d[1], xzr
3893; CHECK-GI-FP16-NEXT:    mov v6.d[0], x11
3894; CHECK-GI-FP16-NEXT:    mov v7.d[0], x12
3895; CHECK-GI-FP16-NEXT:    mov v1.d[1], xzr
3896; CHECK-GI-FP16-NEXT:    mov v0.d[1], xzr
3897; CHECK-GI-FP16-NEXT:    mov v5.d[1], xzr
3898; CHECK-GI-FP16-NEXT:    stp q2, q3, [x8]
3899; CHECK-GI-FP16-NEXT:    mov v6.d[1], xzr
3900; CHECK-GI-FP16-NEXT:    mov v7.d[1], xzr
3901; CHECK-GI-FP16-NEXT:    stp q4, q1, [x8, #32]
3902; CHECK-GI-FP16-NEXT:    stp q0, q5, [x8, #64]
3903; CHECK-GI-FP16-NEXT:    stp q6, q7, [x8, #96]
3904; CHECK-GI-FP16-NEXT:    ret
3905    %x = call <8 x i128> @llvm.fptoui.sat.v8f16.v8i128(<8 x half> %f)
3906    ret <8 x i128> %x
3907}
3908
3909
3910declare <8 x i8> @llvm.fptoui.sat.v8f32.v8i8(<8 x float> %f)
3911declare <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f)
3912declare <16 x i8> @llvm.fptoui.sat.v16f32.v16i8(<16 x float> %f)
3913declare <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f)
3914
3915declare <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f)
3916declare <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f)
3917
3918declare <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f)
3919declare <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f)
3920declare <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f)
3921declare <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f)
3922
3923define <8 x i8> @test_unsigned_v8f32_v8i8(<8 x float> %f) {
3924; CHECK-SD-LABEL: test_unsigned_v8f32_v8i8:
3925; CHECK-SD:       // %bb.0:
3926; CHECK-SD-NEXT:    movi v2.2d, #0x0000ff000000ff
3927; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
3928; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
3929; CHECK-SD-NEXT:    umin v1.4s, v1.4s, v2.4s
3930; CHECK-SD-NEXT:    umin v0.4s, v0.4s, v2.4s
3931; CHECK-SD-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
3932; CHECK-SD-NEXT:    xtn v0.8b, v0.8h
3933; CHECK-SD-NEXT:    ret
3934;
3935; CHECK-GI-LABEL: test_unsigned_v8f32_v8i8:
3936; CHECK-GI:       // %bb.0:
3937; CHECK-GI-NEXT:    movi v2.2d, #0x0000ff000000ff
3938; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
3939; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
3940; CHECK-GI-NEXT:    umin v0.4s, v0.4s, v2.4s
3941; CHECK-GI-NEXT:    umin v1.4s, v1.4s, v2.4s
3942; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
3943; CHECK-GI-NEXT:    xtn v0.8b, v0.8h
3944; CHECK-GI-NEXT:    ret
3945    %x = call <8 x i8> @llvm.fptoui.sat.v8f32.v8i8(<8 x float> %f)
3946    ret <8 x i8> %x
3947}
3948
3949define <16 x i8> @test_unsigned_v16f32_v16i8(<16 x float> %f) {
3950; CHECK-SD-LABEL: test_unsigned_v16f32_v16i8:
3951; CHECK-SD:       // %bb.0:
3952; CHECK-SD-NEXT:    movi v4.2d, #0x0000ff000000ff
3953; CHECK-SD-NEXT:    fcvtzu v3.4s, v3.4s
3954; CHECK-SD-NEXT:    fcvtzu v2.4s, v2.4s
3955; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
3956; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
3957; CHECK-SD-NEXT:    umin v3.4s, v3.4s, v4.4s
3958; CHECK-SD-NEXT:    umin v2.4s, v2.4s, v4.4s
3959; CHECK-SD-NEXT:    umin v1.4s, v1.4s, v4.4s
3960; CHECK-SD-NEXT:    umin v0.4s, v0.4s, v4.4s
3961; CHECK-SD-NEXT:    uzp1 v2.8h, v2.8h, v3.8h
3962; CHECK-SD-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
3963; CHECK-SD-NEXT:    uzp1 v0.16b, v0.16b, v2.16b
3964; CHECK-SD-NEXT:    ret
3965;
3966; CHECK-GI-LABEL: test_unsigned_v16f32_v16i8:
3967; CHECK-GI:       // %bb.0:
3968; CHECK-GI-NEXT:    movi v4.2d, #0x0000ff000000ff
3969; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
3970; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
3971; CHECK-GI-NEXT:    fcvtzu v2.4s, v2.4s
3972; CHECK-GI-NEXT:    fcvtzu v3.4s, v3.4s
3973; CHECK-GI-NEXT:    umin v0.4s, v0.4s, v4.4s
3974; CHECK-GI-NEXT:    umin v1.4s, v1.4s, v4.4s
3975; CHECK-GI-NEXT:    umin v2.4s, v2.4s, v4.4s
3976; CHECK-GI-NEXT:    umin v3.4s, v3.4s, v4.4s
3977; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
3978; CHECK-GI-NEXT:    uzp1 v1.8h, v2.8h, v3.8h
3979; CHECK-GI-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
3980; CHECK-GI-NEXT:    ret
3981    %x = call <16 x i8> @llvm.fptoui.sat.v16f32.v16i8(<16 x float> %f)
3982    ret <16 x i8> %x
3983}
3984
3985define <8 x i16> @test_unsigned_v8f32_v8i16(<8 x float> %f) {
3986; CHECK-SD-LABEL: test_unsigned_v8f32_v8i16:
3987; CHECK-SD:       // %bb.0:
3988; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
3989; CHECK-SD-NEXT:    fcvtzu v1.4s, v1.4s
3990; CHECK-SD-NEXT:    uqxtn v0.4h, v0.4s
3991; CHECK-SD-NEXT:    uqxtn2 v0.8h, v1.4s
3992; CHECK-SD-NEXT:    ret
3993;
3994; CHECK-GI-LABEL: test_unsigned_v8f32_v8i16:
3995; CHECK-GI:       // %bb.0:
3996; CHECK-GI-NEXT:    movi v2.2d, #0x00ffff0000ffff
3997; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
3998; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
3999; CHECK-GI-NEXT:    umin v0.4s, v0.4s, v2.4s
4000; CHECK-GI-NEXT:    umin v1.4s, v1.4s, v2.4s
4001; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4002; CHECK-GI-NEXT:    ret
4003    %x = call <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f)
4004    ret <8 x i16> %x
4005}
4006
4007define <16 x i16> @test_unsigned_v16f32_v16i16(<16 x float> %f) {
4008; CHECK-SD-LABEL: test_unsigned_v16f32_v16i16:
4009; CHECK-SD:       // %bb.0:
4010; CHECK-SD-NEXT:    fcvtzu v0.4s, v0.4s
4011; CHECK-SD-NEXT:    fcvtzu v2.4s, v2.4s
4012; CHECK-SD-NEXT:    fcvtzu v4.4s, v1.4s
4013; CHECK-SD-NEXT:    uqxtn v0.4h, v0.4s
4014; CHECK-SD-NEXT:    uqxtn v1.4h, v2.4s
4015; CHECK-SD-NEXT:    fcvtzu v2.4s, v3.4s
4016; CHECK-SD-NEXT:    uqxtn2 v0.8h, v4.4s
4017; CHECK-SD-NEXT:    uqxtn2 v1.8h, v2.4s
4018; CHECK-SD-NEXT:    ret
4019;
4020; CHECK-GI-LABEL: test_unsigned_v16f32_v16i16:
4021; CHECK-GI:       // %bb.0:
4022; CHECK-GI-NEXT:    movi v4.2d, #0x00ffff0000ffff
4023; CHECK-GI-NEXT:    fcvtzu v0.4s, v0.4s
4024; CHECK-GI-NEXT:    fcvtzu v1.4s, v1.4s
4025; CHECK-GI-NEXT:    fcvtzu v2.4s, v2.4s
4026; CHECK-GI-NEXT:    fcvtzu v3.4s, v3.4s
4027; CHECK-GI-NEXT:    umin v0.4s, v0.4s, v4.4s
4028; CHECK-GI-NEXT:    umin v1.4s, v1.4s, v4.4s
4029; CHECK-GI-NEXT:    umin v2.4s, v2.4s, v4.4s
4030; CHECK-GI-NEXT:    umin v3.4s, v3.4s, v4.4s
4031; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4032; CHECK-GI-NEXT:    uzp1 v1.8h, v2.8h, v3.8h
4033; CHECK-GI-NEXT:    ret
4034    %x = call <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f)
4035    ret <16 x i16> %x
4036}
4037
4038
4039
4040define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) {
4041; CHECK-SD-CVT-LABEL: test_unsigned_v16f16_v16i8:
4042; CHECK-SD-CVT:       // %bb.0:
4043; CHECK-SD-CVT-NEXT:    fcvtl2 v3.4s, v1.8h
4044; CHECK-SD-CVT-NEXT:    fcvtl v1.4s, v1.4h
4045; CHECK-SD-CVT-NEXT:    fcvtl2 v4.4s, v0.8h
4046; CHECK-SD-CVT-NEXT:    fcvtl v0.4s, v0.4h
4047; CHECK-SD-CVT-NEXT:    movi v2.2d, #0x0000ff000000ff
4048; CHECK-SD-CVT-NEXT:    fcvtzu v3.4s, v3.4s
4049; CHECK-SD-CVT-NEXT:    fcvtzu v1.4s, v1.4s
4050; CHECK-SD-CVT-NEXT:    fcvtzu v4.4s, v4.4s
4051; CHECK-SD-CVT-NEXT:    fcvtzu v0.4s, v0.4s
4052; CHECK-SD-CVT-NEXT:    umin v3.4s, v3.4s, v2.4s
4053; CHECK-SD-CVT-NEXT:    umin v1.4s, v1.4s, v2.4s
4054; CHECK-SD-CVT-NEXT:    umin v4.4s, v4.4s, v2.4s
4055; CHECK-SD-CVT-NEXT:    umin v0.4s, v0.4s, v2.4s
4056; CHECK-SD-CVT-NEXT:    uzp1 v1.8h, v1.8h, v3.8h
4057; CHECK-SD-CVT-NEXT:    uzp1 v0.8h, v0.8h, v4.8h
4058; CHECK-SD-CVT-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
4059; CHECK-SD-CVT-NEXT:    ret
4060;
4061; CHECK-SD-FP16-LABEL: test_unsigned_v16f16_v16i8:
4062; CHECK-SD-FP16:       // %bb.0:
4063; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
4064; CHECK-SD-FP16-NEXT:    fcvtzu v1.8h, v1.8h
4065; CHECK-SD-FP16-NEXT:    uqxtn v0.8b, v0.8h
4066; CHECK-SD-FP16-NEXT:    uqxtn2 v0.16b, v1.8h
4067; CHECK-SD-FP16-NEXT:    ret
4068;
4069; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i8:
4070; CHECK-GI-CVT:       // %bb.0:
4071; CHECK-GI-CVT-NEXT:    fcvtl v3.4s, v0.4h
4072; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
4073; CHECK-GI-CVT-NEXT:    fcvtl v4.4s, v1.4h
4074; CHECK-GI-CVT-NEXT:    fcvtl2 v1.4s, v1.8h
4075; CHECK-GI-CVT-NEXT:    movi v2.2d, #0x0000ff000000ff
4076; CHECK-GI-CVT-NEXT:    fcvtzu v3.4s, v3.4s
4077; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
4078; CHECK-GI-CVT-NEXT:    fcvtzu v4.4s, v4.4s
4079; CHECK-GI-CVT-NEXT:    fcvtzu v1.4s, v1.4s
4080; CHECK-GI-CVT-NEXT:    umin v3.4s, v3.4s, v2.4s
4081; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v2.4s
4082; CHECK-GI-CVT-NEXT:    umin v4.4s, v4.4s, v2.4s
4083; CHECK-GI-CVT-NEXT:    umin v1.4s, v1.4s, v2.4s
4084; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v3.8h, v0.8h
4085; CHECK-GI-CVT-NEXT:    uzp1 v1.8h, v4.8h, v1.8h
4086; CHECK-GI-CVT-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
4087; CHECK-GI-CVT-NEXT:    ret
4088;
4089; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i8:
4090; CHECK-GI-FP16:       // %bb.0:
4091; CHECK-GI-FP16-NEXT:    movi v2.2d, #0xff00ff00ff00ff
4092; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
4093; CHECK-GI-FP16-NEXT:    fcvtzu v1.8h, v1.8h
4094; CHECK-GI-FP16-NEXT:    umin v0.8h, v0.8h, v2.8h
4095; CHECK-GI-FP16-NEXT:    umin v1.8h, v1.8h, v2.8h
4096; CHECK-GI-FP16-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
4097; CHECK-GI-FP16-NEXT:    ret
4098    %x = call <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f)
4099    ret <16 x i8> %x
4100}
4101
4102define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
4103; CHECK-SD-CVT-LABEL: test_unsigned_v16f16_v16i16:
4104; CHECK-SD-CVT:       // %bb.0:
4105; CHECK-SD-CVT-NEXT:    fcvtl v2.4s, v0.4h
4106; CHECK-SD-CVT-NEXT:    fcvtl v3.4s, v1.4h
4107; CHECK-SD-CVT-NEXT:    fcvtl2 v4.4s, v0.8h
4108; CHECK-SD-CVT-NEXT:    fcvtl2 v5.4s, v1.8h
4109; CHECK-SD-CVT-NEXT:    fcvtzu v2.4s, v2.4s
4110; CHECK-SD-CVT-NEXT:    fcvtzu v1.4s, v3.4s
4111; CHECK-SD-CVT-NEXT:    fcvtzu v3.4s, v5.4s
4112; CHECK-SD-CVT-NEXT:    uqxtn v0.4h, v2.4s
4113; CHECK-SD-CVT-NEXT:    fcvtzu v2.4s, v4.4s
4114; CHECK-SD-CVT-NEXT:    uqxtn v1.4h, v1.4s
4115; CHECK-SD-CVT-NEXT:    uqxtn2 v0.8h, v2.4s
4116; CHECK-SD-CVT-NEXT:    uqxtn2 v1.8h, v3.4s
4117; CHECK-SD-CVT-NEXT:    ret
4118;
4119; CHECK-SD-FP16-LABEL: test_unsigned_v16f16_v16i16:
4120; CHECK-SD-FP16:       // %bb.0:
4121; CHECK-SD-FP16-NEXT:    fcvtzu v0.8h, v0.8h
4122; CHECK-SD-FP16-NEXT:    fcvtzu v1.8h, v1.8h
4123; CHECK-SD-FP16-NEXT:    ret
4124;
4125; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i16:
4126; CHECK-GI-CVT:       // %bb.0:
4127; CHECK-GI-CVT-NEXT:    fcvtl v3.4s, v0.4h
4128; CHECK-GI-CVT-NEXT:    fcvtl2 v0.4s, v0.8h
4129; CHECK-GI-CVT-NEXT:    fcvtl v4.4s, v1.4h
4130; CHECK-GI-CVT-NEXT:    fcvtl2 v1.4s, v1.8h
4131; CHECK-GI-CVT-NEXT:    movi v2.2d, #0x00ffff0000ffff
4132; CHECK-GI-CVT-NEXT:    fcvtzu v3.4s, v3.4s
4133; CHECK-GI-CVT-NEXT:    fcvtzu v0.4s, v0.4s
4134; CHECK-GI-CVT-NEXT:    fcvtzu v4.4s, v4.4s
4135; CHECK-GI-CVT-NEXT:    fcvtzu v1.4s, v1.4s
4136; CHECK-GI-CVT-NEXT:    umin v3.4s, v3.4s, v2.4s
4137; CHECK-GI-CVT-NEXT:    umin v0.4s, v0.4s, v2.4s
4138; CHECK-GI-CVT-NEXT:    umin v4.4s, v4.4s, v2.4s
4139; CHECK-GI-CVT-NEXT:    umin v1.4s, v1.4s, v2.4s
4140; CHECK-GI-CVT-NEXT:    uzp1 v0.8h, v3.8h, v0.8h
4141; CHECK-GI-CVT-NEXT:    uzp1 v1.8h, v4.8h, v1.8h
4142; CHECK-GI-CVT-NEXT:    ret
4143;
4144; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i16:
4145; CHECK-GI-FP16:       // %bb.0:
4146; CHECK-GI-FP16-NEXT:    fcvtzu v0.8h, v0.8h
4147; CHECK-GI-FP16-NEXT:    fcvtzu v1.8h, v1.8h
4148; CHECK-GI-FP16-NEXT:    ret
4149    %x = call <16 x i16> @llvm.fptoui.sat.v16f16.v16i16(<16 x half> %f)
4150    ret <16 x i16> %x
4151}
4152
4153define <8 x i8> @test_unsigned_v8f64_v8i8(<8 x double> %f) {
4154; CHECK-SD-LABEL: test_unsigned_v8f64_v8i8:
4155; CHECK-SD:       // %bb.0:
4156; CHECK-SD-NEXT:    mov d4, v3.d[1]
4157; CHECK-SD-NEXT:    mov d5, v2.d[1]
4158; CHECK-SD-NEXT:    mov w11, #255 // =0xff
4159; CHECK-SD-NEXT:    fcvtzu w9, d3
4160; CHECK-SD-NEXT:    mov d3, v1.d[1]
4161; CHECK-SD-NEXT:    fcvtzu w12, d2
4162; CHECK-SD-NEXT:    fcvtzu w14, d1
4163; CHECK-SD-NEXT:    fcvtzu w8, d4
4164; CHECK-SD-NEXT:    mov d4, v0.d[1]
4165; CHECK-SD-NEXT:    fcvtzu w10, d5
4166; CHECK-SD-NEXT:    fcvtzu w13, d3
4167; CHECK-SD-NEXT:    cmp w8, #255
4168; CHECK-SD-NEXT:    fcvtzu w15, d4
4169; CHECK-SD-NEXT:    csel w8, w8, w11, lo
4170; CHECK-SD-NEXT:    cmp w9, #255
4171; CHECK-SD-NEXT:    csel w9, w9, w11, lo
4172; CHECK-SD-NEXT:    cmp w10, #255
4173; CHECK-SD-NEXT:    fmov s4, w9
4174; CHECK-SD-NEXT:    csel w9, w10, w11, lo
4175; CHECK-SD-NEXT:    cmp w12, #255
4176; CHECK-SD-NEXT:    fcvtzu w10, d0
4177; CHECK-SD-NEXT:    mov v4.s[1], w8
4178; CHECK-SD-NEXT:    csel w8, w12, w11, lo
4179; CHECK-SD-NEXT:    cmp w13, #255
4180; CHECK-SD-NEXT:    fmov s3, w8
4181; CHECK-SD-NEXT:    csel w8, w13, w11, lo
4182; CHECK-SD-NEXT:    cmp w14, #255
4183; CHECK-SD-NEXT:    mov v3.s[1], w9
4184; CHECK-SD-NEXT:    csel w9, w14, w11, lo
4185; CHECK-SD-NEXT:    cmp w15, #255
4186; CHECK-SD-NEXT:    fmov s2, w9
4187; CHECK-SD-NEXT:    csel w9, w15, w11, lo
4188; CHECK-SD-NEXT:    cmp w10, #255
4189; CHECK-SD-NEXT:    mov v2.s[1], w8
4190; CHECK-SD-NEXT:    csel w8, w10, w11, lo
4191; CHECK-SD-NEXT:    fmov s1, w8
4192; CHECK-SD-NEXT:    adrp x8, .LCPI82_0
4193; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI82_0]
4194; CHECK-SD-NEXT:    mov v1.s[1], w9
4195; CHECK-SD-NEXT:    tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.8b
4196; CHECK-SD-NEXT:    ret
4197;
4198; CHECK-GI-LABEL: test_unsigned_v8f64_v8i8:
4199; CHECK-GI:       // %bb.0:
4200; CHECK-GI-NEXT:    movi v4.2d, #0x000000000000ff
4201; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
4202; CHECK-GI-NEXT:    fcvtzu v1.2d, v1.2d
4203; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
4204; CHECK-GI-NEXT:    fcvtzu v3.2d, v3.2d
4205; CHECK-GI-NEXT:    cmhi v5.2d, v4.2d, v0.2d
4206; CHECK-GI-NEXT:    cmhi v6.2d, v4.2d, v1.2d
4207; CHECK-GI-NEXT:    cmhi v7.2d, v4.2d, v2.2d
4208; CHECK-GI-NEXT:    cmhi v16.2d, v4.2d, v3.2d
4209; CHECK-GI-NEXT:    bif v0.16b, v4.16b, v5.16b
4210; CHECK-GI-NEXT:    bif v1.16b, v4.16b, v6.16b
4211; CHECK-GI-NEXT:    bif v2.16b, v4.16b, v7.16b
4212; CHECK-GI-NEXT:    bif v3.16b, v4.16b, v16.16b
4213; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
4214; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
4215; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4216; CHECK-GI-NEXT:    xtn v0.8b, v0.8h
4217; CHECK-GI-NEXT:    ret
4218    %x = call <8 x i8> @llvm.fptoui.sat.v8f64.v8i8(<8 x double> %f)
4219    ret <8 x i8> %x
4220}
4221
4222define <16 x i8> @test_unsigned_v16f64_v16i8(<16 x double> %f) {
4223; CHECK-SD-LABEL: test_unsigned_v16f64_v16i8:
4224; CHECK-SD:       // %bb.0:
4225; CHECK-SD-NEXT:    mov d16, v0.d[1]
4226; CHECK-SD-NEXT:    fcvtzu w10, d0
4227; CHECK-SD-NEXT:    mov w8, #255 // =0xff
4228; CHECK-SD-NEXT:    fcvtzu w9, d16
4229; CHECK-SD-NEXT:    mov d16, v1.d[1]
4230; CHECK-SD-NEXT:    cmp w9, #255
4231; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4232; CHECK-SD-NEXT:    cmp w10, #255
4233; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4234; CHECK-SD-NEXT:    fmov s0, w10
4235; CHECK-SD-NEXT:    fcvtzu w10, d16
4236; CHECK-SD-NEXT:    mov d16, v2.d[1]
4237; CHECK-SD-NEXT:    mov v0.s[1], w9
4238; CHECK-SD-NEXT:    fcvtzu w9, d1
4239; CHECK-SD-NEXT:    cmp w10, #255
4240; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4241; CHECK-SD-NEXT:    cmp w9, #255
4242; CHECK-SD-NEXT:    mov w11, v0.s[1]
4243; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4244; CHECK-SD-NEXT:    fmov s1, w9
4245; CHECK-SD-NEXT:    fcvtzu w9, d16
4246; CHECK-SD-NEXT:    mov d16, v3.d[1]
4247; CHECK-SD-NEXT:    mov v0.b[1], w11
4248; CHECK-SD-NEXT:    mov v1.s[1], w10
4249; CHECK-SD-NEXT:    fcvtzu w10, d2
4250; CHECK-SD-NEXT:    cmp w9, #255
4251; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4252; CHECK-SD-NEXT:    cmp w10, #255
4253; CHECK-SD-NEXT:    mov w11, v1.s[1]
4254; CHECK-SD-NEXT:    mov v0.b[2], v1.b[0]
4255; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4256; CHECK-SD-NEXT:    fmov s2, w10
4257; CHECK-SD-NEXT:    fcvtzu w10, d16
4258; CHECK-SD-NEXT:    mov d16, v4.d[1]
4259; CHECK-SD-NEXT:    mov v0.b[3], w11
4260; CHECK-SD-NEXT:    mov v2.s[1], w9
4261; CHECK-SD-NEXT:    fcvtzu w9, d3
4262; CHECK-SD-NEXT:    cmp w10, #255
4263; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4264; CHECK-SD-NEXT:    cmp w9, #255
4265; CHECK-SD-NEXT:    mov w11, v2.s[1]
4266; CHECK-SD-NEXT:    mov v0.b[4], v2.b[0]
4267; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4268; CHECK-SD-NEXT:    fmov s3, w9
4269; CHECK-SD-NEXT:    fcvtzu w9, d16
4270; CHECK-SD-NEXT:    mov d16, v5.d[1]
4271; CHECK-SD-NEXT:    mov v0.b[5], w11
4272; CHECK-SD-NEXT:    mov v3.s[1], w10
4273; CHECK-SD-NEXT:    fcvtzu w10, d4
4274; CHECK-SD-NEXT:    cmp w9, #255
4275; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4276; CHECK-SD-NEXT:    cmp w10, #255
4277; CHECK-SD-NEXT:    mov w11, v3.s[1]
4278; CHECK-SD-NEXT:    mov v0.b[6], v3.b[0]
4279; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4280; CHECK-SD-NEXT:    fmov s4, w10
4281; CHECK-SD-NEXT:    fcvtzu w10, d16
4282; CHECK-SD-NEXT:    mov v0.b[7], w11
4283; CHECK-SD-NEXT:    mov v4.s[1], w9
4284; CHECK-SD-NEXT:    fcvtzu w9, d5
4285; CHECK-SD-NEXT:    mov d5, v6.d[1]
4286; CHECK-SD-NEXT:    cmp w10, #255
4287; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4288; CHECK-SD-NEXT:    cmp w9, #255
4289; CHECK-SD-NEXT:    mov w11, v4.s[1]
4290; CHECK-SD-NEXT:    mov v0.b[8], v4.b[0]
4291; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4292; CHECK-SD-NEXT:    fmov s16, w9
4293; CHECK-SD-NEXT:    fcvtzu w9, d5
4294; CHECK-SD-NEXT:    mov d5, v7.d[1]
4295; CHECK-SD-NEXT:    mov v0.b[9], w11
4296; CHECK-SD-NEXT:    mov v16.s[1], w10
4297; CHECK-SD-NEXT:    fcvtzu w10, d6
4298; CHECK-SD-NEXT:    cmp w9, #255
4299; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4300; CHECK-SD-NEXT:    cmp w10, #255
4301; CHECK-SD-NEXT:    mov v0.b[10], v16.b[0]
4302; CHECK-SD-NEXT:    mov w11, v16.s[1]
4303; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4304; CHECK-SD-NEXT:    fmov s6, w10
4305; CHECK-SD-NEXT:    fcvtzu w10, d7
4306; CHECK-SD-NEXT:    mov v0.b[11], w11
4307; CHECK-SD-NEXT:    mov v6.s[1], w9
4308; CHECK-SD-NEXT:    fcvtzu w9, d5
4309; CHECK-SD-NEXT:    cmp w9, #255
4310; CHECK-SD-NEXT:    mov v0.b[12], v6.b[0]
4311; CHECK-SD-NEXT:    mov w11, v6.s[1]
4312; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4313; CHECK-SD-NEXT:    cmp w10, #255
4314; CHECK-SD-NEXT:    csel w8, w10, w8, lo
4315; CHECK-SD-NEXT:    fmov s5, w8
4316; CHECK-SD-NEXT:    mov v0.b[13], w11
4317; CHECK-SD-NEXT:    mov v5.s[1], w9
4318; CHECK-SD-NEXT:    mov v0.b[14], v5.b[0]
4319; CHECK-SD-NEXT:    mov w8, v5.s[1]
4320; CHECK-SD-NEXT:    mov v0.b[15], w8
4321; CHECK-SD-NEXT:    ret
4322;
4323; CHECK-GI-LABEL: test_unsigned_v16f64_v16i8:
4324; CHECK-GI:       // %bb.0:
4325; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
4326; CHECK-GI-NEXT:    fcvtzu v1.2d, v1.2d
4327; CHECK-GI-NEXT:    movi v16.2d, #0x000000000000ff
4328; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
4329; CHECK-GI-NEXT:    fcvtzu v3.2d, v3.2d
4330; CHECK-GI-NEXT:    fcvtzu v4.2d, v4.2d
4331; CHECK-GI-NEXT:    fcvtzu v5.2d, v5.2d
4332; CHECK-GI-NEXT:    fcvtzu v6.2d, v6.2d
4333; CHECK-GI-NEXT:    fcvtzu v7.2d, v7.2d
4334; CHECK-GI-NEXT:    cmhi v17.2d, v16.2d, v0.2d
4335; CHECK-GI-NEXT:    cmhi v18.2d, v16.2d, v1.2d
4336; CHECK-GI-NEXT:    cmhi v19.2d, v16.2d, v2.2d
4337; CHECK-GI-NEXT:    cmhi v20.2d, v16.2d, v3.2d
4338; CHECK-GI-NEXT:    cmhi v21.2d, v16.2d, v4.2d
4339; CHECK-GI-NEXT:    cmhi v22.2d, v16.2d, v5.2d
4340; CHECK-GI-NEXT:    cmhi v23.2d, v16.2d, v6.2d
4341; CHECK-GI-NEXT:    cmhi v24.2d, v16.2d, v7.2d
4342; CHECK-GI-NEXT:    bif v0.16b, v16.16b, v17.16b
4343; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v18.16b
4344; CHECK-GI-NEXT:    bif v2.16b, v16.16b, v19.16b
4345; CHECK-GI-NEXT:    bif v3.16b, v16.16b, v20.16b
4346; CHECK-GI-NEXT:    bif v4.16b, v16.16b, v21.16b
4347; CHECK-GI-NEXT:    bif v5.16b, v16.16b, v22.16b
4348; CHECK-GI-NEXT:    bif v6.16b, v16.16b, v23.16b
4349; CHECK-GI-NEXT:    bif v7.16b, v16.16b, v24.16b
4350; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
4351; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
4352; CHECK-GI-NEXT:    uzp1 v2.4s, v4.4s, v5.4s
4353; CHECK-GI-NEXT:    uzp1 v3.4s, v6.4s, v7.4s
4354; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4355; CHECK-GI-NEXT:    uzp1 v1.8h, v2.8h, v3.8h
4356; CHECK-GI-NEXT:    uzp1 v0.16b, v0.16b, v1.16b
4357; CHECK-GI-NEXT:    ret
4358    %x = call <16 x i8> @llvm.fptoui.sat.v16f64.v16i8(<16 x double> %f)
4359    ret <16 x i8> %x
4360}
4361
4362define <8 x i16> @test_unsigned_v8f64_v8i16(<8 x double> %f) {
4363; CHECK-SD-LABEL: test_unsigned_v8f64_v8i16:
4364; CHECK-SD:       // %bb.0:
4365; CHECK-SD-NEXT:    mov d4, v3.d[1]
4366; CHECK-SD-NEXT:    mov d5, v2.d[1]
4367; CHECK-SD-NEXT:    mov w10, #65535 // =0xffff
4368; CHECK-SD-NEXT:    fcvtzu w9, d3
4369; CHECK-SD-NEXT:    mov d3, v1.d[1]
4370; CHECK-SD-NEXT:    fcvtzu w12, d2
4371; CHECK-SD-NEXT:    fcvtzu w14, d1
4372; CHECK-SD-NEXT:    fcvtzu w8, d4
4373; CHECK-SD-NEXT:    mov d4, v0.d[1]
4374; CHECK-SD-NEXT:    fcvtzu w11, d5
4375; CHECK-SD-NEXT:    fcvtzu w13, d3
4376; CHECK-SD-NEXT:    cmp w8, w10
4377; CHECK-SD-NEXT:    fcvtzu w15, d4
4378; CHECK-SD-NEXT:    csel w8, w8, w10, lo
4379; CHECK-SD-NEXT:    cmp w9, w10
4380; CHECK-SD-NEXT:    csel w9, w9, w10, lo
4381; CHECK-SD-NEXT:    cmp w11, w10
4382; CHECK-SD-NEXT:    fmov s4, w9
4383; CHECK-SD-NEXT:    csel w9, w11, w10, lo
4384; CHECK-SD-NEXT:    cmp w12, w10
4385; CHECK-SD-NEXT:    fcvtzu w11, d0
4386; CHECK-SD-NEXT:    mov v4.s[1], w8
4387; CHECK-SD-NEXT:    csel w8, w12, w10, lo
4388; CHECK-SD-NEXT:    cmp w13, w10
4389; CHECK-SD-NEXT:    fmov s3, w8
4390; CHECK-SD-NEXT:    csel w8, w13, w10, lo
4391; CHECK-SD-NEXT:    cmp w14, w10
4392; CHECK-SD-NEXT:    mov v3.s[1], w9
4393; CHECK-SD-NEXT:    csel w9, w14, w10, lo
4394; CHECK-SD-NEXT:    cmp w15, w10
4395; CHECK-SD-NEXT:    fmov s2, w9
4396; CHECK-SD-NEXT:    csel w9, w15, w10, lo
4397; CHECK-SD-NEXT:    cmp w11, w10
4398; CHECK-SD-NEXT:    mov v2.s[1], w8
4399; CHECK-SD-NEXT:    csel w8, w11, w10, lo
4400; CHECK-SD-NEXT:    fmov s1, w8
4401; CHECK-SD-NEXT:    adrp x8, .LCPI84_0
4402; CHECK-SD-NEXT:    ldr q0, [x8, :lo12:.LCPI84_0]
4403; CHECK-SD-NEXT:    mov v1.s[1], w9
4404; CHECK-SD-NEXT:    tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v0.16b
4405; CHECK-SD-NEXT:    ret
4406;
4407; CHECK-GI-LABEL: test_unsigned_v8f64_v8i16:
4408; CHECK-GI:       // %bb.0:
4409; CHECK-GI-NEXT:    movi v4.2d, #0x0000000000ffff
4410; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
4411; CHECK-GI-NEXT:    fcvtzu v1.2d, v1.2d
4412; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
4413; CHECK-GI-NEXT:    fcvtzu v3.2d, v3.2d
4414; CHECK-GI-NEXT:    cmhi v5.2d, v4.2d, v0.2d
4415; CHECK-GI-NEXT:    cmhi v6.2d, v4.2d, v1.2d
4416; CHECK-GI-NEXT:    cmhi v7.2d, v4.2d, v2.2d
4417; CHECK-GI-NEXT:    cmhi v16.2d, v4.2d, v3.2d
4418; CHECK-GI-NEXT:    bif v0.16b, v4.16b, v5.16b
4419; CHECK-GI-NEXT:    bif v1.16b, v4.16b, v6.16b
4420; CHECK-GI-NEXT:    bif v2.16b, v4.16b, v7.16b
4421; CHECK-GI-NEXT:    bif v3.16b, v4.16b, v16.16b
4422; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
4423; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
4424; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4425; CHECK-GI-NEXT:    ret
4426    %x = call <8 x i16> @llvm.fptoui.sat.v8f64.v8i16(<8 x double> %f)
4427    ret <8 x i16> %x
4428}
4429
4430define <16 x i16> @test_unsigned_v16f64_v16i16(<16 x double> %f) {
4431; CHECK-SD-LABEL: test_unsigned_v16f64_v16i16:
4432; CHECK-SD:       // %bb.0:
4433; CHECK-SD-NEXT:    mov d16, v3.d[1]
4434; CHECK-SD-NEXT:    mov d17, v2.d[1]
4435; CHECK-SD-NEXT:    mov w8, #65535 // =0xffff
4436; CHECK-SD-NEXT:    fcvtzu w9, d3
4437; CHECK-SD-NEXT:    mov d3, v1.d[1]
4438; CHECK-SD-NEXT:    fcvtzu w10, d1
4439; CHECK-SD-NEXT:    mov d1, v0.d[1]
4440; CHECK-SD-NEXT:    fcvtzu w11, d2
4441; CHECK-SD-NEXT:    fcvtzu w12, d0
4442; CHECK-SD-NEXT:    mov d0, v7.d[1]
4443; CHECK-SD-NEXT:    mov d2, v6.d[1]
4444; CHECK-SD-NEXT:    fcvtzu w14, d7
4445; CHECK-SD-NEXT:    fcvtzu w13, d16
4446; CHECK-SD-NEXT:    fcvtzu w16, d17
4447; CHECK-SD-NEXT:    fcvtzu w15, d6
4448; CHECK-SD-NEXT:    fcvtzu w17, d3
4449; CHECK-SD-NEXT:    mov d6, v5.d[1]
4450; CHECK-SD-NEXT:    mov d3, v4.d[1]
4451; CHECK-SD-NEXT:    fcvtzu w18, d1
4452; CHECK-SD-NEXT:    cmp w13, w8
4453; CHECK-SD-NEXT:    csel w13, w13, w8, lo
4454; CHECK-SD-NEXT:    cmp w9, w8
4455; CHECK-SD-NEXT:    csel w9, w9, w8, lo
4456; CHECK-SD-NEXT:    cmp w16, w8
4457; CHECK-SD-NEXT:    fmov s19, w9
4458; CHECK-SD-NEXT:    csel w9, w16, w8, lo
4459; CHECK-SD-NEXT:    cmp w11, w8
4460; CHECK-SD-NEXT:    fcvtzu w16, d0
4461; CHECK-SD-NEXT:    csel w11, w11, w8, lo
4462; CHECK-SD-NEXT:    cmp w17, w8
4463; CHECK-SD-NEXT:    mov v19.s[1], w13
4464; CHECK-SD-NEXT:    csel w13, w17, w8, lo
4465; CHECK-SD-NEXT:    cmp w10, w8
4466; CHECK-SD-NEXT:    csel w10, w10, w8, lo
4467; CHECK-SD-NEXT:    cmp w18, w8
4468; CHECK-SD-NEXT:    fmov s18, w11
4469; CHECK-SD-NEXT:    csel w11, w18, w8, lo
4470; CHECK-SD-NEXT:    cmp w12, w8
4471; CHECK-SD-NEXT:    fcvtzu w17, d2
4472; CHECK-SD-NEXT:    csel w12, w12, w8, lo
4473; CHECK-SD-NEXT:    cmp w16, w8
4474; CHECK-SD-NEXT:    fcvtzu w18, d6
4475; CHECK-SD-NEXT:    mov v18.s[1], w9
4476; CHECK-SD-NEXT:    csel w9, w16, w8, lo
4477; CHECK-SD-NEXT:    cmp w14, w8
4478; CHECK-SD-NEXT:    fmov s17, w10
4479; CHECK-SD-NEXT:    csel w10, w14, w8, lo
4480; CHECK-SD-NEXT:    fcvtzu w16, d5
4481; CHECK-SD-NEXT:    fmov s23, w10
4482; CHECK-SD-NEXT:    cmp w17, w8
4483; CHECK-SD-NEXT:    fcvtzu w14, d3
4484; CHECK-SD-NEXT:    csel w10, w17, w8, lo
4485; CHECK-SD-NEXT:    cmp w15, w8
4486; CHECK-SD-NEXT:    fcvtzu w17, d4
4487; CHECK-SD-NEXT:    mov v17.s[1], w13
4488; CHECK-SD-NEXT:    mov v23.s[1], w9
4489; CHECK-SD-NEXT:    csel w9, w15, w8, lo
4490; CHECK-SD-NEXT:    cmp w18, w8
4491; CHECK-SD-NEXT:    fmov s22, w9
4492; CHECK-SD-NEXT:    csel w9, w18, w8, lo
4493; CHECK-SD-NEXT:    cmp w16, w8
4494; CHECK-SD-NEXT:    fmov s16, w12
4495; CHECK-SD-NEXT:    mov v22.s[1], w10
4496; CHECK-SD-NEXT:    csel w10, w16, w8, lo
4497; CHECK-SD-NEXT:    cmp w14, w8
4498; CHECK-SD-NEXT:    fmov s21, w10
4499; CHECK-SD-NEXT:    csel w10, w14, w8, lo
4500; CHECK-SD-NEXT:    cmp w17, w8
4501; CHECK-SD-NEXT:    csel w8, w17, w8, lo
4502; CHECK-SD-NEXT:    mov v16.s[1], w11
4503; CHECK-SD-NEXT:    mov v21.s[1], w9
4504; CHECK-SD-NEXT:    fmov s20, w8
4505; CHECK-SD-NEXT:    adrp x8, .LCPI85_0
4506; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI85_0]
4507; CHECK-SD-NEXT:    mov v20.s[1], w10
4508; CHECK-SD-NEXT:    tbl v0.16b, { v16.16b, v17.16b, v18.16b, v19.16b }, v1.16b
4509; CHECK-SD-NEXT:    tbl v1.16b, { v20.16b, v21.16b, v22.16b, v23.16b }, v1.16b
4510; CHECK-SD-NEXT:    ret
4511;
4512; CHECK-GI-LABEL: test_unsigned_v16f64_v16i16:
4513; CHECK-GI:       // %bb.0:
4514; CHECK-GI-NEXT:    fcvtzu v0.2d, v0.2d
4515; CHECK-GI-NEXT:    fcvtzu v1.2d, v1.2d
4516; CHECK-GI-NEXT:    movi v16.2d, #0x0000000000ffff
4517; CHECK-GI-NEXT:    fcvtzu v2.2d, v2.2d
4518; CHECK-GI-NEXT:    fcvtzu v3.2d, v3.2d
4519; CHECK-GI-NEXT:    fcvtzu v4.2d, v4.2d
4520; CHECK-GI-NEXT:    fcvtzu v5.2d, v5.2d
4521; CHECK-GI-NEXT:    fcvtzu v6.2d, v6.2d
4522; CHECK-GI-NEXT:    fcvtzu v7.2d, v7.2d
4523; CHECK-GI-NEXT:    cmhi v17.2d, v16.2d, v0.2d
4524; CHECK-GI-NEXT:    cmhi v18.2d, v16.2d, v1.2d
4525; CHECK-GI-NEXT:    cmhi v19.2d, v16.2d, v2.2d
4526; CHECK-GI-NEXT:    cmhi v20.2d, v16.2d, v3.2d
4527; CHECK-GI-NEXT:    cmhi v21.2d, v16.2d, v4.2d
4528; CHECK-GI-NEXT:    cmhi v22.2d, v16.2d, v5.2d
4529; CHECK-GI-NEXT:    cmhi v23.2d, v16.2d, v6.2d
4530; CHECK-GI-NEXT:    cmhi v24.2d, v16.2d, v7.2d
4531; CHECK-GI-NEXT:    bif v0.16b, v16.16b, v17.16b
4532; CHECK-GI-NEXT:    bif v1.16b, v16.16b, v18.16b
4533; CHECK-GI-NEXT:    bif v2.16b, v16.16b, v19.16b
4534; CHECK-GI-NEXT:    bif v3.16b, v16.16b, v20.16b
4535; CHECK-GI-NEXT:    bif v4.16b, v16.16b, v21.16b
4536; CHECK-GI-NEXT:    bif v5.16b, v16.16b, v22.16b
4537; CHECK-GI-NEXT:    bif v6.16b, v16.16b, v23.16b
4538; CHECK-GI-NEXT:    bif v7.16b, v16.16b, v24.16b
4539; CHECK-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
4540; CHECK-GI-NEXT:    uzp1 v1.4s, v2.4s, v3.4s
4541; CHECK-GI-NEXT:    uzp1 v2.4s, v4.4s, v5.4s
4542; CHECK-GI-NEXT:    uzp1 v3.4s, v6.4s, v7.4s
4543; CHECK-GI-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
4544; CHECK-GI-NEXT:    uzp1 v1.8h, v2.8h, v3.8h
4545; CHECK-GI-NEXT:    ret
4546    %x = call <16 x i16> @llvm.fptoui.sat.v16f64.v16i16(<16 x double> %f)
4547    ret <16 x i16> %x
4548}
4549