1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64 -mattr=+v8.2a,+fullfp16 | FileCheck %s 3 4declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half) 5declare i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half) 6declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half) 7declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half) 8declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half) 9declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half) 10declare i64 @llvm.aarch64.neon.fcvtns.i64.f16(half) 11declare i32 @llvm.aarch64.neon.fcvtns.i32.f16(half) 12declare i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half) 13declare i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half) 14declare i64 @llvm.aarch64.neon.fcvtms.i64.f16(half) 15declare i32 @llvm.aarch64.neon.fcvtms.i32.f16(half) 16declare i64 @llvm.aarch64.neon.fcvtau.i64.f16(half) 17declare i32 @llvm.aarch64.neon.fcvtau.i32.f16(half) 18declare i64 @llvm.aarch64.neon.fcvtas.i64.f16(half) 19declare i32 @llvm.aarch64.neon.fcvtas.i32.f16(half) 20declare i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half) 21declare i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half) 22declare i64 @llvm.aarch64.neon.fcvtzu.i64.f16(half) 23declare i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half) 24declare half @llvm.aarch64.neon.frsqrte.f16(half) 25declare half @llvm.aarch64.neon.frecpx.f16(half) 26declare half @llvm.aarch64.neon.frecpe.f16(half) 27 28define dso_local i16 @t2(half %a) { 29; CHECK-LABEL: t2: 30; CHECK: // %bb.0: // %entry 31; CHECK-NEXT: fcmp h0, #0.0 32; CHECK-NEXT: csetm w0, eq 33; CHECK-NEXT: ret 34entry: 35 %0 = fcmp oeq half %a, 0xH0000 36 %vceqz = sext i1 %0 to i16 37 ret i16 %vceqz 38} 39 40define dso_local i16 @t3(half %a) { 41; CHECK-LABEL: t3: 42; CHECK: // %bb.0: // %entry 43; CHECK-NEXT: fcmp h0, #0.0 44; CHECK-NEXT: csetm w0, ge 45; CHECK-NEXT: ret 46entry: 47 %0 = fcmp oge half %a, 0xH0000 48 %vcgez = sext i1 %0 to i16 49 ret i16 %vcgez 50} 51 52define dso_local i16 @t4(half %a) { 53; CHECK-LABEL: t4: 54; CHECK: // %bb.0: // %entry 55; CHECK-NEXT: fcmp h0, #0.0 56; CHECK-NEXT: csetm w0, gt 57; CHECK-NEXT: ret 58entry: 59 %0 = fcmp ogt half %a, 0xH0000 60 %vcgtz = sext i1 %0 to i16 61 ret i16 %vcgtz 62} 63 64define dso_local i16 @t5(half %a) { 65; CHECK-LABEL: t5: 66; CHECK: // %bb.0: // %entry 67; CHECK-NEXT: fcmp h0, #0.0 68; CHECK-NEXT: csetm w0, ls 69; CHECK-NEXT: ret 70entry: 71 %0 = fcmp ole half %a, 0xH0000 72 %vclez = sext i1 %0 to i16 73 ret i16 %vclez 74} 75 76define dso_local i16 @t6(half %a) { 77; CHECK-LABEL: t6: 78; CHECK: // %bb.0: // %entry 79; CHECK-NEXT: fcmp h0, #0.0 80; CHECK-NEXT: csetm w0, mi 81; CHECK-NEXT: ret 82entry: 83 %0 = fcmp olt half %a, 0xH0000 84 %vcltz = sext i1 %0 to i16 85 ret i16 %vcltz 86} 87 88define dso_local half @t8(i32 %a) { 89; CHECK-LABEL: t8: 90; CHECK: // %bb.0: // %entry 91; CHECK-NEXT: scvtf h0, w0 92; CHECK-NEXT: ret 93entry: 94 %0 = sitofp i32 %a to half 95 ret half %0 96} 97 98define dso_local half @t9(i64 %a) { 99; CHECK-LABEL: t9: 100; CHECK: // %bb.0: // %entry 101; CHECK-NEXT: scvtf h0, x0 102; CHECK-NEXT: ret 103entry: 104 %0 = sitofp i64 %a to half 105 ret half %0 106} 107 108define dso_local half @t12(i64 %a) { 109; CHECK-LABEL: t12: 110; CHECK: // %bb.0: // %entry 111; CHECK-NEXT: ucvtf h0, x0 112; CHECK-NEXT: ret 113entry: 114 %0 = uitofp i64 %a to half 115 ret half %0 116} 117 118define dso_local i16 @t13(half %a) { 119; CHECK-LABEL: t13: 120; CHECK: // %bb.0: // %entry 121; CHECK-NEXT: fcvtzs w0, h0 122; CHECK-NEXT: ret 123entry: 124 %0 = fptosi half %a to i16 125 ret i16 %0 126} 127 128define dso_local i64 @t15(half %a) { 129; CHECK-LABEL: t15: 130; CHECK: // %bb.0: // %entry 131; CHECK-NEXT: fcvtzs x0, h0 132; CHECK-NEXT: ret 133entry: 134 %0 = fptosi half %a to i64 135 ret i64 %0 136} 137 138define dso_local i16 @t16(half %a) { 139; CHECK-LABEL: t16: 140; CHECK: // %bb.0: // %entry 141; CHECK-NEXT: fcvtzs w0, h0 142; CHECK-NEXT: ret 143entry: 144 %0 = fptoui half %a to i16 145 ret i16 %0 146} 147 148define dso_local i64 @t18(half %a) { 149; CHECK-LABEL: t18: 150; CHECK: // %bb.0: // %entry 151; CHECK-NEXT: fcvtzu x0, h0 152; CHECK-NEXT: ret 153entry: 154 %0 = fptoui half %a to i64 155 ret i64 %0 156} 157 158define i32 @fcvtzu_intrinsic_i32(half %a) { 159; CHECK-LABEL: fcvtzu_intrinsic_i32: 160; CHECK: // %bb.0: // %entry 161; CHECK-NEXT: fcvtzu w0, h0 162; CHECK-NEXT: ret 163entry: 164 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half %a) 165 ret i32 %fcvt 166} 167 168define i64 @fcvtzu_intrinsic_i64(half %a) { 169; CHECK-LABEL: fcvtzu_intrinsic_i64: 170; CHECK: // %bb.0: // %entry 171; CHECK-NEXT: fcvtzs x0, h0 172; CHECK-NEXT: ret 173entry: 174 %fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a) 175 ret i64 %fcvt 176} 177 178define i32 @fcvtzs_intrinsic_i32(half %a) { 179; CHECK-LABEL: fcvtzs_intrinsic_i32: 180; CHECK: // %bb.0: // %entry 181; CHECK-NEXT: fcvtzs w0, h0 182; CHECK-NEXT: ret 183entry: 184 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a) 185 ret i32 %fcvt 186} 187 188define i64 @fcvtzs_intrinsic_i64(half %a) { 189; CHECK-LABEL: fcvtzs_intrinsic_i64: 190; CHECK: // %bb.0: // %entry 191; CHECK-NEXT: fcvtzs x0, h0 192; CHECK-NEXT: ret 193entry: 194 %fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a) 195 ret i64 %fcvt 196} 197 198define dso_local i16 @t19(half %a) { 199; CHECK-LABEL: t19: 200; CHECK: // %bb.0: // %entry 201; CHECK-NEXT: fcvtas w0, h0 202; CHECK-NEXT: ret 203entry: 204 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a) 205 %0 = trunc i32 %fcvt to i16 206 ret i16 %0 207} 208 209define dso_local i64 @t21(half %a) { 210; CHECK-LABEL: t21: 211; CHECK: // %bb.0: // %entry 212; CHECK-NEXT: fcvtas x0, h0 213; CHECK-NEXT: ret 214entry: 215 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a) 216 ret i64 %vcvtah_s64_f16 217} 218 219define dso_local i16 @t22(half %a) { 220; CHECK-LABEL: t22: 221; CHECK: // %bb.0: // %entry 222; CHECK-NEXT: fcvtau w0, h0 223; CHECK-NEXT: ret 224entry: 225 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a) 226 %0 = trunc i32 %fcvt to i16 227 ret i16 %0 228} 229 230define dso_local i64 @t24(half %a) { 231; CHECK-LABEL: t24: 232; CHECK: // %bb.0: // %entry 233; CHECK-NEXT: fcvtau x0, h0 234; CHECK-NEXT: ret 235entry: 236 %vcvtah_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a) 237 ret i64 %vcvtah_u64_f16 238} 239 240define dso_local i16 @t25(half %a) { 241; CHECK-LABEL: t25: 242; CHECK: // %bb.0: // %entry 243; CHECK-NEXT: fcvtms w0, h0 244; CHECK-NEXT: ret 245entry: 246 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a) 247 %0 = trunc i32 %fcvt to i16 248 ret i16 %0 249} 250 251define dso_local i64 @t27(half %a) { 252; CHECK-LABEL: t27: 253; CHECK: // %bb.0: // %entry 254; CHECK-NEXT: fcvtms x0, h0 255; CHECK-NEXT: ret 256entry: 257 %vcvtmh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a) 258 ret i64 %vcvtmh_s64_f16 259} 260 261define dso_local i16 @t28(half %a) { 262; CHECK-LABEL: t28: 263; CHECK: // %bb.0: // %entry 264; CHECK-NEXT: fcvtmu w0, h0 265; CHECK-NEXT: ret 266entry: 267 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a) 268 %0 = trunc i32 %fcvt to i16 269 ret i16 %0 270} 271 272define dso_local i64 @t30(half %a) { 273; CHECK-LABEL: t30: 274; CHECK: // %bb.0: // %entry 275; CHECK-NEXT: fcvtmu x0, h0 276; CHECK-NEXT: ret 277entry: 278 %vcvtmh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a) 279 ret i64 %vcvtmh_u64_f16 280} 281 282define dso_local i16 @t31(half %a) { 283; CHECK-LABEL: t31: 284; CHECK: // %bb.0: // %entry 285; CHECK-NEXT: fcvtns w0, h0 286; CHECK-NEXT: ret 287entry: 288 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a) 289 %0 = trunc i32 %fcvt to i16 290 ret i16 %0 291} 292 293define dso_local i64 @t33(half %a) { 294; CHECK-LABEL: t33: 295; CHECK: // %bb.0: // %entry 296; CHECK-NEXT: fcvtns x0, h0 297; CHECK-NEXT: ret 298entry: 299 %vcvtnh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a) 300 ret i64 %vcvtnh_s64_f16 301} 302 303define dso_local i16 @t34(half %a) { 304; CHECK-LABEL: t34: 305; CHECK: // %bb.0: // %entry 306; CHECK-NEXT: fcvtnu w0, h0 307; CHECK-NEXT: ret 308entry: 309 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a) 310 %0 = trunc i32 %fcvt to i16 311 ret i16 %0 312} 313 314define dso_local i64 @t36(half %a) { 315; CHECK-LABEL: t36: 316; CHECK: // %bb.0: // %entry 317; CHECK-NEXT: fcvtnu x0, h0 318; CHECK-NEXT: ret 319entry: 320 %vcvtnh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a) 321 ret i64 %vcvtnh_u64_f16 322} 323 324define dso_local i16 @t37(half %a) { 325; CHECK-LABEL: t37: 326; CHECK: // %bb.0: // %entry 327; CHECK-NEXT: fcvtps w0, h0 328; CHECK-NEXT: ret 329entry: 330 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a) 331 %0 = trunc i32 %fcvt to i16 332 ret i16 %0 333} 334 335define dso_local i64 @t39(half %a) { 336; CHECK-LABEL: t39: 337; CHECK: // %bb.0: // %entry 338; CHECK-NEXT: fcvtps x0, h0 339; CHECK-NEXT: ret 340entry: 341 %vcvtph_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a) 342 ret i64 %vcvtph_s64_f16 343} 344 345define dso_local i16 @t40(half %a) { 346; CHECK-LABEL: t40: 347; CHECK: // %bb.0: // %entry 348; CHECK-NEXT: fcvtpu w0, h0 349; CHECK-NEXT: ret 350entry: 351 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half %a) 352 %0 = trunc i32 %fcvt to i16 353 ret i16 %0 354} 355 356define dso_local i64 @t42(half %a) { 357; CHECK-LABEL: t42: 358; CHECK: // %bb.0: // %entry 359; CHECK-NEXT: fcvtpu x0, h0 360; CHECK-NEXT: ret 361entry: 362 %vcvtph_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a) 363 ret i64 %vcvtph_u64_f16 364} 365 366define dso_local half @t44(half %a) { 367; CHECK-LABEL: t44: 368; CHECK: // %bb.0: // %entry 369; CHECK-NEXT: frecpe h0, h0 370; CHECK-NEXT: ret 371entry: 372 %vrecpeh_f16 = tail call half @llvm.aarch64.neon.frecpe.f16(half %a) 373 ret half %vrecpeh_f16 374} 375 376define dso_local half @t45(half %a) { 377; CHECK-LABEL: t45: 378; CHECK: // %bb.0: // %entry 379; CHECK-NEXT: frecpx h0, h0 380; CHECK-NEXT: ret 381entry: 382 %vrecpxh_f16 = tail call half @llvm.aarch64.neon.frecpx.f16(half %a) 383 ret half %vrecpxh_f16 384} 385 386define dso_local half @t53(half %a) { 387; CHECK-LABEL: t53: 388; CHECK: // %bb.0: // %entry 389; CHECK-NEXT: frsqrte h0, h0 390; CHECK-NEXT: ret 391entry: 392 %vrsqrteh_f16 = tail call half @llvm.aarch64.neon.frsqrte.f16(half %a) 393 ret half %vrsqrteh_f16 394} 395