1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s 3 4define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 { 5; CHECK-LABEL: v4f16_to_v4i16: 6; CHECK: // %bb.0: // %entry 7; CHECK-NEXT: fmov d0, d1 8; CHECK-NEXT: ret 9entry: 10 %1 = bitcast <4 x half> %a to <4 x i16> 11 ret <4 x i16> %1 12} 13 14define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 { 15; CHECK-LABEL: v4f16_to_v2i32: 16; CHECK: // %bb.0: // %entry 17; CHECK-NEXT: fmov d0, d1 18; CHECK-NEXT: ret 19entry: 20 %1 = bitcast <4 x half> %a to <2 x i32> 21 ret <2 x i32> %1 22} 23 24define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 { 25; CHECK-LABEL: v4f16_to_v1i64: 26; CHECK: // %bb.0: // %entry 27; CHECK-NEXT: fmov d0, d1 28; CHECK-NEXT: ret 29entry: 30 %1 = bitcast <4 x half> %a to <1 x i64> 31 ret <1 x i64> %1 32} 33 34define i64 @v4f16_to_i64(float, <4 x half> %a) #0 { 35; CHECK-LABEL: v4f16_to_i64: 36; CHECK: // %bb.0: // %entry 37; CHECK-NEXT: fmov x0, d1 38; CHECK-NEXT: ret 39entry: 40 %1 = bitcast <4 x half> %a to i64 41 ret i64 %1 42} 43 44define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 { 45; CHECK-LABEL: v4f16_to_v2float: 46; CHECK: // %bb.0: // %entry 47; CHECK-NEXT: fmov d0, d1 48; CHECK-NEXT: ret 49entry: 50 %1 = bitcast <4 x half> %a to <2 x float> 51 ret <2 x float> %1 52} 53 54define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 { 55; CHECK-LABEL: v4f16_to_v1double: 56; CHECK: // %bb.0: // %entry 57; CHECK-NEXT: fmov d0, d1 58; CHECK-NEXT: ret 59entry: 60 %1 = bitcast <4 x half> %a to <1 x double> 61 ret <1 x double> %1 62} 63 64define double @v4f16_to_double(float, <4 x half> %a) #0 { 65; CHECK-LABEL: v4f16_to_double: 66; CHECK: // %bb.0: // %entry 67; CHECK-NEXT: fmov d0, d1 68; CHECK-NEXT: ret 69entry: 70 %1 = bitcast <4 x half> %a to double 71 ret double %1 72} 73 74 75define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 { 76; CHECK-LABEL: v4i16_to_v4f16: 77; CHECK: // %bb.0: // %entry 78; CHECK-NEXT: fmov d0, d1 79; CHECK-NEXT: ret 80entry: 81 %1 = bitcast <4 x i16> %a to <4 x half> 82 ret <4 x half> %1 83} 84 85define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 { 86; CHECK-LABEL: v2i32_to_v4f16: 87; CHECK: // %bb.0: // %entry 88; CHECK-NEXT: fmov d0, d1 89; CHECK-NEXT: ret 90entry: 91 %1 = bitcast <2 x i32> %a to <4 x half> 92 ret <4 x half> %1 93} 94 95define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 { 96; CHECK-LABEL: v1i64_to_v4f16: 97; CHECK: // %bb.0: // %entry 98; CHECK-NEXT: fmov d0, d1 99; CHECK-NEXT: ret 100entry: 101 %1 = bitcast <1 x i64> %a to <4 x half> 102 ret <4 x half> %1 103} 104 105define <4 x half> @i64_to_v4f16(float, i64 %a) #0 { 106; CHECK-LABEL: i64_to_v4f16: 107; CHECK: // %bb.0: // %entry 108; CHECK-NEXT: fmov d0, x0 109; CHECK-NEXT: ret 110entry: 111 %1 = bitcast i64 %a to <4 x half> 112 ret <4 x half> %1 113} 114 115define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 { 116; CHECK-LABEL: v2float_to_v4f16: 117; CHECK: // %bb.0: // %entry 118; CHECK-NEXT: fmov d0, d1 119; CHECK-NEXT: ret 120entry: 121 %1 = bitcast <2 x float> %a to <4 x half> 122 ret <4 x half> %1 123} 124 125define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 { 126; CHECK-LABEL: v1double_to_v4f16: 127; CHECK: // %bb.0: // %entry 128; CHECK-NEXT: fmov d0, d1 129; CHECK-NEXT: ret 130entry: 131 %1 = bitcast <1 x double> %a to <4 x half> 132 ret <4 x half> %1 133} 134 135define <4 x half> @double_to_v4f16(float, double %a) #0 { 136; CHECK-LABEL: double_to_v4f16: 137; CHECK: // %bb.0: // %entry 138; CHECK-NEXT: fmov d0, d1 139; CHECK-NEXT: ret 140entry: 141 %1 = bitcast double %a to <4 x half> 142 ret <4 x half> %1 143} 144 145 146 147 148 149 150 151 152 153 154define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 { 155; CHECK-LABEL: v8f16_to_v8i16: 156; CHECK: // %bb.0: // %entry 157; CHECK-NEXT: mov v0.16b, v1.16b 158; CHECK-NEXT: ret 159entry: 160 %1 = bitcast <8 x half> %a to <8 x i16> 161 ret <8 x i16> %1 162} 163 164define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 { 165; CHECK-LABEL: v8f16_to_v4i32: 166; CHECK: // %bb.0: // %entry 167; CHECK-NEXT: mov v0.16b, v1.16b 168; CHECK-NEXT: ret 169entry: 170 %1 = bitcast <8 x half> %a to <4 x i32> 171 ret <4 x i32> %1 172} 173 174define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 { 175; CHECK-LABEL: v8f16_to_v2i64: 176; CHECK: // %bb.0: // %entry 177; CHECK-NEXT: mov v0.16b, v1.16b 178; CHECK-NEXT: ret 179entry: 180 %1 = bitcast <8 x half> %a to <2 x i64> 181 ret <2 x i64> %1 182} 183 184define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 { 185; CHECK-LABEL: v8f16_to_v4float: 186; CHECK: // %bb.0: // %entry 187; CHECK-NEXT: mov v0.16b, v1.16b 188; CHECK-NEXT: ret 189entry: 190 %1 = bitcast <8 x half> %a to <4 x float> 191 ret <4 x float> %1 192} 193 194define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 { 195; CHECK-LABEL: v8f16_to_v2double: 196; CHECK: // %bb.0: // %entry 197; CHECK-NEXT: mov v0.16b, v1.16b 198; CHECK-NEXT: ret 199entry: 200 %1 = bitcast <8 x half> %a to <2 x double> 201 ret <2 x double> %1 202} 203 204define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 { 205; CHECK-LABEL: v8i16_to_v8f16: 206; CHECK: // %bb.0: // %entry 207; CHECK-NEXT: mov v0.16b, v1.16b 208; CHECK-NEXT: ret 209entry: 210 %1 = bitcast <8 x i16> %a to <8 x half> 211 ret <8 x half> %1 212} 213 214define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 { 215; CHECK-LABEL: v4i32_to_v8f16: 216; CHECK: // %bb.0: // %entry 217; CHECK-NEXT: mov v0.16b, v1.16b 218; CHECK-NEXT: ret 219entry: 220 %1 = bitcast <4 x i32> %a to <8 x half> 221 ret <8 x half> %1 222} 223 224define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 { 225; CHECK-LABEL: v2i64_to_v8f16: 226; CHECK: // %bb.0: // %entry 227; CHECK-NEXT: mov v0.16b, v1.16b 228; CHECK-NEXT: ret 229entry: 230 %1 = bitcast <2 x i64> %a to <8 x half> 231 ret <8 x half> %1 232} 233 234define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 { 235; CHECK-LABEL: v4float_to_v8f16: 236; CHECK: // %bb.0: // %entry 237; CHECK-NEXT: mov v0.16b, v1.16b 238; CHECK-NEXT: ret 239entry: 240 %1 = bitcast <4 x float> %a to <8 x half> 241 ret <8 x half> %1 242} 243 244define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 { 245; CHECK-LABEL: v2double_to_v8f16: 246; CHECK: // %bb.0: // %entry 247; CHECK-NEXT: mov v0.16b, v1.16b 248; CHECK-NEXT: ret 249entry: 250 %1 = bitcast <2 x double> %a to <8 x half> 251 ret <8 x half> %1 252} 253