1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc --disable-replace-with-vec-lib --vector-library=ArmPL < %s -o - | FileCheck --check-prefix=ARMPL %s 3; RUN: llc --disable-replace-with-vec-lib --vector-library=sleefgnuabi < %s -o - | FileCheck --check-prefix=SLEEF %s 4 5target triple = "aarch64-unknown-linux-gnu" 6 7define <2 x double> @frem_v2f64(<2 x double> %unused, <2 x double> %a, <2 x double> %b) #0 { 8; ARMPL-LABEL: frem_v2f64: 9; ARMPL: // %bb.0: 10; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 11; ARMPL-NEXT: .cfi_def_cfa_offset 16 12; ARMPL-NEXT: .cfi_offset w30, -16 13; ARMPL-NEXT: mov v0.16b, v1.16b 14; ARMPL-NEXT: mov v1.16b, v2.16b 15; ARMPL-NEXT: bl armpl_vfmodq_f64 16; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 17; ARMPL-NEXT: ret 18; 19; SLEEF-LABEL: frem_v2f64: 20; SLEEF: // %bb.0: 21; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 22; SLEEF-NEXT: .cfi_def_cfa_offset 16 23; SLEEF-NEXT: .cfi_offset w30, -16 24; SLEEF-NEXT: mov v0.16b, v1.16b 25; SLEEF-NEXT: mov v1.16b, v2.16b 26; SLEEF-NEXT: bl _ZGVnN2vv_fmod 27; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 28; SLEEF-NEXT: ret 29 %res = frem <2 x double> %a, %b 30 ret <2 x double> %res 31} 32 33define <4 x float> @frem_strict_v4f32(<4 x float> %unused, <4 x float> %a, <4 x float> %b) #1 { 34; ARMPL-LABEL: frem_strict_v4f32: 35; ARMPL: // %bb.0: 36; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 37; ARMPL-NEXT: .cfi_def_cfa_offset 16 38; ARMPL-NEXT: .cfi_offset w30, -16 39; ARMPL-NEXT: mov v0.16b, v1.16b 40; ARMPL-NEXT: mov v1.16b, v2.16b 41; ARMPL-NEXT: bl armpl_vfmodq_f32 42; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 43; ARMPL-NEXT: ret 44; 45; SLEEF-LABEL: frem_strict_v4f32: 46; SLEEF: // %bb.0: 47; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 48; SLEEF-NEXT: .cfi_def_cfa_offset 16 49; SLEEF-NEXT: .cfi_offset w30, -16 50; SLEEF-NEXT: mov v0.16b, v1.16b 51; SLEEF-NEXT: mov v1.16b, v2.16b 52; SLEEF-NEXT: bl _ZGVnN4vv_fmodf 53; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 54; SLEEF-NEXT: ret 55 %res = frem <4 x float> %a, %b 56 ret <4 x float> %res 57} 58 59define <vscale x 4 x float> @frem_nxv4f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { 60; ARMPL-LABEL: frem_nxv4f32: 61; ARMPL: // %bb.0: 62; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 63; ARMPL-NEXT: .cfi_def_cfa_offset 16 64; ARMPL-NEXT: .cfi_offset w30, -16 65; ARMPL-NEXT: mov z0.d, z1.d 66; ARMPL-NEXT: mov z1.d, z2.d 67; ARMPL-NEXT: ptrue p0.s 68; ARMPL-NEXT: bl armpl_svfmod_f32_x 69; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 70; ARMPL-NEXT: ret 71; 72; SLEEF-LABEL: frem_nxv4f32: 73; SLEEF: // %bb.0: 74; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 75; SLEEF-NEXT: .cfi_def_cfa_offset 16 76; SLEEF-NEXT: .cfi_offset w30, -16 77; SLEEF-NEXT: mov z0.d, z1.d 78; SLEEF-NEXT: mov z1.d, z2.d 79; SLEEF-NEXT: ptrue p0.s 80; SLEEF-NEXT: bl _ZGVsMxvv_fmodf 81; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 82; SLEEF-NEXT: ret 83 %res = frem <vscale x 4 x float> %a, %b 84 ret <vscale x 4 x float> %res 85} 86 87define <vscale x 2 x double> @frem_strict_nxv2f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #1 { 88; ARMPL-LABEL: frem_strict_nxv2f64: 89; ARMPL: // %bb.0: 90; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 91; ARMPL-NEXT: .cfi_def_cfa_offset 16 92; ARMPL-NEXT: .cfi_offset w30, -16 93; ARMPL-NEXT: mov z0.d, z1.d 94; ARMPL-NEXT: mov z1.d, z2.d 95; ARMPL-NEXT: ptrue p0.d 96; ARMPL-NEXT: bl armpl_svfmod_f64_x 97; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 98; ARMPL-NEXT: ret 99; 100; SLEEF-LABEL: frem_strict_nxv2f64: 101; SLEEF: // %bb.0: 102; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 103; SLEEF-NEXT: .cfi_def_cfa_offset 16 104; SLEEF-NEXT: .cfi_offset w30, -16 105; SLEEF-NEXT: mov z0.d, z1.d 106; SLEEF-NEXT: mov z1.d, z2.d 107; SLEEF-NEXT: ptrue p0.d 108; SLEEF-NEXT: bl _ZGVsMxvv_fmod 109; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 110; SLEEF-NEXT: ret 111 %res = frem <vscale x 2 x double> %a, %b 112 ret <vscale x 2 x double> %res 113} 114 115attributes #0 = { "target-features"="+sve" } 116attributes #1 = { "target-features"="+sve" strictfp } 117