xref: /llvm-project/llvm/test/CodeGen/AArch64/fnmul.ll (revision cc5f93bb49fd241b22f753065acafdbd3edf8a08)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -fp-contract=fast -verify-machineinstrs -global-isel=0 | FileCheck %s
3;RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 -verify-machineinstrs -global-isel=0 | FileCheck %s
4
5
6define half @fnmul16(half noundef %x, half noundef %y)  {
7; CHECK-LABEL: fnmul16:
8; CHECK:       // %bb.0: // %entry
9; CHECK-NEXT:    fnmul h0, h0, h1
10; CHECK-NEXT:    ret
11;
12entry:
13  %fneg = fneg fast half %x
14  %mul = fmul fast half %fneg, %y
15  ret half %mul
16}
17
18define float @fnmul32(float noundef %x, float noundef %y)  {
19; CHECK-LABEL: fnmul32:
20; CHECK:       // %bb.0: // %entry
21; CHECK-NEXT:    fnmul s0, s0, s1
22; CHECK-NEXT:    ret
23;
24entry:
25  %fneg = fneg float %x
26  %mul = fmul float %fneg, %y
27  ret float %mul
28}
29
30define double @fnmul64(double noundef %x, double noundef %y)  {
31; CHECK-LABEL: fnmul64:
32; CHECK:       // %bb.0: // %entry
33; CHECK-NEXT:    fnmul d0, d0, d1
34; CHECK-NEXT:    ret
35;
36entry:
37  %fneg = fneg fast double %x
38  %mul = fmul fast double %fneg, %y
39  ret double %mul
40}
41
42define half @fnmul16_2(half noundef %x, half noundef %y)  {
43; CHECK-LABEL: fnmul16_2:
44; CHECK:       // %bb.0: // %entry
45; CHECK-NEXT:    fnmul h0, h1, h0
46; CHECK-NEXT:    ret
47;
48entry:
49  %fneg = fneg fast half %y
50  %mul = fmul fast half %x, %fneg
51  ret half %mul
52}
53
54define float @fnmul32_2(float noundef %x, float noundef %y)  {
55; CHECK-LABEL: fnmul32_2:
56; CHECK:       // %bb.0: // %entry
57; CHECK-NEXT:    fnmul s0, s1, s0
58; CHECK-NEXT:    ret
59;
60entry:
61  %fneg = fneg fast float %y
62  %mul = fmul fast float %x, %fneg
63  ret float %mul
64}
65
66define double @fnmul64_2(double noundef %x, double noundef %y)  {
67; CHECK-LABEL: fnmul64_2:
68; CHECK:       // %bb.0: // %entry
69; CHECK-NEXT:    fnmul d0, d1, d0
70; CHECK-NEXT:    ret
71;
72entry:
73  %fneg = fneg double %y
74  %mul = fmul double %x, %fneg
75  ret double %mul
76}
77