1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs -o - %s | FileCheck %s 3 4; LLVM should be able to cope with multiple uses of the same flag-setting 5; instruction at different points of a routine. Either by rematerializing the 6; compare or by saving and restoring the flag register. 7 8declare void @bar() 9 10@var = global i32 0 11 12define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) { 13; CHECK-LABEL: test_multiflag: 14; CHECK: // %bb.0: 15; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill 16; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill 17; CHECK-NEXT: .cfi_def_cfa_offset 32 18; CHECK-NEXT: .cfi_offset w19, -8 19; CHECK-NEXT: .cfi_offset w20, -16 20; CHECK-NEXT: .cfi_offset w30, -32 21; CHECK-NEXT: adrp x8, :got:var 22; CHECK-NEXT: cmp w0, w1 23; CHECK-NEXT: mov w19, w1 24; CHECK-NEXT: ldr x8, [x8, :got_lo12:var] 25; CHECK-NEXT: cset w9, ne 26; CHECK-NEXT: mov w20, w0 27; CHECK-NEXT: str w9, [x8] 28; CHECK-NEXT: bl bar 29; CHECK-NEXT: cmp w20, w19 30; CHECK-NEXT: b.eq .LBB0_2 31; CHECK-NEXT: // %bb.1: // %iftrue 32; CHECK-NEXT: mov w0, #42 // =0x2a 33; CHECK-NEXT: b .LBB0_3 34; CHECK-NEXT: .LBB0_2: // %iffalse 35; CHECK-NEXT: mov w0, wzr 36; CHECK-NEXT: .LBB0_3: // %iftrue 37; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload 38; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload 39; CHECK-NEXT: ret 40 41 %test = icmp ne i32 %n, %m 42 43 %val = zext i1 %test to i32 44 45 46 store i32 %val, ptr @var 47 48 call void @bar() 49 50 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be 51 ; acceptable, but assuming the call preserves NZCV is not. 52 br i1 %test, label %iftrue, label %iffalse 53 54iftrue: 55 ret i32 42 56iffalse: 57 ret i32 0 58} 59