1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=arm64-eabi -mattr=fullfp16,sve | FileCheck %s 3 4define float @divf32_2(float %a) nounwind { 5; CHECK-LABEL: divf32_2: 6; CHECK: // %bb.0: 7; CHECK-NEXT: fmov s1, #0.50000000 8; CHECK-NEXT: fmul s0, s0, s1 9; CHECK-NEXT: ret 10 %r = fdiv float %a, 2.0 11 ret float %r 12} 13 14define float @divf32_2_arcp(float %a) nounwind { 15; CHECK-LABEL: divf32_2_arcp: 16; CHECK: // %bb.0: 17; CHECK-NEXT: fmov s1, #0.50000000 18; CHECK-NEXT: fmul s0, s0, s1 19; CHECK-NEXT: ret 20 %r = fdiv arcp float %a, 2.0 21 ret float %r 22} 23 24define float @divf32_p75(float %a) nounwind { 25; CHECK-LABEL: divf32_p75: 26; CHECK: // %bb.0: 27; CHECK-NEXT: fmov s1, #0.75000000 28; CHECK-NEXT: fdiv s0, s0, s1 29; CHECK-NEXT: ret 30 %r = fdiv float %a, 0.75 31 ret float %r 32} 33 34define float @divf32_p75_arcp(float %a) nounwind { 35; CHECK-LABEL: divf32_p75_arcp: 36; CHECK: // %bb.0: 37; CHECK-NEXT: mov w8, #43691 // =0xaaab 38; CHECK-NEXT: movk w8, #16298, lsl #16 39; CHECK-NEXT: fmov s1, w8 40; CHECK-NEXT: fmul s0, s0, s1 41; CHECK-NEXT: ret 42 %r = fdiv arcp float %a, 0.75 43 ret float %r 44} 45 46define half @divf16_2(half %a) nounwind { 47; CHECK-LABEL: divf16_2: 48; CHECK: // %bb.0: 49; CHECK-NEXT: fmov h1, #0.50000000 50; CHECK-NEXT: fmul h0, h0, h1 51; CHECK-NEXT: ret 52 %r = fdiv half %a, 2.0 53 ret half %r 54} 55 56define half @divf16_32768(half %a) nounwind { 57; CHECK-LABEL: divf16_32768: 58; CHECK: // %bb.0: 59; CHECK-NEXT: mov w8, #30720 // =0x7800 60; CHECK-NEXT: fmov h1, w8 61; CHECK-NEXT: fdiv h0, h0, h1 62; CHECK-NEXT: ret 63 %r = fdiv half %a, 32768.0 64 ret half %r 65} 66 67define half @divf16_32768_arcp(half %a) nounwind { 68; CHECK-LABEL: divf16_32768_arcp: 69; CHECK: // %bb.0: 70; CHECK-NEXT: mov w8, #30720 // =0x7800 71; CHECK-NEXT: fmov h1, w8 72; CHECK-NEXT: fdiv h0, h0, h1 73; CHECK-NEXT: ret 74 %r = fdiv arcp half %a, 32768.0 75 ret half %r 76} 77 78define double @divf64_2(double %a) nounwind { 79; CHECK-LABEL: divf64_2: 80; CHECK: // %bb.0: 81; CHECK-NEXT: fmov d1, #0.50000000 82; CHECK-NEXT: fmul d0, d0, d1 83; CHECK-NEXT: ret 84 %r = fdiv double %a, 2.0 85 ret double %r 86} 87 88define <4 x float> @divv4f32_2(<4 x float> %a) nounwind { 89; CHECK-LABEL: divv4f32_2: 90; CHECK: // %bb.0: 91; CHECK-NEXT: movi v1.4s, #63, lsl #24 92; CHECK-NEXT: fmul v0.4s, v0.4s, v1.4s 93; CHECK-NEXT: ret 94 %r = fdiv <4 x float> %a, <float 2.0, float 2.0, float 2.0, float 2.0> 95 ret <4 x float> %r 96} 97 98define <4 x float> @divv4f32_2_arcp(<4 x float> %a) nounwind { 99; CHECK-LABEL: divv4f32_2_arcp: 100; CHECK: // %bb.0: 101; CHECK-NEXT: movi v1.4s, #63, lsl #24 102; CHECK-NEXT: fmul v0.4s, v0.4s, v1.4s 103; CHECK-NEXT: ret 104 %r = fdiv arcp <4 x float> %a, <float 2.0, float 2.0, float 2.0, float 2.0> 105 ret <4 x float> %r 106} 107 108define <4 x float> @divv4f32_3(<4 x float> %a) nounwind { 109; CHECK-LABEL: divv4f32_3: 110; CHECK: // %bb.0: 111; CHECK-NEXT: fmov v1.4s, #3.00000000 112; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s 113; CHECK-NEXT: ret 114 %r = fdiv <4 x float> %a, <float 3.0, float 3.0, float 3.0, float 3.0> 115 ret <4 x float> %r 116} 117 118define <4 x float> @divv4f32_3_arcp(<4 x float> %a) nounwind { 119; CHECK-LABEL: divv4f32_3_arcp: 120; CHECK: // %bb.0: 121; CHECK-NEXT: mov w8, #43691 // =0xaaab 122; CHECK-NEXT: movk w8, #16042, lsl #16 123; CHECK-NEXT: dup v1.4s, w8 124; CHECK-NEXT: fmul v0.4s, v0.4s, v1.4s 125; CHECK-NEXT: ret 126 %r = fdiv arcp <4 x float> %a, <float 3.0, float 3.0, float 3.0, float 3.0> 127 ret <4 x float> %r 128} 129 130define <4 x float> @divv4f32_24816(<4 x float> %a) nounwind { 131; CHECK-LABEL: divv4f32_24816: 132; CHECK: // %bb.0: 133; CHECK-NEXT: adrp x8, .LCPI12_0 134; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0] 135; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s 136; CHECK-NEXT: ret 137 %r = fdiv <4 x float> %a, <float 2.0, float 4.0, float 8.0, float 16.0> 138 ret <4 x float> %r 139} 140 141define <vscale x 4 x float> @divnxv4f32_2(<vscale x 4 x float> %a) nounwind { 142; CHECK-LABEL: divnxv4f32_2: 143; CHECK: // %bb.0: 144; CHECK-NEXT: ptrue p0.s 145; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5 146; CHECK-NEXT: ret 147 %r = fdiv <vscale x 4 x float> %a, splat (float 2.0) 148 ret <vscale x 4 x float> %r 149} 150