1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s 3 4define zeroext i16 @asr_zext_i1_i16(i1 %b) { 5; CHECK-LABEL: asr_zext_i1_i16: 6; CHECK: ; %bb.0: 7; CHECK-NEXT: uxth w0, wzr 8; CHECK-NEXT: ret 9 %1 = zext i1 %b to i16 10 %2 = ashr i16 %1, 1 11 ret i16 %2 12} 13 14define signext i16 @asr_sext_i1_i16(i1 %b) { 15; CHECK-LABEL: asr_sext_i1_i16: 16; CHECK: ; %bb.0: 17; CHECK-NEXT: sbfx w8, w0, #0, #1 18; CHECK-NEXT: sxth w0, w8 19; CHECK-NEXT: ret 20 %1 = sext i1 %b to i16 21 %2 = ashr i16 %1, 1 22 ret i16 %2 23} 24 25define i32 @asr_zext_i1_i32(i1 %b) { 26; CHECK-LABEL: asr_zext_i1_i32: 27; CHECK: ; %bb.0: 28; CHECK-NEXT: mov w0, wzr 29; CHECK-NEXT: ret 30 %1 = zext i1 %b to i32 31 %2 = ashr i32 %1, 1 32 ret i32 %2 33} 34 35define i32 @asr_sext_i1_i32(i1 %b) { 36; CHECK-LABEL: asr_sext_i1_i32: 37; CHECK: ; %bb.0: 38; CHECK-NEXT: sbfx w0, w0, #0, #1 39; CHECK-NEXT: ret 40 %1 = sext i1 %b to i32 41 %2 = ashr i32 %1, 1 42 ret i32 %2 43} 44 45define i64 @asr_zext_i1_i64(i1 %b) { 46; CHECK-LABEL: asr_zext_i1_i64: 47; CHECK: ; %bb.0: 48; CHECK-NEXT: mov x0, xzr 49; CHECK-NEXT: ret 50 %1 = zext i1 %b to i64 51 %2 = ashr i64 %1, 1 52 ret i64 %2 53} 54 55define i64 @asr_sext_i1_i64(i1 %b) { 56; CHECK-LABEL: asr_sext_i1_i64: 57; CHECK: ; %bb.0: 58; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 59; CHECK-NEXT: sbfx x0, x0, #0, #1 60; CHECK-NEXT: ret 61 %1 = sext i1 %b to i64 62 %2 = ashr i64 %1, 1 63 ret i64 %2 64} 65 66define zeroext i16 @lsr_zext_i1_i16(i1 %b) { 67; CHECK-LABEL: lsr_zext_i1_i16: 68; CHECK: ; %bb.0: 69; CHECK-NEXT: uxth w0, wzr 70; CHECK-NEXT: ret 71 %1 = zext i1 %b to i16 72 %2 = lshr i16 %1, 1 73 ret i16 %2 74} 75 76define signext i16 @lsr_sext_i1_i16(i1 %b) { 77; CHECK-LABEL: lsr_sext_i1_i16: 78; CHECK: ; %bb.0: 79; CHECK-NEXT: sbfx w8, w0, #0, #1 80; CHECK-NEXT: ubfx w8, w8, #1, #15 81; CHECK-NEXT: sxth w0, w8 82; CHECK-NEXT: ret 83 %1 = sext i1 %b to i16 84 %2 = lshr i16 %1, 1 85 ret i16 %2 86} 87 88define i32 @lsr_zext_i1_i32(i1 %b) { 89; CHECK-LABEL: lsr_zext_i1_i32: 90; CHECK: ; %bb.0: 91; CHECK-NEXT: mov w0, wzr 92; CHECK-NEXT: ret 93 %1 = zext i1 %b to i32 94 %2 = lshr i32 %1, 1 95 ret i32 %2 96} 97 98define i32 @lsr_sext_i1_i32(i1 %b) { 99; CHECK-LABEL: lsr_sext_i1_i32: 100; CHECK: ; %bb.0: 101; CHECK-NEXT: sbfx w8, w0, #0, #1 102; CHECK-NEXT: lsr w0, w8, #1 103; CHECK-NEXT: ret 104 %1 = sext i1 %b to i32 105 %2 = lshr i32 %1, 1 106 ret i32 %2 107} 108 109define i64 @lsr_zext_i1_i64(i1 %b) { 110; CHECK-LABEL: lsr_zext_i1_i64: 111; CHECK: ; %bb.0: 112; CHECK-NEXT: mov x0, xzr 113; CHECK-NEXT: ret 114 %1 = zext i1 %b to i64 115 %2 = lshr i64 %1, 1 116 ret i64 %2 117} 118 119define zeroext i16 @lsl_zext_i1_i16(i1 %b) { 120; CHECK-LABEL: lsl_zext_i1_i16: 121; CHECK: ; %bb.0: 122; CHECK-NEXT: ubfiz w8, w0, #4, #1 123; CHECK-NEXT: uxth w0, w8 124; CHECK-NEXT: ret 125 %1 = zext i1 %b to i16 126 %2 = shl i16 %1, 4 127 ret i16 %2 128} 129 130define signext i16 @lsl_sext_i1_i16(i1 %b) { 131; CHECK-LABEL: lsl_sext_i1_i16: 132; CHECK: ; %bb.0: 133; CHECK-NEXT: sbfiz w8, w0, #4, #1 134; CHECK-NEXT: sxth w0, w8 135; CHECK-NEXT: ret 136 %1 = sext i1 %b to i16 137 %2 = shl i16 %1, 4 138 ret i16 %2 139} 140 141define i32 @lsl_zext_i1_i32(i1 %b) { 142; CHECK-LABEL: lsl_zext_i1_i32: 143; CHECK: ; %bb.0: 144; CHECK-NEXT: ubfiz w0, w0, #4, #1 145; CHECK-NEXT: ret 146 %1 = zext i1 %b to i32 147 %2 = shl i32 %1, 4 148 ret i32 %2 149} 150 151define i32 @lsl_sext_i1_i32(i1 %b) { 152; CHECK-LABEL: lsl_sext_i1_i32: 153; CHECK: ; %bb.0: 154; CHECK-NEXT: sbfiz w0, w0, #4, #1 155; CHECK-NEXT: ret 156 %1 = sext i1 %b to i32 157 %2 = shl i32 %1, 4 158 ret i32 %2 159} 160 161define i64 @lsl_zext_i1_i64(i1 %b) { 162; CHECK-LABEL: lsl_zext_i1_i64: 163; CHECK: ; %bb.0: 164; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 165; CHECK-NEXT: ubfiz x0, x0, #4, #1 166; CHECK-NEXT: ret 167 %1 = zext i1 %b to i64 168 %2 = shl i64 %1, 4 169 ret i64 %2 170} 171 172define i64 @lsl_sext_i1_i64(i1 %b) { 173; CHECK-LABEL: lsl_sext_i1_i64: 174; CHECK: ; %bb.0: 175; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 176; CHECK-NEXT: sbfiz x0, x0, #4, #1 177; CHECK-NEXT: ret 178 %1 = sext i1 %b to i64 179 %2 = shl i64 %1, 4 180 ret i64 %2 181} 182 183define zeroext i8 @lslv_i8(i8 %a, i8 %b) { 184; CHECK-LABEL: lslv_i8: 185; CHECK: ; %bb.0: 186; CHECK-NEXT: and w8, w1, #0xff 187; CHECK-NEXT: lsl w8, w0, w8 188; CHECK-NEXT: and w8, w8, #0xff 189; CHECK-NEXT: uxtb w0, w8 190; CHECK-NEXT: ret 191 %1 = shl i8 %a, %b 192 ret i8 %1 193} 194 195define zeroext i8 @lsl_i8(i8 %a) { 196; CHECK-LABEL: lsl_i8: 197; CHECK: ; %bb.0: 198; CHECK-NEXT: ubfiz w8, w0, #4, #4 199; CHECK-NEXT: uxtb w0, w8 200; CHECK-NEXT: ret 201 %1 = shl i8 %a, 4 202 ret i8 %1 203} 204 205define zeroext i16 @lsl_zext_i8_i16(i8 %b) { 206; CHECK-LABEL: lsl_zext_i8_i16: 207; CHECK: ; %bb.0: 208; CHECK-NEXT: ubfiz w8, w0, #4, #8 209; CHECK-NEXT: uxth w0, w8 210; CHECK-NEXT: ret 211 %1 = zext i8 %b to i16 212 %2 = shl i16 %1, 4 213 ret i16 %2 214} 215 216define signext i16 @lsl_sext_i8_i16(i8 %b) { 217; CHECK-LABEL: lsl_sext_i8_i16: 218; CHECK: ; %bb.0: 219; CHECK-NEXT: sbfiz w8, w0, #4, #8 220; CHECK-NEXT: sxth w0, w8 221; CHECK-NEXT: ret 222 %1 = sext i8 %b to i16 223 %2 = shl i16 %1, 4 224 ret i16 %2 225} 226 227define i32 @lsl_zext_i8_i32(i8 %b) { 228; CHECK-LABEL: lsl_zext_i8_i32: 229; CHECK: ; %bb.0: 230; CHECK-NEXT: ubfiz w0, w0, #4, #8 231; CHECK-NEXT: ret 232 %1 = zext i8 %b to i32 233 %2 = shl i32 %1, 4 234 ret i32 %2 235} 236 237define i32 @lsl_sext_i8_i32(i8 %b) { 238; CHECK-LABEL: lsl_sext_i8_i32: 239; CHECK: ; %bb.0: 240; CHECK-NEXT: sbfiz w0, w0, #4, #8 241; CHECK-NEXT: ret 242 %1 = sext i8 %b to i32 243 %2 = shl i32 %1, 4 244 ret i32 %2 245} 246 247define i64 @lsl_zext_i8_i64(i8 %b) { 248; CHECK-LABEL: lsl_zext_i8_i64: 249; CHECK: ; %bb.0: 250; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 251; CHECK-NEXT: ubfiz x0, x0, #4, #8 252; CHECK-NEXT: ret 253 %1 = zext i8 %b to i64 254 %2 = shl i64 %1, 4 255 ret i64 %2 256} 257 258define i64 @lsl_sext_i8_i64(i8 %b) { 259; CHECK-LABEL: lsl_sext_i8_i64: 260; CHECK: ; %bb.0: 261; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 262; CHECK-NEXT: sbfiz x0, x0, #4, #8 263; CHECK-NEXT: ret 264 %1 = sext i8 %b to i64 265 %2 = shl i64 %1, 4 266 ret i64 %2 267} 268 269define zeroext i16 @lslv_i16(i16 %a, i16 %b) { 270; CHECK-LABEL: lslv_i16: 271; CHECK: ; %bb.0: 272; CHECK-NEXT: and w8, w1, #0xffff 273; CHECK-NEXT: lsl w8, w0, w8 274; CHECK-NEXT: and w8, w8, #0xffff 275; CHECK-NEXT: uxth w0, w8 276; CHECK-NEXT: ret 277 %1 = shl i16 %a, %b 278 ret i16 %1 279} 280 281define zeroext i16 @lsl_i16(i16 %a) { 282; CHECK-LABEL: lsl_i16: 283; CHECK: ; %bb.0: 284; CHECK-NEXT: ubfiz w8, w0, #8, #8 285; CHECK-NEXT: uxth w0, w8 286; CHECK-NEXT: ret 287 %1 = shl i16 %a, 8 288 ret i16 %1 289} 290 291define i32 @lsl_zext_i16_i32(i16 %b) { 292; CHECK-LABEL: lsl_zext_i16_i32: 293; CHECK: ; %bb.0: 294; CHECK-NEXT: ubfiz w0, w0, #8, #16 295; CHECK-NEXT: ret 296 %1 = zext i16 %b to i32 297 %2 = shl i32 %1, 8 298 ret i32 %2 299} 300 301define i32 @lsl_sext_i16_i32(i16 %b) { 302; CHECK-LABEL: lsl_sext_i16_i32: 303; CHECK: ; %bb.0: 304; CHECK-NEXT: sbfiz w0, w0, #8, #16 305; CHECK-NEXT: ret 306 %1 = sext i16 %b to i32 307 %2 = shl i32 %1, 8 308 ret i32 %2 309} 310 311define i64 @lsl_zext_i16_i64(i16 %b) { 312; CHECK-LABEL: lsl_zext_i16_i64: 313; CHECK: ; %bb.0: 314; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 315; CHECK-NEXT: ubfiz x0, x0, #8, #16 316; CHECK-NEXT: ret 317 %1 = zext i16 %b to i64 318 %2 = shl i64 %1, 8 319 ret i64 %2 320} 321 322define i64 @lsl_sext_i16_i64(i16 %b) { 323; CHECK-LABEL: lsl_sext_i16_i64: 324; CHECK: ; %bb.0: 325; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 326; CHECK-NEXT: sbfiz x0, x0, #8, #16 327; CHECK-NEXT: ret 328 %1 = sext i16 %b to i64 329 %2 = shl i64 %1, 8 330 ret i64 %2 331} 332 333define zeroext i32 @lslv_i32(i32 %a, i32 %b) { 334; CHECK-LABEL: lslv_i32: 335; CHECK: ; %bb.0: 336; CHECK-NEXT: lsl w0, w0, w1 337; CHECK-NEXT: ret 338 %1 = shl i32 %a, %b 339 ret i32 %1 340} 341 342define zeroext i32 @lsl_i32(i32 %a) { 343; CHECK-LABEL: lsl_i32: 344; CHECK: ; %bb.0: 345; CHECK-NEXT: lsl w0, w0, #16 346; CHECK-NEXT: ret 347 %1 = shl i32 %a, 16 348 ret i32 %1 349} 350 351define i64 @lsl_zext_i32_i64(i32 %b) { 352; CHECK-LABEL: lsl_zext_i32_i64: 353; CHECK: ; %bb.0: 354; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 355; CHECK-NEXT: ubfiz x0, x0, #16, #32 356; CHECK-NEXT: ret 357 %1 = zext i32 %b to i64 358 %2 = shl i64 %1, 16 359 ret i64 %2 360} 361 362define i64 @lsl_sext_i32_i64(i32 %b) { 363; CHECK-LABEL: lsl_sext_i32_i64: 364; CHECK: ; %bb.0: 365; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 366; CHECK-NEXT: sbfiz x0, x0, #16, #32 367; CHECK-NEXT: ret 368 %1 = sext i32 %b to i64 369 %2 = shl i64 %1, 16 370 ret i64 %2 371} 372 373define i64 @lslv_i64(i64 %a, i64 %b) { 374; CHECK-LABEL: lslv_i64: 375; CHECK: ; %bb.0: 376; CHECK-NEXT: lsl x0, x0, x1 377; CHECK-NEXT: ret 378 %1 = shl i64 %a, %b 379 ret i64 %1 380} 381 382define i64 @lsl_i64(i64 %a) { 383; CHECK-LABEL: lsl_i64: 384; CHECK: ; %bb.0: 385; CHECK-NEXT: lsl x0, x0, #32 386; CHECK-NEXT: ret 387 %1 = shl i64 %a, 32 388 ret i64 %1 389} 390 391define zeroext i8 @lsrv_i8(i8 %a, i8 %b) { 392; CHECK-LABEL: lsrv_i8: 393; CHECK: ; %bb.0: 394; CHECK-NEXT: and w8, w0, #0xff 395; CHECK-NEXT: and w9, w1, #0xff 396; CHECK-NEXT: lsr w8, w8, w9 397; CHECK-NEXT: and w8, w8, #0xff 398; CHECK-NEXT: uxtb w0, w8 399; CHECK-NEXT: ret 400 %1 = lshr i8 %a, %b 401 ret i8 %1 402} 403 404define zeroext i8 @lsr_i8(i8 %a) { 405; CHECK-LABEL: lsr_i8: 406; CHECK: ; %bb.0: 407; CHECK-NEXT: ubfx w8, w0, #4, #4 408; CHECK-NEXT: uxtb w0, w8 409; CHECK-NEXT: ret 410 %1 = lshr i8 %a, 4 411 ret i8 %1 412} 413 414define zeroext i16 @lsr_zext_i8_i16(i8 %b) { 415; CHECK-LABEL: lsr_zext_i8_i16: 416; CHECK: ; %bb.0: 417; CHECK-NEXT: ubfx w8, w0, #4, #4 418; CHECK-NEXT: uxth w0, w8 419; CHECK-NEXT: ret 420 %1 = zext i8 %b to i16 421 %2 = lshr i16 %1, 4 422 ret i16 %2 423} 424 425define signext i16 @lsr_sext_i8_i16(i8 %b) { 426; CHECK-LABEL: lsr_sext_i8_i16: 427; CHECK: ; %bb.0: 428; CHECK-NEXT: sxtb w8, w0 429; CHECK-NEXT: ubfx w8, w8, #4, #12 430; CHECK-NEXT: sxth w0, w8 431; CHECK-NEXT: ret 432 %1 = sext i8 %b to i16 433 %2 = lshr i16 %1, 4 434 ret i16 %2 435} 436 437define i32 @lsr_zext_i8_i32(i8 %b) { 438; CHECK-LABEL: lsr_zext_i8_i32: 439; CHECK: ; %bb.0: 440; CHECK-NEXT: ubfx w0, w0, #4, #4 441; CHECK-NEXT: ret 442 %1 = zext i8 %b to i32 443 %2 = lshr i32 %1, 4 444 ret i32 %2 445} 446 447define i32 @lsr_sext_i8_i32(i8 %b) { 448; CHECK-LABEL: lsr_sext_i8_i32: 449; CHECK: ; %bb.0: 450; CHECK-NEXT: sxtb w8, w0 451; CHECK-NEXT: lsr w0, w8, #4 452; CHECK-NEXT: ret 453 %1 = sext i8 %b to i32 454 %2 = lshr i32 %1, 4 455 ret i32 %2 456} 457 458define zeroext i16 @lsrv_i16(i16 %a, i16 %b) { 459; CHECK-LABEL: lsrv_i16: 460; CHECK: ; %bb.0: 461; CHECK-NEXT: and w8, w0, #0xffff 462; CHECK-NEXT: and w9, w1, #0xffff 463; CHECK-NEXT: lsr w8, w8, w9 464; CHECK-NEXT: and w8, w8, #0xffff 465; CHECK-NEXT: uxth w0, w8 466; CHECK-NEXT: ret 467 %1 = lshr i16 %a, %b 468 ret i16 %1 469} 470 471define zeroext i16 @lsr_i16(i16 %a) { 472; CHECK-LABEL: lsr_i16: 473; CHECK: ; %bb.0: 474; CHECK-NEXT: ubfx w8, w0, #8, #8 475; CHECK-NEXT: uxth w0, w8 476; CHECK-NEXT: ret 477 %1 = lshr i16 %a, 8 478 ret i16 %1 479} 480 481define zeroext i32 @lsrv_i32(i32 %a, i32 %b) { 482; CHECK-LABEL: lsrv_i32: 483; CHECK: ; %bb.0: 484; CHECK-NEXT: lsr w0, w0, w1 485; CHECK-NEXT: ret 486 %1 = lshr i32 %a, %b 487 ret i32 %1 488} 489 490define zeroext i32 @lsr_i32(i32 %a) { 491; CHECK-LABEL: lsr_i32: 492; CHECK: ; %bb.0: 493; CHECK-NEXT: lsr w0, w0, #16 494; CHECK-NEXT: ret 495 %1 = lshr i32 %a, 16 496 ret i32 %1 497} 498 499define i64 @lsrv_i64(i64 %a, i64 %b) { 500; CHECK-LABEL: lsrv_i64: 501; CHECK: ; %bb.0: 502; CHECK-NEXT: lsr x0, x0, x1 503; CHECK-NEXT: ret 504 %1 = lshr i64 %a, %b 505 ret i64 %1 506} 507 508define i64 @lsr_i64(i64 %a) { 509; CHECK-LABEL: lsr_i64: 510; CHECK: ; %bb.0: 511; CHECK-NEXT: lsr x0, x0, #32 512; CHECK-NEXT: ret 513 %1 = lshr i64 %a, 32 514 ret i64 %1 515} 516 517define zeroext i8 @asrv_i8(i8 %a, i8 %b) { 518; CHECK-LABEL: asrv_i8: 519; CHECK: ; %bb.0: 520; CHECK-NEXT: sxtb w8, w0 521; CHECK-NEXT: and w9, w1, #0xff 522; CHECK-NEXT: asr w8, w8, w9 523; CHECK-NEXT: and w8, w8, #0xff 524; CHECK-NEXT: uxtb w0, w8 525; CHECK-NEXT: ret 526 %1 = ashr i8 %a, %b 527 ret i8 %1 528} 529 530define zeroext i8 @asr_i8(i8 %a) { 531; CHECK-LABEL: asr_i8: 532; CHECK: ; %bb.0: 533; CHECK-NEXT: sbfx w8, w0, #4, #4 534; CHECK-NEXT: uxtb w0, w8 535; CHECK-NEXT: ret 536 %1 = ashr i8 %a, 4 537 ret i8 %1 538} 539 540define zeroext i16 @asr_zext_i8_i16(i8 %b) { 541; CHECK-LABEL: asr_zext_i8_i16: 542; CHECK: ; %bb.0: 543; CHECK-NEXT: ubfx w8, w0, #4, #4 544; CHECK-NEXT: uxth w0, w8 545; CHECK-NEXT: ret 546 %1 = zext i8 %b to i16 547 %2 = ashr i16 %1, 4 548 ret i16 %2 549} 550 551define signext i16 @asr_sext_i8_i16(i8 %b) { 552; CHECK-LABEL: asr_sext_i8_i16: 553; CHECK: ; %bb.0: 554; CHECK-NEXT: sbfx w8, w0, #4, #4 555; CHECK-NEXT: sxth w0, w8 556; CHECK-NEXT: ret 557 %1 = sext i8 %b to i16 558 %2 = ashr i16 %1, 4 559 ret i16 %2 560} 561 562define i32 @asr_zext_i8_i32(i8 %b) { 563; CHECK-LABEL: asr_zext_i8_i32: 564; CHECK: ; %bb.0: 565; CHECK-NEXT: ubfx w0, w0, #4, #4 566; CHECK-NEXT: ret 567 %1 = zext i8 %b to i32 568 %2 = ashr i32 %1, 4 569 ret i32 %2 570} 571 572define i32 @asr_sext_i8_i32(i8 %b) { 573; CHECK-LABEL: asr_sext_i8_i32: 574; CHECK: ; %bb.0: 575; CHECK-NEXT: sbfx w0, w0, #4, #4 576; CHECK-NEXT: ret 577 %1 = sext i8 %b to i32 578 %2 = ashr i32 %1, 4 579 ret i32 %2 580} 581 582define zeroext i16 @asrv_i16(i16 %a, i16 %b) { 583; CHECK-LABEL: asrv_i16: 584; CHECK: ; %bb.0: 585; CHECK-NEXT: sxth w8, w0 586; CHECK-NEXT: and w9, w1, #0xffff 587; CHECK-NEXT: asr w8, w8, w9 588; CHECK-NEXT: and w8, w8, #0xffff 589; CHECK-NEXT: uxth w0, w8 590; CHECK-NEXT: ret 591 %1 = ashr i16 %a, %b 592 ret i16 %1 593} 594 595define zeroext i16 @asr_i16(i16 %a) { 596; CHECK-LABEL: asr_i16: 597; CHECK: ; %bb.0: 598; CHECK-NEXT: sbfx w8, w0, #8, #8 599; CHECK-NEXT: uxth w0, w8 600; CHECK-NEXT: ret 601 %1 = ashr i16 %a, 8 602 ret i16 %1 603} 604 605define zeroext i32 @asrv_i32(i32 %a, i32 %b) { 606; CHECK-LABEL: asrv_i32: 607; CHECK: ; %bb.0: 608; CHECK-NEXT: asr w0, w0, w1 609; CHECK-NEXT: ret 610 %1 = ashr i32 %a, %b 611 ret i32 %1 612} 613 614define zeroext i32 @asr_i32(i32 %a) { 615; CHECK-LABEL: asr_i32: 616; CHECK: ; %bb.0: 617; CHECK-NEXT: asr w0, w0, #16 618; CHECK-NEXT: ret 619 %1 = ashr i32 %a, 16 620 ret i32 %1 621} 622 623define i64 @asrv_i64(i64 %a, i64 %b) { 624; CHECK-LABEL: asrv_i64: 625; CHECK: ; %bb.0: 626; CHECK-NEXT: asr x0, x0, x1 627; CHECK-NEXT: ret 628 %1 = ashr i64 %a, %b 629 ret i64 %1 630} 631 632define i64 @asr_i64(i64 %a) { 633; CHECK-LABEL: asr_i64: 634; CHECK: ; %bb.0: 635; CHECK-NEXT: asr x0, x0, #32 636; CHECK-NEXT: ret 637 %1 = ashr i64 %a, 32 638 ret i64 %1 639} 640 641define i32 @shift_test1(i8 %a) { 642; CHECK-LABEL: shift_test1: 643; CHECK: ; %bb.0: 644; CHECK-NEXT: ubfiz w8, w0, #4, #4 645; CHECK-NEXT: sbfx w8, w8, #4, #4 646; CHECK-NEXT: sxtb w0, w8 647; CHECK-NEXT: ret 648 %1 = shl i8 %a, 4 649 %2 = ashr i8 %1, 4 650 %3 = sext i8 %2 to i32 651 ret i32 %3 652} 653 654; Test zero shifts 655 656define i32 @shl_zero(i32 %a) { 657; CHECK-LABEL: shl_zero: 658; CHECK: ; %bb.0: 659; CHECK-NEXT: ret 660 %1 = shl i32 %a, 0 661 ret i32 %1 662} 663 664define i32 @lshr_zero(i32 %a) { 665; CHECK-LABEL: lshr_zero: 666; CHECK: ; %bb.0: 667; CHECK-NEXT: ret 668 %1 = lshr i32 %a, 0 669 ret i32 %1 670} 671 672define i32 @ashr_zero(i32 %a) { 673; CHECK-LABEL: ashr_zero: 674; CHECK: ; %bb.0: 675; CHECK-NEXT: ret 676 %1 = ashr i32 %a, 0 677 ret i32 %1 678} 679 680define i64 @shl_zext_zero(i32 %a) { 681; CHECK-LABEL: shl_zext_zero: 682; CHECK: ; %bb.0: 683; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 684; CHECK-NEXT: lsr w0, w0, #0 685; CHECK-NEXT: ret 686 %1 = zext i32 %a to i64 687 %2 = shl i64 %1, 0 688 ret i64 %2 689} 690 691define i64 @lshr_zext_zero(i32 %a) { 692; CHECK-LABEL: lshr_zext_zero: 693; CHECK: ; %bb.0: 694; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 695; CHECK-NEXT: lsr w0, w0, #0 696; CHECK-NEXT: ret 697 %1 = zext i32 %a to i64 698 %2 = lshr i64 %1, 0 699 ret i64 %2 700} 701 702define i64 @ashr_zext_zero(i32 %a) { 703; CHECK-LABEL: ashr_zext_zero: 704; CHECK: ; %bb.0: 705; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0 706; CHECK-NEXT: lsr w0, w0, #0 707; CHECK-NEXT: ret 708 %1 = zext i32 %a to i64 709 %2 = ashr i64 %1, 0 710 ret i64 %2 711} 712 713