xref: /llvm-project/llvm/test/CodeGen/AArch64/fabs-combine.ll (revision 6c84709eff20460a75fb58d2face54432c133967)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4; Test against PR36600: https://bugs.llvm.org/show_bug.cgi?id=36600
5; This is not fabs. If X = -0.0, it should return -0.0 not 0.0.
6
7define double @not_fabs(double %x) #0 {
8; CHECK-LABEL: not_fabs:
9; CHECK:       // %bb.0:
10; CHECK-NEXT:    fneg d1, d0
11; CHECK-NEXT:    fcmp d0, #0.0
12; CHECK-NEXT:    fcsel d0, d1, d0, le
13; CHECK-NEXT:    ret
14  %cmp = fcmp nnan ole double %x, 0.0
15  %sub = fsub nnan double -0.0, %x
16  %cond = select i1 %cmp, double %sub, double %x
17  ret double %cond
18}
19
20; Try again with different type, predicate, and compare constant.
21
22define float @still_not_fabs(float %x) #0 {
23; CHECK-LABEL: still_not_fabs:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    movi v1.2s, #128, lsl #24
26; CHECK-NEXT:    fneg s2, s0
27; CHECK-NEXT:    fcmp s0, s1
28; CHECK-NEXT:    fcsel s0, s0, s2, ge
29; CHECK-NEXT:    ret
30  %cmp = fcmp nnan oge float %x, -0.0
31  %sub = fsub nnan float -0.0, %x
32  %cond = select i1 %cmp, float %x, float %sub
33  ret float %cond
34}
35
36define float @nabsf(float %a) {
37; CHECK-LABEL: nabsf:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    fabs s0, s0
40; CHECK-NEXT:    fneg s0, s0
41; CHECK-NEXT:    ret
42  %conv = bitcast float %a to i32
43  %and = or i32 %conv, -2147483648
44  %conv1 = bitcast i32 %and to float
45  ret float %conv1
46}
47
48define double @nabsd(double %a) {
49; CHECK-LABEL: nabsd:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    fabs d0, d0
52; CHECK-NEXT:    fneg d0, d0
53; CHECK-NEXT:    ret
54  %conv = bitcast double %a to i64
55  %and = or i64 %conv, -9223372036854775808
56  %conv1 = bitcast i64 %and to double
57  ret double %conv1
58}
59
60define <4 x float> @nabsv4f32(<4 x float> %a) {
61; CHECK-LABEL: nabsv4f32:
62; CHECK:       // %bb.0:
63; CHECK-NEXT:    orr v0.4s, #128, lsl #24
64; CHECK-NEXT:    ret
65  %conv = bitcast <4 x float> %a to <4 x i32>
66  %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
67  %conv1 = bitcast <4 x i32> %and to <4 x float>
68  ret <4 x float> %conv1
69}
70
71define <2 x double> @nabsv2d64(<2 x double> %a) {
72; CHECK-LABEL: nabsv2d64:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    movi v1.2d, #0000000000000000
75; CHECK-NEXT:    fneg v1.2d, v1.2d
76; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
77; CHECK-NEXT:    ret
78  %conv = bitcast <2 x double> %a to <2 x i64>
79  %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>
80  %conv1 = bitcast <2 x i64> %and to <2 x double>
81  ret <2 x double> %conv1
82}
83
84attributes #0 = { "no-nans-fp-math"="true" }
85
86