xref: /llvm-project/llvm/test/CodeGen/AArch64/extractvector-of-load.mir (revision c02b0d008c17cdf8dc46ad930c69311bcd8c7dd4)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            f
6alignment:       4
7tracksRegLiveness: true
8registers:
9  - { id: 0, class: _ }
10  - { id: 1, class: _ }
11  - { id: 2, class: _ }
12  - { id: 3, class: _ }
13  - { id: 4, class: _ }
14  - { id: 5, class: _ }
15liveins:
16  - { reg: '$x0' }
17frameInfo:
18  maxAlignment:    1
19machineFunctionInfo: {}
20body:             |
21  bb.0:
22    liveins: $x0
23
24    ; CHECK-LABEL: name: f
25    ; CHECK: liveins: $x0
26    ; CHECK-NEXT: {{  $}}
27    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
28    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
29    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
30    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
31    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
32    ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>))
33    ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LOAD]](<2 x s32>), [[C1]](s64)
34    ; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
35    ; CHECK-NEXT: RET_ReallyLR implicit $w0
36    %0:_(p0) = COPY $x0
37    %3:_(s32) = G_CONSTANT i32 0
38    %2:_(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32)
39    %5:_(s64) = G_CONSTANT i64 0
40    %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
41    G_STORE %2(<4 x s32>), %0(p0) :: (store (<4 x s32>))
42    %4:_(s32) = G_EXTRACT_VECTOR_ELT %1(<2 x s32>), %5(s64)
43    $w0 = COPY %4(s32)
44    RET_ReallyLR implicit $w0
45
46...
47