1; RUN: llc -mtriple=arm64 -o - %s -mcpu=cyclone | FileCheck %s 2; RUN: llc -mtriple=arm64 -o - %s -O0 -fast-isel -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST 3 4@var8 = external dso_local global i8, align 1 5@var16 = external dso_local global i16, align 2 6@var32 = external dso_local global i32, align 4 7@var64 = external dso_local global i64, align 8 8 9define i8 @test_i8(i8 %new) { 10 %val = load i8, ptr @var8, align 1 11 store i8 %new, ptr @var8 12 ret i8 %val 13; CHECK-LABEL: test_i8: 14; CHECK: adrp x[[HIREG:[0-9]+]], var8 15; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 16; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 17 18; CHECK-FAST-LABEL: test_i8: 19; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8 20; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 21} 22 23define i16 @test_i16(i16 %new) { 24 %val = load i16, ptr @var16, align 2 25 store i16 %new, ptr @var16 26 ret i16 %val 27; CHECK-LABEL: test_i16: 28; CHECK: adrp x[[HIREG:[0-9]+]], var16 29; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 30; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 31 32; CHECK-FAST-LABEL: test_i16: 33; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16 34; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 35} 36 37define i32 @test_i32(i32 %new) { 38 %val = load i32, ptr @var32, align 4 39 store i32 %new, ptr @var32 40 ret i32 %val 41; CHECK-LABEL: test_i32: 42; CHECK: adrp x[[HIREG:[0-9]+]], var32 43; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] 44; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] 45 46; CHECK-FAST-LABEL: test_i32: 47; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32 48; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32 49} 50 51define i64 @test_i64(i64 %new) { 52 %val = load i64, ptr @var64, align 8 53 store i64 %new, ptr @var64 54 ret i64 %val 55; CHECK-LABEL: test_i64: 56; CHECK: adrp x[[HIREG:[0-9]+]], var64 57; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] 58; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] 59 60; CHECK-FAST-LABEL: test_i64: 61; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64 62; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64 63} 64 65define ptr @test_addr() { 66 ret ptr @var64 67; CHECK-LABEL: test_addr: 68; CHECK: adrp [[HIREG:x[0-9]+]], var64 69; CHECK: add x0, [[HIREG]], :lo12:var64 70 71; CHECK-FAST-LABEL: test_addr: 72; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64 73; CHECK-FAST: add x0, [[HIREG]], :lo12:var64 74} 75 76@var_default = external dso_local global [2 x i32] 77 78define i32 @test_default_align() { 79 %val = load i32, ptr @var_default 80 ret i32 %val 81; CHECK-LABEL: test_default_align: 82; CHECK: adrp x[[HIREG:[0-9]+]], var_default 83; CHECK: ldr w0, [x[[HIREG]], :lo12:var_default] 84} 85 86define i64 @test_default_unaligned() { 87 %val = load i64, ptr @var_default 88 ret i64 %val 89; CHECK-LABEL: test_default_unaligned: 90; CHECK: adrp [[HIREG:x[0-9]+]], var_default 91; CHECK: add x[[ADDR:[0-9]+]], [[HIREG]], :lo12:var_default 92; CHECK: ldr x0, [x[[ADDR]]] 93} 94