1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-unknown | FileCheck %s 3 4; PR32273 5 6define void @signbits_vXi1(<4 x i16> %a1) { 7; CHECK-LABEL: signbits_vXi1: 8; CHECK: // %bb.0: 9; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 10; CHECK-NEXT: adrp x8, .LCPI0_0 11; CHECK-NEXT: mov w1, wzr 12; CHECK-NEXT: mov w2, wzr 13; CHECK-NEXT: dup v0.4h, v0.h[0] 14; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0] 15; CHECK-NEXT: add v0.4h, v0.4h, v1.4h 16; CHECK-NEXT: cmle v0.4h, v0.4h, #0 17; CHECK-NEXT: umov w0, v0.h[0] 18; CHECK-NEXT: umov w3, v0.h[3] 19; CHECK-NEXT: b foo 20 %tmp3 = shufflevector <4 x i16> %a1, <4 x i16> undef, <4 x i32> zeroinitializer 21 %tmp5 = add <4 x i16> %tmp3, <i16 18249, i16 6701, i16 -18744, i16 -25086> 22 %tmp6 = icmp slt <4 x i16> %tmp5, <i16 1, i16 1, i16 1, i16 1> 23 %tmp7 = and <4 x i1> %tmp6, <i1 true, i1 false, i1 false, i1 true> 24 %tmp8 = sext <4 x i1> %tmp7 to <4 x i16> 25 %tmp9 = extractelement <4 x i16> %tmp8, i32 0 26 %tmp10 = zext i16 %tmp9 to i32 27 %tmp11 = extractelement <4 x i16> %tmp8, i32 1 28 %tmp12 = zext i16 %tmp11 to i32 29 %tmp13 = extractelement <4 x i16> %tmp8, i32 2 30 %tmp14 = zext i16 %tmp13 to i32 31 %tmp15 = extractelement <4 x i16> %tmp8, i32 3 32 %tmp16 = zext i16 %tmp15 to i32 33 tail call void @foo(i32 %tmp10, i32 %tmp12, i32 %tmp14, i32 %tmp16) 34 ret void 35} 36 37declare void @foo(i32, i32, i32, i32) 38