xref: /llvm-project/llvm/test/CodeGen/AArch64/dag-combine-mul-shl.ll (revision a815578c31775f3bca57a6ede65787aa152bafbd) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
3
4define <16 x i8> @fn1_vector(<16 x i8> %arg) {
5; CHECK-LABEL: fn1_vector:
6; CHECK:       // %bb.0: // %entry
7; CHECK-NEXT:    adrp x8, .LCPI0_0
8; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
9; CHECK-NEXT:    mul v0.16b, v0.16b, v1.16b
10; CHECK-NEXT:    ret
11entry:
12  %shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
13  %mul = mul <16 x i8> %shl, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
14  ret <16 x i8> %mul
15}
16
17define <16 x i8> @fn2_vector(<16 x i8> %arg) {
18; CHECK-LABEL: fn2_vector:
19; CHECK:       // %bb.0: // %entry
20; CHECK-NEXT:    adrp x8, .LCPI1_0
21; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
22; CHECK-NEXT:    mul v0.16b, v0.16b, v1.16b
23; CHECK-NEXT:    ret
24entry:
25  %mul = mul <16 x i8> %arg, <i8 0, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
26  %shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
27  ret <16 x i8> %shl
28}
29
30define <16 x i8> @fn1_vector_undef(<16 x i8> %arg) {
31; CHECK-LABEL: fn1_vector_undef:
32; CHECK:       // %bb.0: // %entry
33; CHECK-NEXT:    adrp x8, .LCPI2_0
34; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
35; CHECK-NEXT:    mul v0.16b, v0.16b, v1.16b
36; CHECK-NEXT:    ret
37entry:
38  %shl = shl <16 x i8> %arg, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
39  %mul = mul <16 x i8> %shl, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
40  ret <16 x i8> %mul
41}
42
43define <16 x i8> @fn2_vector_undef(<16 x i8> %arg) {
44; CHECK-LABEL: fn2_vector_undef:
45; CHECK:       // %bb.0: // %entry
46; CHECK-NEXT:    adrp x8, .LCPI3_0
47; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
48; CHECK-NEXT:    mul v0.16b, v0.16b, v1.16b
49; CHECK-NEXT:    ret
50entry:
51  %mul = mul <16 x i8> %arg, <i8 undef, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
52  %shl = shl <16 x i8> %mul, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
53  ret <16 x i8> %shl
54}
55
56define i32 @fn1_scalar(i32 %arg) {
57; CHECK-LABEL: fn1_scalar:
58; CHECK:       // %bb.0: // %entry
59; CHECK-NEXT:    mov w8, #1664
60; CHECK-NEXT:    mul w0, w0, w8
61; CHECK-NEXT:    ret
62entry:
63  %shl = shl i32 %arg, 7
64  %mul = mul i32 %shl, 13
65  ret i32 %mul
66}
67
68define i32 @fn2_scalar(i32 %arg) {
69; CHECK-LABEL: fn2_scalar:
70; CHECK:       // %bb.0: // %entry
71; CHECK-NEXT:    mov w8, #1664
72; CHECK-NEXT:    mul w0, w0, w8
73; CHECK-NEXT:    ret
74entry:
75  %mul = mul i32 %arg, 13
76  %shl = shl i32 %mul, 7
77  ret i32 %shl
78}
79
80define i32 @fn1_scalar_undef(i32 %arg) {
81; CHECK-LABEL: fn1_scalar_undef:
82; CHECK:       // %bb.0: // %entry
83; CHECK-NEXT:    mov w0, wzr
84; CHECK-NEXT:    ret
85entry:
86  %shl = shl i32 %arg, 7
87  %mul = mul i32 %shl, undef
88  ret i32 %mul
89}
90
91define i32 @fn2_scalar_undef(i32 %arg) {
92; CHECK-LABEL: fn2_scalar_undef:
93; CHECK:       // %bb.0: // %entry
94; CHECK-NEXT:    mov w0, wzr
95; CHECK-NEXT:    ret
96entry:
97  %mul = mul i32 %arg, undef
98  %shl = shl i32 %mul, 7
99  ret i32 %shl
100}
101
102define i32 @fn1_scalar_opaque(i32 %arg) {
103; CHECK-LABEL: fn1_scalar_opaque:
104; CHECK:       // %bb.0: // %entry
105; CHECK-NEXT:    mov w8, #13
106; CHECK-NEXT:    mul w8, w0, w8
107; CHECK-NEXT:    lsl w0, w8, #7
108; CHECK-NEXT:    ret
109entry:
110  %bitcast = bitcast i32 13 to i32
111  %shl = shl i32 %arg, 7
112  %mul = mul i32 %shl, %bitcast
113  ret i32 %mul
114}
115
116define i32 @fn2_scalar_opaque(i32 %arg) {
117; CHECK-LABEL: fn2_scalar_opaque:
118; CHECK:       // %bb.0: // %entry
119; CHECK-NEXT:    mov w8, #13
120; CHECK-NEXT:    mul w8, w0, w8
121; CHECK-NEXT:    lsl w0, w8, #7
122; CHECK-NEXT:    ret
123entry:
124  %bitcast = bitcast i32 13 to i32
125  %mul = mul i32 %arg, %bitcast
126  %shl = shl i32 %mul, 7
127  ret i32 %shl
128}
129