xref: /llvm-project/llvm/test/CodeGen/AArch64/ctlz_zero_undef.ll (revision 69192e0193e60c169c7776f444362dffba31eb7d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc < %s --mtriple=aarch64 | FileCheck %s
3
4declare i8 @llvm.ctlz.i8(i8, i1 immarg)
5declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1 immarg)
6declare i11 @llvm.ctlz.i11(i11, i1 immarg)
7
8define i32 @clz_nzu8(i8 %self) {
9; CHECK-LABEL: clz_nzu8:
10; CHECK:       // %bb.0: // %start
11; CHECK-NEXT:    lsl w8, w0, #24
12; CHECK-NEXT:    clz w0, w8
13; CHECK-NEXT:    ret
14start:
15  %ctlz_res = call i8 @llvm.ctlz.i8(i8 %self, i1 true)
16  %ret = zext i8 %ctlz_res to i32
17  ret i32 %ret
18}
19
20; non standard bit size argument to ctlz
21define i32 @clz_nzu11(i11 %self) {
22; CHECK-LABEL: clz_nzu11:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    lsl w8, w0, #21
25; CHECK-NEXT:    clz w0, w8
26; CHECK-NEXT:    ret
27  %ctlz_res = call i11 @llvm.ctlz.i11(i11 %self, i1 true)
28  %ret = zext i11 %ctlz_res to i32
29  ret i32 %ret
30}
31
32; vector type argument to ctlz intrinsic
33define <8 x i32> @clz_vec_nzu8(<8 x i8> %self) {
34; CHECK-LABEL: clz_vec_nzu8:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    clz v0.8b, v0.8b
37; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
38; CHECK-NEXT:    ushll2 v1.4s, v0.8h, #0
39; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
40; CHECK-NEXT:    ret
41  %ctlz_res = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %self, i1 true)
42  %ret = zext <8 x i8> %ctlz_res to <8 x i32>
43  ret <8 x i32> %ret
44}
45